ncr810.h

IXP425的BSP代码

/* SXFER */

#define    SXFER_TP2     0x80	/* Synchronous transfer period 2 */
#define    SXFER_TP1     0x40	/* Synchronous transfer period 1 */
#define    SXFER_TP0     0x20	/* Synchronous transfer period 0 */
#define    SXFER_MO3     0x08	/* Maximun scsi Synchronous transfer offset */
#define    SXFER_MO2     0x04	/* Maximun scsi Synchronous transfer offset */
#define    SXFER_MO1     0x02	/* Maximun scsi Synchronous transfer offset */
#define    SXFER_MO0     0x01	/* Maximun scsi Synchronous transfer offset */
#define    SXFER_OFFSET  0x0f

/* SDID */

#define    SDID_ENC2     0x04   /* Destination SCSI ID bit 2 */
#define    SDID_ENC1     0x02   /* Destination SCSI ID bit 1 */
#define    SDID_ENC0     0x01   /* Destination SCSI ID bit 0 */
#define    SDID_ENC_MASK 0x07	   /* The Encoded SCSI ID mask */

/* GPREG */

/* ??? */

/* SFBR */

/* No need to specify bits */

/*  SOCL (RW) and SBCL (RO not latched) */

#define    B_REQ     0x80	/* Assert scsi req */
#define    B_ACK     0x40	/* Assert scsi ack */
#define    B_BSY     0x20	/* Assert scsi busy */

/*#define    B_SEL     0x10*/	/* Assert scsi sel */

#define    B_ATN     0x08	/* Assert scsi atn */
#define    B_MSG     0x04	/* Assert scsi msg */
#define    B_CD      0x02	/* Assert scsi c/d */
#define    B_IO      0x01	/* Assert scsi i/o */

/* SSID */

#define    SSID_VAL  0x80	/* SCSI Valid Bit. ENID is valid only if this
				   bit is set. */

#define    SSID_ENC_MASK_7 0x07  /* Binary encoded SCSI ID mask 0-7 */
#define    SSID_ENC_MASK_F 0x0F  /* Binary encoded SCSI ID mask 0-15 */

#if (SCSI_MAX_BUS_ID == SCSI_MAX_BUS_ID_7)
   #define    SSID_ENC_MASK   SSID_ENC_MASK_7 /* SCSI ID mask 0-7 */
#else
   #define    SSID_ENC_MASK   SSID_ENC_MASK_F /* SCSI ID mask 0-15 */
#endif

/* DSTAT (RO) and DIEN (RW enable intr) */

#define    B_DFE     0x80	/* Dma fifo empty */
#define    B_MDPE    0x40       /* Master Data Parity Error */
#define    B_BF      0x20	/* Bus Fault */
#define    B_ABT     0x10	/* Abort condition */
#define    B_SSI     0x08	/* Scsi Step Interrupt */
#define    B_SIR     0x04	/* Script Interrupt received */
#define    B_IID     0x01	/* Illegal Instruction Detected */

/* SSTAT0 */

#define    SSTAT0_ILF 0x80      /* SIDL Input Latch Full */
#define    SSTAT0_ORF 0x40      /* SODR Output Register Full */
#define    SSTAT0_OLF 0x20      /* SODL Output Latch Full */
#define    SSTAT0_AIP 0x10      /* Arbitration In Progress */ 
#define    SSTAT0_LOA 0x01      /* LOst Arbitration */
#define    SSTAT0_WOA 0x02	/* WOn Arbitration */
#define    SSTAT0_RST 0x04    	/* SCSI ReSeT signal in the ISTAT register */
#define    SSTAT0_SDP 0x08 	/* SCSI SDP/ parity signal */

/* SSTAT1 RO register */

#define    SSTAT1_FF3     0x80	/* Fifo flag 3 :number of bytes in fifo */
#define    SSTAT1_FF2     0x40	/* Fifo flag 2 :number of bytes in fifo */
#define    SSTAT1_FF1     0x20	/* Fifo flag 1 :number of bytes in fifo */
#define    SSTAT1_FF0     0x10	/* Fifo flag 0 :number of bytes in fifo */
				/* 0000=0 ..... 1000=8 */
#define    SSTAT1_SPDL    0x08	/* Latched parity line */
#define    SSTAT1_MSGL    0x04	/* Latched state of MSG line */
#define    SSTAT1_CDL     0x02	/* Latched state of C/D line */
#define    SSTAT1_IOL     0x01	/* Latched sate of IO line */
#define    FIFO_MASK      0xf0

/* SSTAT2 */

#define    SSTAT2_ILF  0x80     /* SIDL MSB full */
#define    SSTAT2_ORF  0x40     /* SODR MSB full */
#define    SSTAT2_OLF  0x20     /* SODL MSB full */
#define    SSTAT2_FF4  0x10     /* FIFO flags bit 4 */
#define    SSTAT2_SPL  0x08     /* Latched SCSI Parity */
#define    SSTAT2_DSP  0x04     /* differential sense pin */
#define    SSTAT2_LDSC 0x02 	/* Last Disconnect; used in conjunction with
				   CON bit in SCNTL1 */
#define    SSTAT2_SDP  0x01 	/* SCSI SDP/ parity signal */


/* ISTAT RW register */

#define    ISTAT_ABRT    0x80	/* Abort operation */
#define    ISTAT_SOFTRST 0x40	/* Soft chip reset */
#define    ISTAT_SIGP    0x20	/* signal process */
#define    ISTAT_SEM     0x10  	/* Semaphore */
#define    ISTAT_CON     0x08	/* stat connected (reset doesn't disconnect) */
#define    ISTAT_INTF    0x04  	/* set by INTFLY script instruction. Signals 
				   ISRs while scripts are still running     */
#define    ISTAT_SIP     0x02	/* SCSI Interrupt Pending */
#define    ISTAT_DIP     0x01	/* Dma Interrupt Pending */

/* CTEST1 */

/* 
 * FMT? bits define the bottom bytes in the FIFO that are empty. ? specifies
 * the byte lane number. If byte lane3 is empty then FMT3 bit is set. All
 * 1's indicate an empty FIFO.
 */

#define    CTEST1_FMT3   0x80	/* Byte lane 3 empty? */
#define    CTEST1_FMT2   0x40	/* Byte lane 2 empty? */
#define    CTEST1_FMT1   0x20	/* Byte lane 1 empty? */
#define    CTEST1_FMT0   0x10	/* Byte lane 0 empty? */

/*
 * FFL? bits define the top bytes in the FIFO that are full. ? specifies the
 * byte lane number. If byte lane3 is full then FFL3 is set. All 1's indicate
 * a full FIFO.
 */

#define    CTEST1_FFL3   0x08	/* Byte lane 3 full? */
#define    CTEST1_FFL2   0x04	/* Byte lane 2 full? */
#define    CTEST1_FFL1   0x02	/* Byte lane 1 full? */
#define    CTEST1_FFL0   0x01	/* Byte lane 0 full? */

/* CTEST2 */

#define    CTEST2_DDIR   0x80 	/* Data Direction. 1 => From SCSI to board */
#define    CTEST2_SIGP   0x40	/* Signal Process. Same as in ISTAT. When this
				   register is read SIGP is cleared in ISTAT */
#define    CTEST2_CIO	 0x20   /* Configured as I/O XXX ??? */
#define    CTEST2_CM     0x10	/* Configured as Memory XXX ??? */
#define    CTEST2_TEOP   0x04   /* SCSI true end of process */
#define    CTEST2_DREQ   0x02 	/* 1 => DREQ is active */
#define    CTEST_DACK    0x01 	/* 1 => DACK is inactive */

/* CTEST3 */

#define    CTEST3_V3      0x80	/* Chip Revision Bit 3 */
#define    CTEST3_V2      0x40	/* Chip Revision Bit 2 */
#define    CTEST3_V1      0x20	/* Chip Revision Bit 1 */
#define    CTEST3_V0      0x10	/* Chip Revision Bit 0 */
#define    CTEST3_FLF     0x08	/* Flush DMA FIFO */
#define    CTEST3_CLF     0x04	/* Clear DMA FIFO */
#define    CTEST3_FM      0x02	/* Fetch Pin mode */
#define    CTEST3_WRIE    0x01 	/* Write and Invalidate Enable */

/* DFIFO */

#define    DFIFO_BO_MASK  0x7f  /* 7 bits of SCSI Byte Offset counter between 
				   SCSI core and DMA core */

/* CTEST4 */

#define    CTEST4_BDIS    0x80	/* Burst transfer DISable */
#define    CTEST4_ZMOD    0x40	/* Host bus high impedance mode  */
#define    CTEST4_SZD     0x20	/* Scsi data high impedance mode */
#define    CTEST4_SRTM    0x10	/* Shadow Register Test Mode */
#define    CTEST4_MPEE    0x08	/* Master Parity Error Enable */
#define    CTEST4_FBL2    0x04	/* Enable bytes lane */
#define    CTEST4_FLB1    0x02	/* Bit one mux byte lane */
#define    CTEST4_FLB0    0x01	/* Bit zero mux byte lane */

/* CTEST5 */

#define    CTEST5_ADCK    0x80	/* Increment DNAD register */
#define    CTEST5_BBCK    0x40	/* Decrement DBC register */
#define    CTEST5_DFS     0x20  /* DMA FIFO Size: 0=88, 1=536 bytes */
#define    CTEST5_MASR    0x10	/* set/reset values for bit 3 */
#define    CTEST5_DDIR    0x08	/* control internel DMAWR (scsi to host) */
#define    CTEST5_EOP     0x04	/* control internal EOP (DMA/SCSI) */
#define    CTEST5_DREQ    0x02	/* control internal DREQ */
#define    CTEST5_DACK    0x01	/* control internal DACK (DMA/SCSI) */

/* CTEST6 */

#define    CTEST6_DF_MASK 0xff 	/* Dma Fifo bits - mask */

/* DMODE RW register */

#define    DMODE_BL1     0x80	/* Burst Length transfer bits; determine the */
#define    DMODE_BL0     0x40	/* number of transfers per bus ownership */
				/* 00=2,01=4,10=8,11=16 */
#define    DMODE_SIOM    0x20	/* Source I/O Memory Enable; 1 => I/O space */
#define    DMODE_DIOM    0x10 	/* Destination I/O Memory Enable; "  "  "   */
#define    DMODE_ERL     0x08	/* Enable Read Line; */
#define    DMODE_ERMP    0x04	/* Enable Read Multiple */
#define    DMODE_BOF     0x02	/* Burst Opcode Fetch enable; instrs fetched 
				   in burst mode */
#define    DMODE_MAN     0x01	/* Manual start mode ,when set disable */
				/* autostart script when writting in DSP */

/* DCNTL - DMA Control bits */

#define    DCNTL_CLSE    0x80	/* Cache Line Size Enable */
#define    DCNTL_PFF     0x40   /* Pre-Fetch Flush */
#define    DCNTL_PFEN    0x20   /* Pre-Fetch ENable */ 
#define    DCNTL_SSM     0x10  	/* Single-Step Mode */
#define    DCNTL_IRQM    0x08	/* IRQ Mode */
#define    DCNTL_STD     0x04  	/* STart Dma operation; instr. is in DSP */
#define    DCNTL_IRQD    0x02	/* IRQ Disable; 1 => IRQ/ wont be asserted */
#define    DCNTL_COM     0x01 	/* Compatability XXX ??? 1 => ncr700 mode ?? */

/* SIEN0 (enable intr)and SIST0 (RO Status) */

/* Enable interrupt */

#define    B_MA      0x80	/* Phase Mismatch; initiator interrupt occurs */
#define    B_CMP     0x40	/* Funtion CoMPlete; interrupt when full 
				   arbitration and selection is complete */
#define    B_SEL     0x20	/* Selected; intr when selected as target */
#define    B_RSL     0x10	/* Reselected; intr when reselected */
#define    B_SGE     0x08	/* SCSI Gross Error; intr enable */
#define    B_UDC     0x04	/* Enable Unexpected Disconnect intr */
#define    B_RST     0x02	/* Enable Reset intr */
#define    B_PAR     0x01	/* Enable parity intr */

/* SIEN1 (enable intr) and SIST1 (RO status) */

#define    B_STO     0x04	/* Selection/Reselection Timeout; intr enable */
#define    B_GEN     0x02	/* GENeral purpose timer expired; intr enable */
#define    B_HTH     0x01	/* Handshake to Handshake timer expired; intr */

/* MACNTL - Memory Access Control (RW) */

#define    MACNTL_TYP_MASK 0xf0	/* Identify the chip TYPe */
#define    MACNTL_DWR      0x08	/* Data WRite is local memeory access */
#define    MACNTL_DRD      0x04	/* Data ReaD is local memory access */
#define    MACNTL_PSCPT    0x02	/* Pointer to SCRIPTs is local mem access */
#define    MACNTL_SCPTS    0x01	/* SCRIPTS fetch is local mem access */

/* GPCNTL - General Purpose Pin Control (RW) */

/* This reg is used to determine if GPREG pins are inputs or outputs */

#define    GPCNTL_ME    0x80	/* Master Enable; internal bus master is GPIO1*/
#define    GPCNTL_FE    0x40	/* Fetch Enable; internal op-code fetch GPIO0 */
#define    GPCNTL_GPIO1 0x02 	/* GPIO1: set - input and reset - output */
#define    GPCNTL_GPIO0 0x01 	/* GPIO0: set - input and reset - output */

/* STIME0  SCSI Timer Zero (RW) */

/* These bits select various timeout values.e.g 0000 => disable; 1111 => 1.6s */

#define    STIME0_HTH_MASK 0xf0	/* Handshake-To-Handshake timer period mask */
#define    STIME0_SEL_MASK 0x0f	/* SELection timeout mask */

/* STIME1 SCSI Timer One (RW) */

#define    STIME1_GEN_MASK 0x0f	/* GENeral timer timeout mask */

/* STEST0 SCSI Test Zero (RO) */

#define  STEST0_SSAID_MASK 0x70	/* SCSI Selected As ID */
#define  STEST0_SLT        0x08	/* Selection response logic test */
#define  STEST0_ART	   0x04	/* Arbitation Priority encoder Test */
#define  STEST0_SOZ	   0x02	/* SCSI Synchronous Offset Zero */
#define  STEST0_SOM	   0x01	/* SCSI Synchronous Offset Maximum */

/* STEST1 SCSI Test One (RW) */

#define     STEST1_SCLK  0x80	/* Disables external SCLK and uses PCI internal
				   SCSI clock */
#define     STEST1_SISO	 0x40	/* SCSI Isolation Mode; inputs isolated from
	    			   the SCSI bus */
#define     STEST1_QEN   0x08   /* Quadrupler Enable: Power on clock Quadrupler */