ncr810.h

IXP425的BSP代码

/* ncr810.h - NCR 810 Script SCSI Controller header file */

/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,03dec98,ihw  Added identMsg{Buf,Length} in NCR810_SCSI_CTRL, to
                 support concatenated IDENTIFY/{SYNC,WIDE} messages. (SRP 24089)
01f,25jun98,ldt  Added definitions for Quadrupler, STEST4, scratch 
                 registers c-j, 895 device id, 50,70,160 MHz speeds
            	 added siopRamBaseAdrs, updated ncr810CtrlCreate (SPR 24089)
01e,23apr98,tm,  Added SSTAT2, CTEST5_DFS definitions for SPR 8384 fix
01d,08may97,dat  temp fix for SPR 8540
01c,10mar97,dds  SPR 7766: added changes for ncr875 SCSI adapter.
01b,21nov96,myz  modified PCI_TO_MEM_OFFSET for i960jx 
01a,26may95,jds  Created ; adapted from ncr710.h
*/

#ifndef __INCncr810h
#define __INCncr810h

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "semLib.h"
#include "scsiLib.h"

/* PRIVATE */

typedef struct ncr810Thread 	    	/* NCR810_THREAD */
    {
    SCSI_THREAD           scsiThread;	/* generic SCSI thread structure */
    struct ncr810Shared * pShMem;	/* ptr to SIOP shared data area */
    
    /*
     *	The following is a partial context of the SIOP registers which is
     *	maintained independently for each thread.  It is saved and
     *	restored by the host when scripts are started and completed.
     *
     *	See "ncr810Script.h" for aliases for the scratch registers ...
     */

    UINT8 scratcha0;		/* image of scratch 0 register */
    UINT8 scratcha1;		/* image of scratch 1 register */
    UINT8 scratcha2;		/* image of scratch 2 register */
    UINT8 scratcha3;		/* image of scratch 3 register */
    UINT8 sxfer;		/* image of sxfer register */
    UINT8 scntl3;		/* image of scntl3 for sync xfers */
    } NCR810_THREAD;


typedef struct ncr810Event  	    	/* NCR810_EVENT */
    {
    SCSI_EVENT scsiEvent;   	 	/* generic SCSI event */
    UINT       remCount;	 	/* remaining byte count (mismatch) */
    } NCR810_EVENT;

/* Script entry point identifiers (see "ncr810StartScript()" if changed) */

typedef enum ncr810ScriptEntry
    {
    NCR810_SCRIPT_WAIT           = 0,	/* wait for re-select or host cmd */
    NCR810_SCRIPT_INIT_START     = 1,	/* start an initiator thread      */
    NCR810_SCRIPT_INIT_CONTINUE  = 2,	/* continue an initiator thread   */
    NCR810_SCRIPT_TGT_DISCONNECT = 3	/* disconnect a target thread     */
    } NCR810_SCRIPT_ENTRY;


/* SIOP state enumeration */

typedef enum ncr810State
    {
    NCR810_STATE_IDLE = 0,		/* not running any script            */
    NCR810_STATE_PASSIVE,		/* waiting for reselect or host cmd  */
    NCR810_STATE_ACTIVE			/* running a client script           */
    } NCR810_STATE;


/*
 * Structure used in the ncr810SetHwRegister() and ncr810GetHwRegister().
 * This is used to try to handle the possible different hardware
 * implementations of the chip.  This structure must contain the logical
 * value one wishes e.g 0 sets register bit to zero  and 1 sets to one.
 */

typedef struct
    {
    int stest1Bit7;		/* Disable external SCSI clock 	*/
    int stest2Bit7;		/* SCSI control enable		*/
    int stest2Bit5;		/* Enable differential SCSI bus	*/
    int stest2Bit2;		/* Always WIDE SCSI		*/
    int stest2Bit1;		/* Extend SREQ/SACK filtering 	*/
    int stest3Bit7;		/* TolerANT enable 		*/
    int dmodeBit7;              /* Burst Length transfer bit 1 	*/
    int dmodeBit6;              /* Burst Length transfer bit 0 	*/
    int dmodeBit5;		/* Source I/O memory enable 	*/
    int dmodeBit4;		/* Destination I/O memory enable*/
    int scntl1Bit7;		/* Slow cable mode              */
    } NCR810_HW_REGS;


/*
 * SCSI controller structure
 *
 * NOTE: the entire structure must be located in cache-coherent memory 
 * safe for DMA transfers. This is because some fields are shared with the 
 * SCSI controller e.g. Msg In/Out buffers, Data In/Out buffers and the Cmd 
 * buffer.
 *
 * NOTE: some fields in this structure control hardware features which are
 * not supported by the current software.
 */

typedef struct                  /* NCR_810_SCSI_CTRL - NCR810 */
                                /* SCSI controller info       */
    {
    SCSI_CTRL scsiCtrl;         /* generic SCSI controller info */
    SEM_ID    singleStepSem;	/* use to debug script in single step mode */
    
				/* Hardware implementation dependencies */
    BOOL  slowCableMode;	/* TRUE to select slow cable mode */
    int   chipType;		/* Device type NCR7X0_TYPE */
				/* Only 810 Supported today */
    int   devType;		/* type of device (see define's below) */
    BOOL  resetReportDsbl;	/* TRUE to disable SCSI bus reset reporting */
    BOOL  parityTestMode;	/* TRUE enable parity test mode */
    BOOL  parityCheckEnbl;	/* TRUE to enable parity checking */
    UINT  clkPeriod;	    	/* period of controller clock (nsec x 100) */
    UINT8 clkDiv;		/* async and sync clock divider in  scntl3 */
    NCR810_HW_REGS hwRegs;	/* values used for hardware dependent regs */

    NCR810_STATE  state;	/* current state of controller */
    	    	    	    	/* shared data areas for */
    	    	    	    	/* identification & client threads */
    struct ncr810Shared *pIdentShMem;
    struct ncr810Shared *pClientShMem;

    NCR810_THREAD *pHwThread;   /* thread corresp. to current script run */
    NCR810_THREAD *pNewThread;  /* thread to be activated by ISR (if any) */
    BOOL          cmdPending;   /* TRUE => task wants to start new command */
    BOOL          singleStep;   /* TRUE => SIOP is in single-step mode */

    UINT8         identMsg[SCSI_MAX_IDENT_MSG_LENGTH + 5]; /* 5 for wide/sync */
    UINT          identMsgLength;

    volatile UINT8    *pScntl0;      /* SCTNL0 SCSI control register 0 */
    volatile UINT8    *pScntl1;      /* SCTNL1 SCSI control register 1 */
    volatile UINT8    *pScntl2;      /* SCTNL2 SCSI control register 2 */
    volatile UINT8    *pScntl3;      /* SCTNL3 SCSI control register 3 */
    volatile UINT8    *pScid;        /* SCID SCSI chip ID register */
    volatile UINT8    *pSxfer;       /* SODL SCSI transfer register */
    volatile UINT8    *pSdid;        /* SDID SCSI destination ID register */
    volatile UINT8    *pGpreg;       /* GPREG General Purpose register */
    volatile UINT8    *pSfbr;        /* SFBR SCSI first byte received reg */
    volatile UINT8    *pSocl;        /* SOCL SCSI output control latch reg */
    volatile UINT8    *pSsid;        /* SSID SCSI selector ID */
    volatile UINT8    *pSbcl;        /* SBCL SCSI bus control lines reg */
    volatile UINT8    *pDstat;       /* DSTAT DMA status register */
    volatile UINT8    *pSstat0;      /* SSTAT0 SCSI status register 0 */
    volatile UINT8    *pSstat1;      /* SSTAT1 SCSI status register 1 */
    volatile UINT8    *pSstat2;      /* SSTAT2 SCSI status register 2 */
    volatile UINT     *pDsa;         /* DSA data structure address */
    volatile UINT8    *pIstat;       /* ISTAT interrupt status register */
    volatile UINT8    *pCtest0;      /* CTEST0 chip test register 0 */
    volatile UINT8    *pCtest1;      /* CTEST1 chip test register 1 */
    volatile UINT8    *pCtest2;      /* CTEST2 chip test register 2 */
    volatile UINT8    *pCtest3;      /* CTEST3 chip test register 3 */
    volatile UINT     *pTemp;        /* TEMP temporary holding register */
    volatile UINT8    *pDfifo;       /* DFIFO DMA FIFO control register */
    volatile UINT8    *pCtest4;      /* CTEST4 chip test register 4 */
    volatile UINT8    *pCtest5;      /* CTEST5 chip test register 5 */
    volatile UINT8    *pCtest6;      /* CTEST6 chip test register 6 */
    volatile UINT     *pDbc;	     /* DCMD SIOP command reg (24Bits Reg) */
    volatile UINT8    *pDcmd;	     /* DBC SIOP command register 8bits  */
    volatile UINT     *pDnad;        /* DNAD DMA buffer ptr (next address) */
    volatile UINT     *pDsp;         /* DSP SIOP scripts pointer register */
    volatile UINT     *pDsps;        /* DSPS SIOP scripts ptr save reg */
    volatile UINT8    *pScratcha0;   /* SCRATCHA0 general purpose scratch reg */
    volatile UINT8    *pScratcha1;   /* SCRATCHA1 general purpose scratch reg */
    volatile UINT8    *pScratcha2;   /* SCRATCHA2 general purpose scratch reg */
    volatile UINT8    *pScratcha3;   /* SCRATCHA3 general purpose scratch reg */
    volatile UINT8    *pDmode;       /* DMODE DMA operation mode register */
    volatile UINT8    *pDien;        /* DIEN DMA interrupt enable */
    volatile UINT8    *pDwt;         /* DWT DMA watchdog timer register */
    volatile UINT8    *pDcntl;       /* DCTNL DMA control register */
    volatile UINT     *pAdder;	     /* ADDER Adder output Register */
    volatile UINT8    *pSien0;       /* SIEN0 SCSI interrupt enable Zero reg */
    volatile UINT8    *pSien1;       /* SIEN1 SCSI interrupt enable One reg */
    volatile UINT8    *pSist0;       /* SIST0 SCSI interrupt status Zero reg */
    volatile UINT8    *pSist1;       /* SIST1 SCSI interrupt status One reg */
    volatile UINT8    *pSlpar;       /* SLPAR SCSI longitudinal Parity reg */
    volatile UINT8    *pSwide;       /* NCR825 specific: SCSI Wide Residue */
    volatile UINT8    *pMacntl;      /* MACNTL Memory Access Control reg */
    volatile UINT8    *pGpcntl;      /* GPCNTL General Purpose Pin Control */
    volatile UINT8    *pStime0;      /* STIME0 SCSI Timer Zero reg */
    volatile UINT8    *pStime1;      /* STIME1 SCSI Timer One reg */
    volatile UINT8    *pRespid;      /* RESPID Response ID reg */
    volatile UINT8    *pStest0;      /* STEST0 SCSI Test Zero reg */
    volatile UINT8    *pStest1;      /* STEST1 SCSI Test One reg */
    volatile UINT8    *pStest2;      /* STEST2 SCSI Test Two reg */
    volatile UINT8    *pStest3;      /* STEST3 SCSI Test Three reg */

    volatile UINT8    *pStest4;      /* STEST4 SCSI Test Four reg */

    volatile UINT16   *pSidl;        /* SIDL SCSI input data latch reg */
    volatile UINT16   *pSodl;        /* SCSI output data latch reg */
    volatile UINT16   *pSbdl;        /* SBDL SCSI bus data lines register */
    volatile UINT     *pScratchb;    /* SCRATCHB Scratch Register B */

    volatile UINT8    *siopRamBaseAdrs; /* ram base address of SIOP */

    } NCR_810_SCSI_CTRL;

/* END PRIVATE */

/* Data stream swapping macros THESE ARE NOW OBSOLETE */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#   define BYTE_SWAP_32_BIT(x)     LONGSWAP(x)
#   define BYTE_SWAP_16_BIT(x)     ((LSB(x) << 8) | MSB(x))
#else
#   define BYTE_SWAP_32_BIT(x)    (x)
#   define BYTE_SWAP_16_BIT(x)    (x)
#endif 

/* Bit Registers definitions for ncr810 */

/* SCNTL0 */

#define    SCNTL0_ARB1    0x80	/*     Arbitration bit1 and bit0, where  */
#define    SCNTL0_ARB0    0x40	/*     00 - simple arb; 11 - full arb.   */
#define    SCNTL0_START   0x20	/* Start sequence */
#define    SCNTL0_WATN    0x10	/* Select w/wo atn */
#define    SCNTL0_EPC     0x08       /* Parity checking */
#define    SCNTL0_AAP     0x02	/* Assert ATN on parity error */
#define    SCNTL0_TRG     0x01	/* Target/initiator mode */

/* SCNTL1 */

#define    SCNTL1_EXC     0x80	/* Extra Data Set up */
#define    SCNTL1_ADB     0x40	/* Assert Data (SODL) onto scsi */
#define    SCNTL1_DHP     0x20	/* Disable Halt on Parity Error or ATN (targ) */
#define    SCNTL1_CON     0x10	/* connected bit status */
#define    SCNTL1_RST     0x08	/* Assert Rst on scsi */
#define    SCNTL1_AESP    0x04	/* Assert even parity -force error */
#define    SCNTL1_IARB    0x02	/* Immediate arbitration */
#define    SCNTL1_SST     0x01	/* Start SCSI Transfer */

/* SCNTL2 */

#define    SCNTL2_SDU     0x80  /* SCSI Disconnect Unexpected */
#define    SCNTL2_WSR     0x01  /* Wide SCSI Receive */
 
/* SCNTL3 */

#define    SCNTL3_ULTRA   0x80  /* Ultra Enable */
#define    SCNTL3_SCF2    0x40  /* Syncronous Clock Conversion Factor bits */
#define    SCNTL3_SCF1    0x20
#define    SCNTL3_SCF0    0x10
#define    SCNTL3_EWS  	  0x08	/* Enable WIDE SCSI */
#define    SCNTL3_CCF2    0x04	/* Clock Conversion Factor bits */
#define    SCNTL3_CCF1    0x02	
#define    SCNTL3_CCF0    0x01	
#define    SCNTL3_SCF_MASK 0x70 /* Sync Clock Conv Factor bit mask */
#define    SCNTL3_CCF_MASK 0x07 /* Clock Conv Factor bit mask */

/* SCID */

#define    SCID_RRE     0x40	/* Enable Response to Reselection */
#define    SCID_SRE     0x20       /* Enable Response to Selection   */
#define    SCID_ENC2    0x04       /* Encoded SCSI ID bit 2 */
#define    SCID_ENC1    0x02       /* Encoded SCSI ID bit 1 */
#define    SCID_ENC0    0x01       /* Encoded SCSI ID bit 0 */
#define    SCID_ENC_MASK 0x07	   /* The Encoded SCSI ID mask */