ncr710_2.h

IXP425的BSP代码

#define    B_WOA     0x04	/* stat :won arbitration-full arbit mode */
#define    B_RSTNL   0x02	/* stat :current stat of RST line-Not Latched */
#define    B_PARNL   0x01	/* stat :curr stat Parity lines-Not Latched */

/* SSTAT2 RO register */
#define    B_FF3     0x80	/* Fifo flag 3 :number of bytes in fifo */
#define    B_FF2     0x40	/* Fifo flag 2 :number of bytes in fifo */
#define    B_FF1     0x20	/* Fifo flag 1 :number of bytes in fifo */
#define    B_FF0     0x10	/* Fifo flag 0 :number of bytes in fifo */
				/* 0000=0 ..... 1000=8 */
#define    B_SPDL    0x08	/* Latched parity line */
#define    B_MSGL    0x04	/* Latched state of MSG line */
#define    B_CDL     0x02	/* Latched state of C/D line */
#define    B_IOL     0x01	/* Latched sate of IO line */

/* DFIFO RW register */
#define    B_BO6     0x40	/* Byte offset counter 6 */
#define    B_BO5     0x20	/* Byte offset counter 5 */
#define    B_BO4     0x10	/* Byte offset counter 4 */
#define    B_BO3     0x08	/* Byte offset counter 3 */
#define    B_BO2     0x04	/* Byte offset counter 2 */
#define    B_BO1     0x02	/* Byte offset counter 1 */
#define    B_BO0     0x01	/* Byte offset counter 0 */

/* ISTAT RW register */
#define    B_ABORT   0x80	/* Abort operation */
#define    B_SOFTRST 0x40	/* Soft chip reset */
#define    B_SIGP    0x20	/* signal process */
#define    B_CONST   0x08	/* stat connected (reset doesn't disconnect) */
#define    B_SIP     0x02	/* Status scsi interrupt pending */
#define    B_DIP     0x01	/* Status Dma portion interrupt pending */

/* DMODE RW register */
#define    B_BL1     0x80	/* Burst Length transfer bit 1 */
#define    B_BL0     0x40	/* Burst Length transfer bit 0 */
				/* 00=1,01=2,10=4,11=8 */
#define    B_FC2     0x20	/* Function code bit 1 user defined */
#define    B_FC1     0x10	/* Function code bit 0 user defined */
#define    B_PD      0x08	/* Program data access */
#define    B_FAM     0x04	/* Fixed Address mode */
#define    B_U0TT0   0x02	/* user  programmable transfer type */
#define    B_MAN     0x01	/* Manual start mode ,when set disable */
				/* autostart script when writting in DSP */
/* DCTNL */
#define    B_CF1     0x80	/* Prescale bit 1 for scsi core */
#define    B_CF0     0x40	/* Prescale bit 0 for scsi core */
				/* involve all timing on scsi */
#define    B_EA      0x20	/* Enable ack (host/chip) */
#define    B_SSM     0x10	/* Enable single step mode */
#define    B_LLM     0x08	/* Enable Low level mode */
#define    B_STD     0x04	/* Start Dma operation used with B_MAN in */
				/* DMODE Register and single step mode */
#define    B_FA      0x02	/* Enable fast arbitration on host port */
#define    B_COM     0x01	/* When 0, enable compatible mode with ncr700 */

/* CTEST0 */
#define	   B_EAN     0x10   	/* Enable active negation */

/* CTEST4 */
#define    B_MUX     0x80	/* Host mux bus mode */
#define    B_ZMOD    0x40	/* Host bus high impedance mode  */
#define    B_SZM     0x20	/* Scsi bus high impedance mode */
#define    B_SLBE    0x10	/* Enable loopback mode */
#define    B_SFWR    0x08	/* Scsi fifo write enable */
#define    B_FBL2    0x04	/* Enable bytes lane */
#define    B_FLB1    0x02	/* Bit one mux byte lane */
#define    B_FLB0    0x01	/* Bit zero mux byte lane */

/* CTEST5 */
#define    B_ADCK    0x80	/* Increment DNAD register */
#define    B_BBCK    0x40	/* Decrement DBC register */
#define    B_ROFF    0x20	/* Clear offset in scsi sync mode */
#define    B_MASR    0x10	/* set/reset values for bit 3:0 */
#define    B_DDIR    0x08	/* control internel DMAWR (scsi to host) */
#define    B_EOP     0x04	/* control internal EOP (DMA/SCSI) */
#define    B_DREQ    0x02	/* control internal DREQ */
#define    B_DACK    0x01	/* control internal DACK (DMA/SCSI) */

/* CTEST7 */
#define    B_CDIS    0x80	/* Disable Burst Cache */
#define    B_SC1     0x40	/* Snoop control bit1 */
#define    B_SC0     0x20	/* Snoop control bit0 */
#define    B_TOUT    0x10	/* disable scsi timout */
#define    B_DFP     0x08	/* Fifo parity bit */
#define    B_EVP     0x04	/* enable even parity on host/fifo */
#define    B_TT1     0x02	/* invert tt1 pin (sync host mode only) */
#define    B_DIFF    0x01       /* Valid differential scsi bus */

/* CTEST8 */
#define    B_V3      0x80	/* Chip Revision Bit 3 */
#define    B_V2      0x40	/* Chip Revision Bit 2 */
#define    B_V1      0x20	/* Chip Revision Bit 1 */
#define    B_V0      0x10	/* Chip Revision Bit 0 */
#define    B_FLF     0x08	/* Flush DMA FIFO */
#define    B_CLF     0x04	/* Clear DMA FIFO */
#define    B_FM      0x02	/* Fetch Pin mode */
#define    B_SM      0x01       /* Snoop pins mode */

/* offset registers */

#if _BYTE_ORDER==_BIG_ENDIAN

#define OFF_SIEN         (0X00)   /* scsi interrupt enable reg */
#define OFF_SDID         (0X01)   /* scsi destination ID reg */
#define OFF_SCNTL1       (0X02)   /* scsi control reg 1 */
#define OFF_SCNTL0       (0X03)   /* scsi control reg 0 */
#define OFF_SOCL         (0X04)   /* scsi output control latch reg */
#define OFF_SODL         (0X05)   /* scsi output data latch reg */
#define OFF_SXFER        (0X06)   /* scsi transfer reg */
#define OFF_SCID         (0X07)   /* scsi chip ID reg */
#define OFF_SBCL         (0X08)   /* scsi bus control lines reg */
#define OFF_SBDL         (0X09)   /* scsi bus data lines reg */
#define OFF_SIDL         (0X0A)   /* scsi input data latch reg */
#define OFF_SFBR         (0X0B)   /* scsi first byte received reg */
#define OFF_SSTAT2       (0X0C)   /* scsi status reg 2 */
#define OFF_SSTAT1       (0X0D)   /* scsi status reg 1 */
#define OFF_SSTAT0       (0X0E)   /* scsi status reg 0 */
#define OFF_DSTAT        (0X0F)   /* dma  status reg */
#define OFF_DSA          (0X10)   /* data structure address */
#define OFF_CTEST3       (0X14)   /* chip test reg 3 */
#define OFF_CTEST2       (0X15)   /* chip test reg 2 */
#define OFF_CTEST1       (0X16)   /* chip test reg 1 */
#define OFF_CTEST0       (0X17)   /* chip test reg 0 */
#define OFF_CTEST7       (0X18)   /* chip test reg 7 */
#define OFF_CTEST6       (0X19)   /* chip test reg 6 */
#define OFF_CTEST5       (0X1A)   /* chip test reg 5 */
#define OFF_CTEST4       (0X1B)   /* chip test reg 4 */
#define OFF_TEMP         (0X1C)   /* Temporary stack reg */
#define OFF_LCRC         (0X20)   /* CRC register */
#define OFF_CTEST8       (0X21)   /* Chip test reg 8 */
#define OFF_ISTAT        (0X22)   /* Interrupt status reg */
#define OFF_DFIFO        (0X23)   /* DMA FIFO reg */
#define OFF_DCMD         (0X24)   /* 8 bit reg DMA command reg */
#define OFF_DBC          (0X24)   /* 24 bit Reg DMA byte counter register */
#define OFF_DNAD         (0X28)   /* DMA next address for data reg */
#define OFF_DSP          (0X2C)   /* DMA scripts pointer reg */
#define OFF_DSPS         (0X30)   /* DMA scripts pointer save reg */
#define OFF_SCRATCH3     (0X34)   /* scratch register */
#define OFF_SCRATCH2     (0X35)   /* scratch register */
#define OFF_SCRATCH1     (0X36)   /* scratch register */
#define OFF_SCRATCH0     (0X37)   /* scratch register */
#define OFF_DCNTL        (0X38)   /* DMA control reg */
#define OFF_DWT          (0X39)   /* DMA watchdog timer */
#define OFF_DIEN         (0X3A)   /* DMA interrupt enable reg */
#define OFF_DMODE        (0X3B)   /* DMA mode reg */
#define OFF_ADDER        (0X3C)   /* internal adder register;don't use */

#else  /* _BYTE_ORDER==_BIG_ENDIAN */

#define OFF_SIEN         (0X03)   /* scsi interrupt enable reg */
#define OFF_SDID         (0X02)   /* scsi destination ID reg */
#define OFF_SCNTL1       (0X01)   /* scsi control reg 1 */
#define OFF_SCNTL0       (0X00)   /* scsi control reg 0 */
#define OFF_SOCL         (0X07)   /* scsi output control latch reg */
#define OFF_SODL         (0X06)   /* scsi output data latch reg */
#define OFF_SXFER        (0X05)   /* scsi transfer reg */
#define OFF_SCID         (0X04)   /* scsi chip ID reg */
#define OFF_SBCL         (0X0B)   /* scsi bus control lines reg */
#define OFF_SBDL         (0X0A)   /* scsi bus data lines reg */
#define OFF_SIDL         (0X09)   /* scsi input data latch reg */
#define OFF_SFBR         (0X08)   /* scsi first byte received reg */
#define OFF_SSTAT2       (0X0F)   /* scsi status reg 2 */
#define OFF_SSTAT1       (0X0E)   /* scsi status reg 1 */
#define OFF_SSTAT0       (0X0D)   /* scsi status reg 0 */
#define OFF_DSTAT        (0X0C)   /* dma  status reg */
#define OFF_DSA          (0X10)   /* data structure address */
#define OFF_CTEST3       (0X17)   /* chip test reg 3 */
#define OFF_CTEST2       (0X16)   /* chip test reg 2 */
#define OFF_CTEST1       (0X15)   /* chip test reg 1 */
#define OFF_CTEST0       (0X14)   /* chip test reg 0 */
#define OFF_CTEST7       (0X1B)   /* chip test reg 7 */
#define OFF_CTEST6       (0X1A)   /* chip test reg 6 */
#define OFF_CTEST5       (0X19)   /* chip test reg 5 */
#define OFF_CTEST4       (0X18)   /* chip test reg 4 */
#define OFF_TEMP         (0X1C)   /* Temporary stack reg */
#define OFF_LCRC         (0X23)   /* CRC register */
#define OFF_CTEST8       (0X22)   /* Chip test reg 8 */
#define OFF_ISTAT        (0X21)   /* Interrupt status reg */
#define OFF_DFIFO        (0X20)   /* DMA FIFO reg */
#define OFF_DCMD         (0X27)   /* 8 bit reg DMA command reg */
#define OFF_DBC          (0X24)   /* 24 bit Reg DMA byte counter register */
#define OFF_DNAD         (0X28)   /* DMA next address for data reg */
#define OFF_DSP          (0X2C)   /* DMA scripts pointer reg */
#define OFF_DSPS         (0X30)   /* DMA scripts pointer save reg */
#define OFF_SCRATCH3     (0X37)   /* scratch register */
#define OFF_SCRATCH2     (0X36)   /* scratch register */
#define OFF_SCRATCH1     (0X35)   /* scratch register */
#define OFF_SCRATCH0     (0X36)   /* scratch register */
#define OFF_DCNTL        (0X3B)   /* DMA control reg */
#define OFF_DWT          (0X3A)   /* DMA watchdog timer */
#define OFF_DIEN         (0X39)   /* DMA interrupt enable reg */
#define OFF_DMODE        (0X38)   /* DMA mode reg */
#define OFF_ADDER        (0X3C)   /* internal adder register;don't use */

#endif  /* _BYTE_ORDER==_BIG_ENDIAN */

/* Mask Values */
#define NCR710_COUNT_MASK    ((UINT)0x00ffffff) /* Mask 24 bit value in block */
                                                /* move description */
/* Shift values for "device" field in shared data structure */
#define NCR710_TARGET_BUS_ID_SHIFT  16	/* bits 23-16: specify target bus ID */
#define	NCR710_XFER_PARAMS_SHIFT     8	/* bits 15-08: copy of sxfer reg.    */

/* Sync offset and period (SXFER register) */
#define NCR710_MAX_REQ_ACK_OFFSET   7	/* Maximum sync offset        */
#define NCR710_MIN_XFER_PERIOD      0	/* Minimum sync period (clks) */
#define NCR710_MAX_XFER_PERIOD      7	/* Maximum sync period (clks) */

#define	NCR710_SYNC_XFER_PERIOD_SHIFT 	4

#define	NCR710_SYNC_XFER_PARAMS_ASYNC	0x00

/* Synchronous transfer clock division factor (SBCL register bits 1,0 (w-o) */
#define	NCR710_MIN_CLOCK_DIV	    	0x00
#define	NCR710_MAX_CLOCK_DIV	    	0x03
#define	NCR710_CLOCK_DIVIDE_ASYNC   	0x00

/* Clock conversion factor */
/* prescale factor for scsi core (dctnl) */
#define NCR710_16MHZ_DIV        0x80    /* 16-25Mhz chip */
#define NCR710_25MHZ_DIV        0x40    /* 25-37.5Mhz chip */
#define NCR710_50MHZ_DIV        0x00    /* 37.5-50Mhz chip */
#define NCR710_66MHZ_DIV        0xC0    /* 50-66Mhz chip */

/* ns x 100 clock period */
#define NCR710_1667MHZ  6000    /* 16.67Mhz chip */
#define NCR710_20MHZ    5000    /* 20Mhz chip */
#define NCR710_25MHZ    4000    /* 25Mhz chip */
#define NCR710_3750MHZ  2667    /* 37.50Mhz chip */
#define NCR710_40MHZ    2500    /* 40Mhz chip */
#define NCR710_50MHZ    2000    /* 50Mhz chip */
#define NCR710_66MHZ    1515    /* 66Mhz chip */
#define NCR710_6666MHZ  1500    /* 66Mhz chip */

/* Chip Type */
#define NCR700_TYPE	0x700   /* not supported */
#define NCR710_TYPE	0x710   /* supported */
#define NCR720_TYPE	0x720   /* not supported */

/* Default value to initialize some registers involved
 * in the hardware implementation.Those values could be
 * overwritten by a bsp call with the ncr710HwSetRegister().
 * The ncr710 Data Manual documentation will you give all
 * the light regarding values choose. See also the
 * documentation of ncr710SetHwRegister call.
 * See above the NCR710_HW_REGS for the meaning of the
 * values prefill.
 */
#define DEFAULT_710_HW_REGS { 0,0,0,0,1,0,0,0,0,0,0,0,0,1,0 }


/* function declarations */

#if defined(__STDC__) || defined(__cplusplus)

IMPORT  NCR_710_SCSI_CTRL * ncr710CtrlCreateScsi2 (UINT8 *siopBaseAdrs,
                                              UINT clkPeriod);
IMPORT  STATUS  ncr710CtrlInitScsi2 (NCR_710_SCSI_CTRL *pSiop, 
					int scsiCtrlBusId, int scsiPriority);
IMPORT	STATUS	ncr710SetHwRegisterScsi2 (NCR_710_SCSI_CTRL *pScsiCtrl,
				    NCR710_HW_REGS *pHwRegs);
IMPORT  void    ncr710IntrScsi2  (NCR_710_SCSI_CTRL *pSiop);
IMPORT  STATUS 	ncr710ShowScsi2  (SCSI_CTRL *pScsiCtrl);
IMPORT  void    ncr710StepEnable (NCR_710_SCSI_CTRL *pSiop, BOOL enable);
IMPORT  void    ncr710SingleStep (NCR_710_SCSI_CTRL *pSiop, BOOL verbose);

#else	/* __STDC__ */

IMPORT  NCR_710_SCSI_CTRL * ncr710CtrlCreateScsi2 ();
IMPORT  STATUS  ncr710CtrlInitScsi2 ();
IMPORT  STATUS 	ncr710SetHwRegisterScsi2 ();
IMPORT  void    ncr710IntrScsi2 ();
IMPORT  STATUS 	ncr710ShowScsi2 ();
IMPORT  void    ncr710StepEnable ();
IMPORT  void    ncr710SingleStep ();

#endif  /* __STDC__ */

#endif	/* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif

#endif /* __INCncr710_2h */