📄 ncr710_1.h
字号:
/* ncr710_1.h - NCR 710 Script SCSI Controller header file *//* Copyright 1984-1994 Wind River Systems, Inc. *//*modification history--------------------02m,08nov94,jds renamed for SCSI1 compatability02l,26sep92,ccc ncr710Show() returns STATUS.02k,22sep92,rrr added support for c++02j,26jul92,rrr removed decl ncr710SyncMsgConvert, was made LOCAL in mod 02i02i,21jul92,eve clean an move debug macros to ncr710Lib.c.01h,03jul92,eve merge header with new driver.01h,03jul92,eve merge header with new driver.01g,29jun92,ccc fixed compile errors.01f,26jun92,ccc changed ASMLANGUAGE to _ASMLANGUAGE.40c,26may92,rrr the tree shuffle40b,28apr92,wmd Added defines for LITTLE_ENDIAN architectures, and fixed typo for declaration of ncr710CtrlCreate(), ansified.40a,12nov91,ccc SPECIAL VERSION FOR 5.0.2 68040 RELEASE.02a,26oct91,eve Add description of hardware dependant registers.01a,23oct91,eve Created driver header*/#ifndef __INCncr710_1h#define __INCncr710_1h#ifdef __cplusplusextern "C" {#endif#ifndef _ASMLANGUAGE#include "semLib.h"#include "scsiLib.h"#include "ncr710Script.h"/* Structure used in the ncr710SetHwRegister() and ncr710GetHwRegister(). * This is used to try to handle the possible differents hardware * implementation of the chip.This structure must contain the logical value * wishes e.g 0 sets register bit to null and 1 sets to one. */typedef struct { int ctest4Bit7; /* Host bus multiplex mode */ int ctest7Bit7; /* Disable/enable burst cache capability */ int ctest7Bit6; /* Snoop control bit1 */ int ctest7Bit5; /* Snoop control bit0 */ int ctest7Bit1; /* invert tt1 pin (sync bus host mode only) */ int ctest7Bit0; /* enable differential scsi bus capability */ int ctest8Bit0; /* Set snoop pins mode */ int dmodeBit7; /* Burst Length transfer bit 1 */ int dmodeBit6; /* Burst Length transfer bit 0 */ int dmodeBit5; /* Function code bit FC2 */ int dmodeBit4; /* Function code bit FC1 */ int dmodeBit3; /* Program data bit ( FC0) */ int dmodeBit1; /* user programmable transfer type */ int dcntlBit5; /* Enable Ack pin */ int dcntlBit1; /* Enable fast arbitration on host port */ } NCR710_HW_REGS; /* Allocate one context per device ( 8 ID max and 8 LUN max per ID) */typedef struct { NCR_CTL ncrCtl[SCSI_MAX_BUS_ID + 1][SCSI_MAX_LUN + 1]; } NCR_CTL_CTXT;/* SCSI controller structure */typedef struct /* NCR_710_SCSI_CTRL - NCR710 */ /* SCSI controller info */ { SCSI_CTRL scsiCtrl; /* generic SCSI controller info */ SEM_ID pMutexData; /* use to protect global siop data */ SCSI_PHYS_DEV *pDevToSelect;/* device to select at intr. level or NULL */ /* Hardware implementation dependencies */ TBOOL slowCableMode; /* TRUE to select slow cable mode */ int chipType; /* Device type NCR7X0_TYPE */ /* Only 710 Supported today */ int devType; /* type of device (see define's below) */ UINT8 ctrlIdPow2; /* controller id in power of 2 (1000000=id 7) */ TBOOL resetReportDsbl; /* TRUE to disable SCSI bus reset reporting */ TBOOL parityTestMode; /* TRUE enable parity test mode (DO NOT USE) */ TBOOL parityCheckEnbl; /* TRUE to enable parity checking */ UINT8 defaultSelTimeOut; /* default dev. select time-out (units var.) */ UINT8 clkCvtFactor; /* value of the clock conversion factor */ UINT8 saveIstat; /* Save Reg under interrupt */ UINT8 saveSstat0; /* Save Reg under interrupt */ UINT8 saveDstat; /* Save Reg under interrupt */ UINT8 saveIdentMsg; /* Save Indent message in at interrupt level */ /* when reconnect. */ TBOOL commandRequest; /* To check if we are reconnected with a */ /* request pending */ UINT saveScriptIntrStat; /* Save intr script status under interrupt */ SEMAPHORE singleStepSem; /* use to debug script in single step mode */ NCR_CTL_CTXT *pNcrCtxt; /* pointer to Array of data shared by script */ /* and driver */ NCR_CTL *pNcrCtl; /* Current context pointer for intr level */ NCR_CTL *pNcrCtlCmd; /* current ctxt pointer to the command */ /* pending */ NCR710_HW_REGS hwRegs; /* values used for hardware dependant regs */ volatile UINT8 *pSien; /* SIEN SCSI interrupt enable reg */ volatile UINT8 *pSdid; /* SDID SCSI destination ID register */ volatile UINT8 *pScntl1; /* SCTNL1 SCSI control register 1 */ volatile UINT8 *pScntl0; /* SCTNL0 SCSI control register 0 */ volatile UINT8 *pSocl; /* SOCL SCSI output control latch reg */ volatile UINT8 *pSodl; /* SCSI output data latch reg */ volatile UINT8 *pSxfer; /* SODL SCSI transfer register */ volatile UINT8 *pScid; /* SCID SCSI chip ID register */ volatile UINT8 *pSbcl; /* SBCL SCSI bus control lines reg */ volatile UINT8 *pSbdl; /* SBDL SCSI bus data lines register */ volatile UINT8 *pSidl; /* SIDL SCSI input data latch reg */ volatile UINT8 *pSfbr; /* SFBR SCSI first byte received reg */ volatile UINT8 *pSstat2; /* SSTAT2 SCSI status register 2 */ volatile UINT8 *pSstat1; /* SSTAT1 SCSI status register 1 */ volatile UINT8 *pSstat0; /* SSTAT0 SCSI status register 0 */ volatile UINT8 *pDstat; /* DSTAT DMA status register */ volatile UINT *pDsa; /* DSA data structure address */ volatile UINT8 *pCtest3; /* CTEST3 chip test register 3 */ volatile UINT8 *pCtest2; /* CTEST2 chip test register 2 */ volatile UINT8 *pCtest1; /* CTEST1 chip test register 1 */ volatile UINT8 *pCtest0; /* CTEST0 chip test register 0 */ volatile UINT8 *pCtest7; /* CTEST7 chip test register 7 */ volatile UINT8 *pCtest6; /* CTEST6 chip test register 6 */ volatile UINT8 *pCtest5; /* CTEST5 chip test register 5 */ volatile UINT8 *pCtest4; /* CTEST4 chip test register 4 */ volatile UINT *pTemp; /* TEMP temporary holding register */ volatile UINT8 *pLcrc; /* LCRC longitudinal parity register */ volatile UINT8 *pCtest8; /* CTEST8 chip test register */ volatile UINT8 *pIstat; /* ISTAT interrupt status register */ volatile UINT8 *pDfifo; /* DFIFO DMA FIFO control register */ volatile UINT8 *pDcmd; /* DBC SIOP command register 8bits */ volatile UINT *pDbc; /* DCMD SIOP command reg (24Bits Reg) */ volatile UINT *pDnad; /* DNAD DMA buffer ptr (next address) */ volatile UINT *pDsp; /* DSP SIOP scripts pointer register */ volatile UINT *pDsps; /* DSPS SIOP scripts ptr save reg */ volatile UINT8 *pScratch3; /* SCRATCH3 general purpose scratch reg */ volatile UINT8 *pScratch2; /* SCRATCH2 general purpose scratch reg */ volatile UINT8 *pScratch1; /* SCRATCH1 general purpose scratch reg */ volatile UINT8 *pScratch0; /* SCRATCH0 general purpose scratch reg */ volatile UINT8 *pDcntl; /* DCTNL DMA control register */ volatile UINT8 *pDwt; /* DWT DMA watchdog timer register */ volatile UINT8 *pDien; /* DIEN DMA interrupt enable */ volatile UINT8 *pDmode; /* DMODE DMA operation mode register */ volatile UINT *pAdder; /* ADDER Adder output Register */ } NCR_710_SCSI_CTRL;/* Bit Registers definitions for ncr710 *//* SCNTL0 */#define B_ARB1 0x80 /* Arbitration bit 1 */#define B_ARB0 0x40 /* Arbitration bit 0 */ /* 00 Simple/11 full */#define B_START 0x20 /* Start sequence */#define B_WATN 0x10 /* Select w/wo atn */#define B_EPC 0x08 /* Parity checking */#define B_EPG 0x04 /* Enable parity generation */#define B_AAP 0x02 /* Assert ATN on parity error */#define B_TRG 0x01 /* Target/initiator mode *//* SCNTL1 */#define B_EXC 0x80 /* Extra Data Set up */#define B_ADB 0x40 /* Assert Data (SODL) onto scsi */#define B_ESR 0x20 /* Enable Select & reselect */#define B_CON 0x10 /* connected bit status */#define B_RST 0x08 /* Assert Rst on scsi */#define B_AESP 0x04 /* Assert even parity -force error */#define B_SND 0x02 /* Start send scsi operation */#define B_RCV 0x01 /* Start receive scsi operation *//* SIEN (enable int)and SSTAT0 (RO Status) *//* Enable interrupt */#define B_MA 0x80 /* Enable phase mismatch/Atn Active */#define B_FCMP 0x40 /* Enable funtion complete */#define B_STO 0x20 /* Enable scsi timout */#define B_SEL 0x10 /* Enable sel/resel */#define B_SGE 0x08 /* Enable scsi gross error */#define B_UDC 0x04 /* Enable unexpected disconnect */#define B_RSTE 0x02 /* Enable Rst received */#define B_PAR 0x01 /* Enable parity int *//* SXFER */#define B_DHP 0x80 /* Disable Halt on parity err */#define B_TP2 0x40 /* Synchronous transfer period 2 */#define B_TP1 0x20 /* Synchronous transfer period 1 */#define B_TP0 0x10 /* Synchronous transfer period 0 */#define B_MO3 0x08 /* Maximun scsi Synchronous transfer offset */#define B_MO2 0x04 /* Maximun scsi Synchronous transfer offset */#define B_MO1 0x02 /* Maximun scsi Synchronous transfer offset */#define B_MO0 0x01 /* Maximun scsi Synchronous transfer offset *//* SOCL (RW) and SBCL (RO not latched) */#define B_REQ 0x80 /* Assert scsi req */#define B_ACK 0x40 /* Assert scsi ack */#define B_BSY 0x20 /* Assert scsi busy */#define B_SEL 0x10 /* Assert scsi sel */#define B_ATN 0x08 /* Assert scsi atn */#define B_MSG 0x04 /* Assert scsi msg */#define B_CD 0x02 /* Assert scsi c/d */#define B_IO 0x01 /* Assert scsi i/o *//* SSCF (Write only same @ as SBCL) */#define B_SSCF1 0x02 /* prescale clock for scsi core bit 1 */#define B_SSCF0 0x01 /* prescale clock for scsi core bit 0 *//* DSTAT (RO) and DIEN (RW enable intr) */#define B_DFE 0x80 /* stat :Dma fifo empty */#define B_BF 0x20 /* stat :Bus access error */#define B_ABT 0x10 /* stat :Abort condition */#define B_SSI 0x08 /* stat :Scsi step interrupt */#define B_SIR 0x04 /* stat :Script interrupt received */#define B_WTD 0x02 /* stat :Watchdog timout */#define B_IID 0x01 /* stat :Illegal instruction occur *//* SSTAT1 RO register */#define B_ILF 0x80 /* stat :SDIL register contain scsi data */ /* in async mode only */#define B_ORF 0x40 /* stat :SODR output data in sync mode hidden */#define B_OLF 0x20 /* stat :SODL Register full (hidden) */#define B_AIP 0x10 /* stat :Arbitration in progress */#define B_LOA 0x08 /* stat :Lost arbitration */#define B_WOA 0x04 /* stat :won arbitration-full arbit mode */#define B_RSTNL 0x02 /* stat :current stat of RST line-Not Latched */#define B_PARNL 0x01 /* stat :curr stat Parity lines-Not Latched *//* SSTAT2 RO register */#define B_FF3 0x80 /* Fifo flag 3 :number of bytes in fifo */#define B_FF2 0x40 /* Fifo flag 2 :number of bytes in fifo */#define B_FF1 0x20 /* Fifo flag 1 :number of bytes in fifo */#define B_FF0 0x10 /* Fifo flag 0 :number of bytes in fifo */ /* 0000=0 ..... 1000=8 */#define B_SPDL 0x08 /* Latched parity line */#define B_MSGL 0x04 /* Latched state of MSG line */#define B_CDL 0x02 /* Latched state of C/D line */#define B_IOL 0x01 /* Latched sate of IO line *//* DFIFO RW register */#define B_BO6 0x40 /* Byte offset counter 6 */#define B_BO5 0x20 /* Byte offset counter 5 */#define B_BO4 0x10 /* Byte offset counter 4 */#define B_BO3 0x08 /* Byte offset counter 3 */#define B_BO2 0x04 /* Byte offset counter 2 */#define B_BO1 0x02 /* Byte offset counter 1 */#define B_BO0 0x01 /* Byte offset counter 0 */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -