if_dc.h

IXP425的BSP代码

/* CSR10 Reserved */


/* CSR11 Full Duplex Register */

#define	CSR11_FDACV_MSK	0x0000FFFF	/* full duplex auto config mask */

/* CSR11 General-Purpose Timer Register for the DEC21140 */

#define	CSR11_CON_MODE		0x00010000	/* GPT Continuous Mode */
#define	CSR11_VALUE_MASK	0x0000FFFF	/* GPT Timer Value Mask */

/* CSR12 SIA status Register */

#define	CSR12_DA0	0x00000080	/* Diagnostic bit all One */
#define	CSR12_DAZ	0x00000040	/* Diagnostic bit all zero */
#define	CSR12_DSP      	0x00000020	/* Diagnostic BIST status indicator */
#define	CSR12_DSD	0x00000010	/* Diagnostic Self test done */
#define	CSR12_APS	0x00000008	/* Auto polarity state */
#define	CSR12_LKF	0x00000004	/* link fail status */
#define	CSR12_NCR	0x00000002	/* network connection error */
#define	CSR12_PAUI	0x00000001	/* pin AUI_TP indication */

/* CSR12 General-Purpose Registerr for the DEC21140 */

#define	CSR12_CNTRL_FLAG	0x00000100   /* Control Flag */
#define	CSR12_DATA_MASK		0x000000FF   /* Mode and Data Mask */

#define INIT_CSR12	CSR12_CNTRL_FLAG | 0x0f	/* Base value for CSR12 */
#define SYM_MODE	0x00000009		/* SYM value for CSR12 */

/* CSR13 SIA connectivity Register */

#define CSR13_OE57	0x00008000	/* Output enable 5 6 7 */
#define CSR13_OE24	0x00004000	/* output enable 2 4 */
#define CSR13_OE13	0x00002000	/* output enable 1 3 */
#define CSR13_IE	0x00001000	/* input enable */	
#define CSR13_SEL_LED	0x00000f00	/* select LED and external driver */
#define CSR13_ASE_APLL	0x00000080	/* ase apll start enable */
#define CSR13_SIM	0x00000040	/* serial iface input multiplexer */
#define CSR13_ENI	0x00000020	/* encoder Input multiplexer */
#define CSR13_EDP_SIA	0x00000010	/* pll external input enable */
#define CSR13_AUI_TP	0x00000008	/* AUI - 10BASE-T or AUI */
#define CSR13_CAC_CSR	0x00000004	/* auto config register */
#define	CSR13_PS	0x00000002	/* pin AUI_TP select */	
#define CSR13_SRL_SIA	0x00000001	/* srl sia Reset */

/* CSR14 SIA xmit rcv Register */

#define CSR14_SPP	0x00004000	/* set polarity plus */
#define CSR14_APE	0x00002000	/* auto polarity enable */
#define CSR14_LTE	0x00001000	/* link test enable */
#define CSR14_SQE	0x00000800	/* signal quality generate enable */
#define CSR14_CLD	0x00000400	/* collision detect enable */
#define CSR14_CSQ	0x00000200	/* collision squelch enable */
#define CSR14_RSQ	0x00000100	/* receive squelch enable */
#define CSR14_CPEN_NC	0x00000030	/* no compensation */
#define CSR14_CPEN_HP	0x00000020	/* high power mode */
#define CSR14_CPEN_DM	0x00000010	/* disable mode */
#define CSR14_LSE	0x00000008	/* link pulse send enable */
#define CSR14_DREN	0x00000004	/* driver enable */
#define CSR14_LBK	0x00000002	/* loopback enable */
#define CSR14_ECEN	0x00000001	/* encoder enable */

/* CSR15 SIA general register */

#define CSR15_JCK	0x00000004	/* jabber clock */
#define CSR15_HUJ	0x00000002	/* host unjab */
#define CSR15_JBD	0x00000001	/* jabber disable */

/* CSR15 Watchdog Timer Register for the DEC21140 */

#define	CSR15_RWR_FLAG	0x00000020   /* Receive Watchdog Release */
#define	CSR15_RWD_FLAG	0x00000010   /* Receive Watchdog Disable */

/* receive descriptor */

/* receive descriptor 0 */

#define RDESC0_OWN		0x80000000	/* Own */
#define RDESC0_ES		0x00008000	/* Error summary */
#define RDESC0_LE		0x00004000
#define RDESC0_DT_SRF		0x00000000	/* serial rcvd frame */
#define RDESC0_DT_ILF		0x00001000	/* internal loop back frame */
#define RDESC0_DT_ELF		0x00002000	/* external loop back frame */
#define RDESC0_RF		0x00000800	/* runt frame */
#define RDESC0_MF		0x00000400	/* multicast frame */
#define RDESC0_FD		0x00000200	/* first descriptor */
#define RDESC0_LS		0x00000100	/* last descriptor */
#define RDESC0_TL		0x00000080	/* frame too long */
#define RDESC0_CS		0x00000040	/* collision seen */
#define RDESC0_FT		0x00000020	/* frame type */
#define RDESC0_RJ		0x00000010	/* receive watch dog */
#define RDESC0_DB		0x00000004	/* dribbling bit */
#define RDESC0_CE		0x00000002	/* crc error */
#define RDESC0_OF		0x00000001	/* Over flow */

#define RDESC0_FL_MSK		0x7FFF0000	/* Frame length mask */
#define RDESC0_FL_GET(x)	(((x) & RDESC0_FL_MSK) >> 16)
#define RDESC0_FL_PUT(x)	(((x) << 16) & RDESC0_FL_MSK)

/* receive descriptor 1 */

#define RDESC1_RER		0x02000000	/* recv end of ring */
#define RDESC1_RCH		0x01000000	/* second address chained */

#define RDESC1_RBS2_MSK		0x003FF800	/* RBS2 buffer 2 size */
#define RDESC1_RBS1_MSK		0x000007FF	/* RBS1 buffer 1 size */

#define RDESC1_RBS1_VAL(x)	((x) & RDESC1_RBS1_MSK)	/* multiple of 4 */
#define RDESC1_RBS2_VAL(x)	(((x) << 11) & RDESC1_RBS2_MSK)	

/* transmit descriptor */

/* xmit descriptor 0 */

#define TDESC0_OWN		0x80000000	/* own */
#define TDESC0_ES		0x00008000	/* error summary */
#define TDESC0_TO		0x00004000	/* xmit jabber time out */
#define TDESC0_LO		0x00000800	/* loss of carrier */
#define TDESC0_NC		0x00000400	/* NC No carrier */
#define TDESC0_LC		0x00000200	/* late collision */	
#define TDESC0_EC		0x00000100	/* excessive collision */
#define TDESC0_HF		0x00000080	/* heart beat fail */
#define TDESC0_LF		0x00000004	/* link fail */
#define TDESC0_UF		0x00000002	/* underflow error */
#define TDESC0_DE	        0x00000001	/* deffered */

#define TDESC0_CC_MSK		0x00000078

/* xmit descriptor 1 */

#define TDESC1_IC		0x80000000	/* interrupt on completion */
#define TDESC1_LS		0x40000000	/* last segment */
#define TDESC1_FS		0x20000000	/* first segment */
#define TDESC1_FT1		0x10000000	/* filtering type */
#define TDESC1_SET		0x08000000	/* setup packet */
#define TDESC1_AC		0x04000000	/* add crc disable */
#define TDESC1_TER		0x02000000	/* xmit end of ring */
#define TDESC1_TCH		0x01000000	/* second address chained */
#define TDESC1_DPD		0x00800000	/* disabled padding */
#define TDESC1_FTO		0x00400000	/* filtering type */

#define TDESC1_TBS2_MSK		0x003FF800	/* TBS2 buffer 2 size */
#define TDESC1_TBS1_MSK		0x000007FF	/* TBS2 buffer 1 size */

#define TDESC1_TBS1_PUT(x)	((x) & TDESC1_TBS1_MSK)	/* multiple of 4 */
#define TDESC1_TBS2_PUT(x)	(((x) << 11) & TDESC1_TBS2_MSK)

#define FLTR_FRM_SIZE		0xC0		/* filter frm size 192 bytes */
#define FLTR_FRM_SIZE_ULONGS	(FLTR_FRM_SIZE / sizeof (ULONG))
#define FLTR_FRM_ADRS_NUM	0x10		/* filter frm holds 16 addrs */
#define FLTR_FRM_ADRS_SIZE	0x06		/* size of each phys addrs */
#define FLTR_FRM_DEF_ADRS	0xFFFFFFFF	/* enet broad cast address */

/* MII/PHY defines */

#define	DC_MAX_PHY		32	/* max number of PHY devices */
#define	DC_MAX_LINK_TOUT	6	/* max link timeout (in secs) */
#define MII_PREAMBLE		((ULONG) 0xFFFFFFFF)

/* MII frame header format */

#define MII_SOF			0x4	/* start of frame */
#define MII_RD			0x2	/* op-code: Read */
#define	MII_WR			0x1	/* op-code: Write  */

/* MII PHY registers */

#define MII_PHY_CR		0x00	/* Control Register */
#define MII_PHY_SR		0x01	/* Status Register */
#define MII_PHY_ID0		0x02	/* Identifier Register 0 */
#define MII_PHY_ID1		0x03	/* Identifier Register 1 */
#define MII_PHY_ANA		0x04	/* Auto Negot'n Advertisement */
#define MII_PHY_ANLPA		0x05	/* Auto Negot'n Link Partner Ability */
#define MII_PHY_ANE		0x06	/* Auto Negot'n Expansion */
#define MII_PHY_ANP		0x07	/* Auto Negot'n Next Page TX */

/* ID0 values of PHY devices */

#define	MII_PHY_ID0_NATIONAL	0x2000	/* National TX */
#define	MII_PHY_ID0_BROADCOM	0x03e0	/* Broadcom T4 */
#define	MII_PHY_ID0_SEEQ	0x0016	/* Seeq T4 */
#define	MII_PHY_ID0_CYPRESS	0x0014	/* Cypress T4 */

/* MII_PHY control register */

#define	MII_PHY_CR_RESET	0x8000	/* reset */
#define	MII_PHY_CR_LOOP		0x4000	/* loopback enable */
#define	MII_PHY_CR_100M		0x2000	/* speed 100Mbps */
#define	MII_PHY_CR_10M		0x0000	/* speed 10Mbps */
#define	MII_PHY_CR_AUTO		0x1000	/* auto speed enable */
#define	MII_PHY_CR_OFF		0x0800	/* powerdown mode */
#define	MII_PHY_CR_ISOLAT	0x0400	/* isolate mode */
#define	MII_PHY_CR_RAN		0x0200	/* restart auto negotiate */
#define	MII_PHY_CR_FDX		0x0100	/* full duplex mode */
#define	MII_PHY_CR_CTE		0x0080	/* collision test enable */

/* MII PHY status register */

#define MII_PHY_SR_100T4	0x8000	/* 100BASE-T4 capable */
#define MII_PHY_SR_100TX_FD	0x4000	/* 100BASE-TX Full Duplex capable */
#define MII_PHY_SR_100TX_HD	0x2000	/* 100BASE-TX Half Duplex capable */
#define MII_PHY_SR_10TFD	0x1000	/* 10BASE-T Full Duplex capable */
#define MII_PHY_SR_10THD	0x0800	/* 10BASE-T Half Duplex capable */
#define MII_PHY_SR_ASS		0x0020	/* Auto Speed Selection Complete*/
#define MII_PHY_SR_RFD		0x0010	/* Remote Fault Detected */
#define MII_PHY_SR_AN		0x0008	/* Auto Negotiation capable */
#define MII_PHY_SR_LNK		0x0004	/* Link Status */
#define MII_PHY_SR_JABD		0x0002	/* Jabber Detect */
#define MII_PHY_SR_XC		0x0001	/* Extended Capabilities */

/* MII PHY Auto Negotiation Advertisement Register */

#define MII_PHY_ANA_TAF		0x03e0	/* Technology Ability Field */
#define MII_PHY_ANA_T4AM	0x0200	/* T4 Technology Ability Mask */
#define MII_PHY_ANA_TXAM	0x0180	/* TX Technology Ability Mask */
#define MII_PHY_ANA_FDAM	0x0140	/* Full Duplex Technology Ability Mask */
#define MII_PHY_ANA_HDAM	0x02a0	/* Half Duplex Technology Ability Mask */
#define MII_PHY_ANA_100M	0x0380	/* 100Mb Technology Ability Mask */
#define MII_PHY_ANA_10M		0x0060	/* 10Mb Technology Ability Mask */
#define MII_PHY_ANA_CSMA	0x0001	/* CSMA-CD Capable */

/* MII PHY Auto Negotiation Remote End Register */

#define MII_PHY_ANLPA_NP	0x8000	/* Next Page (Enable) */
#define MII_PHY_ANLPA_ACK	0x4000	/* Remote Acknowledge */
#define MII_PHY_ANLPA_RF	0x2000	/* Remote Fault */
#define MII_PHY_ANLPA_TAF	0x03e0	/* Technology Ability Field */
#define MII_PHY_ANLPA_T4AM	0x0200	/* T4 Technology Ability Mask */
#define MII_PHY_ANLPA_TXAM	0x0180	/* TX Technology Ability Mask */
#define MII_PHY_ANLPA_FDAM	0x0140	/* Full Duplex Technology Ability Mask */
#define MII_PHY_ANLPA_HDAM	0x02a0	/* Half Duplex Technology Ability Mask */
#define MII_PHY_ANLPA_100M	0x0380	/* 100Mb Technology Ability Mask */
#define MII_PHY_ANLPA_10M	0x0060	/* 10Mb Technology Ability Mask */
#define MII_PHY_ANLPA_CSMA	0x0001	/* CSMA-CD Capable */

#if 0
/* MII defines */

#define	MII_LINK_STATUS			0x4
#define MII_WRITE_DATA_POS		17
#define MII_READ_DATA_POS		19
#define PHY_ADDR_ALIGN			23
#define REG_ADDR_ALIGN			18
#define PHY_CONTROL_REG			0
#define PHY_STATUS_REG			1
#define MII_READ_FRAME			((ULONG) 0x60000000)

#define MII_WRITE			((ULONG) 0x00002000)
#define MII_WRITE_DATA			((ULONG) 0x00020000)
#define MII_WRITE_TS			((ULONG) 0x00042000)
#define MII_READ			((ULONG) 0x00044000)
#define	MII_READ_DATA			((ULONG) 0x00080000)
#define MII_CLOCK			((ULONG) 0x00010000)

#define MII_PHY_CTRL_RES_MSK		((USHORT) 0x007F)
#define MII_PHY_STAT_RES_MSK		((USHORT) 0x07C0)
#define MII_PHY_NWAY_RES_MSK		((USHORT) 0x1C00)
#define MII_PHY_NWAY_EXP_RES_BITS	((USHORT) 0xFFE0)
#endif

/* SROM Version defines */

#define MAX_GP_WRITES 10
#define MAX_MEDIAS 10

/* SROM Version Data types */

typedef struct {
   UCHAR MediaCode;
   UCHAR GPPortData;
   USHORT Command;
} CompactFormat;

typedef struct {
   UCHAR Length;
   UCHAR Type;
   UCHAR BlockData[4];
} ExtendedFormat0;

typedef struct {
   UCHAR Length;
   UCHAR Type;
   UCHAR BlockData[40];
} ExtendedFormat1;

typedef union InfoBlock {
   CompactFormat Compact;
   ExtendedFormat0 Extended0;
   ExtendedFormat1 Extended1;
} InfoBlock;

typedef struct {
   USHORT ConnType;
   UCHAR GPControl;
   UCHAR BlockCount;
   InfoBlock dcInfoBlock;
} InfoLeaf;

typedef struct {
   UINT ValCSR6;
   UINT GPCount;
   UINT GPValue[MAX_GP_WRITES];
   UINT GPResetLen;
   UINT GPResetValue[MAX_GP_WRITES];
} MediaSettingsType;

typedef struct {
   UINT ActiveMedia;
   UINT MediaFound;
   UINT GPMask;
   MediaSettingsType MediaArray[MAX_MEDIAS];
   UINT DontSwitch;
} MediaBlocksType;

#ifdef __cplusplus
}
#endif

#endif /* __INCif_dch */