if_dc.h

IXP425的BSP代码

/* if_dc.h - DEC 21x4x Ethernet LAN network interface header */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01h,09nov01,dat  Adding obsolescence warnings to outdated drivers
01g,30oct97,map  added definitions for MII/PHY
01f,29oct97,map  merged from mv2603/dec21140/dec21140.h (ver 01f) [SPR# 8176]
01e,24feb97,dbt  corrected previous modification history
01d,04sep96,dat  fixed comment within comment, spr 7106
01c,05sep95,vin  added setup/filter frame defines.
01b,04apr95,caf  changed name from "dcPci" to "dc".
01a,02mar95,vin  written.
*/

#ifndef __INCif_dch
#define __INCif_dch

#ifdef __cplusplus
extern "C" {
#endif

#warning "if_dc driver is obsolete, please use dec21x40End driver"

#define DECPCI_REG_OFFSET		0x08	/* quad word aligned */

/* Definitions for the flags field */

#define DC_PROMISCUOUS_FLAG     	0x01	/* set promiscuous mode */
#define DC_MULTICAST_FLAG		0x02	/* pass all multicast pkts */

/* Modes for 100-Mb/s Ethernet configuration */

#define DC_100_MB_FLAG			0x04	/* 100-Mb/s mode */	
#define DC_21140_FLAG			0x08	/* Lance chip is 21140 */
#define DC_FULLDUPLEX_FLAG		0x10	/* Full Duplex Mode */
#define DC_SCRAMBLER_FLAG		0x20	/* MII/SYM in scrambler mode */
#define DC_PCS_FLAG			0x40	/* MII/SYM in symbol mode */
#define DC_PS_FLAG			0x80	/* Serial Port selected  */
#define DC_ILOOPB_FLAG			0x100	/* Internal Loop Back Mode */
#define DC_ELOOPB_FLAG			0x200	/* External Loop Back Mode */
#define DC_HBE_FLAG			0x400	/* Heart Beat Enable Flag */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#  define PCISWAP(x)	LONGSWAP(x)		/* processor big endian */
#else
#  define PCISWAP(x)	(x)			/* processor little endian */
#endif /* _BYTE_ORDER == _BIG_ENDIAN */

/*
 * Receive Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */
typedef struct rDesc
    {
    ULONG	rDesc0;		/* status and ownership */
    ULONG	rDesc1;		/* control & buffer count */
    ULONG	rDesc2;		/* buffer address 1 */
    ULONG	rDesc3;		/* buffer address 2 */
    } DC_RDE;

/*
 * Transmit Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */
typedef struct tDesc
    {
    ULONG	tDesc0;		/* status and ownership */
    ULONG	tDesc1;		/* control & buffer count */
    ULONG	tDesc2;		/* buffer address 1 */
    ULONG	tDesc3;		/* buffer address 2 */
    } DC_TDE;

#define MIN_RDS		5	/* 5 buffers reasonable minimum */	
#define MIN_TDS		5	/* 5 buffers reasonable minimum */
#define NUM_RDS		32	/* default number of Recv descriptors */
#define NUM_TDS		32	/* default number of Xmit descriptors */

/* define CSRs and descriptors */

#define CSR0	0		/* csr 0 */
#define CSR1	1		/* csr 1 */
#define CSR2	2		/* csr 2 */
#define CSR3	3		/* csr 3 */
#define CSR4	4		/* csr 4 */
#define CSR5	5		/* csr 5 */
#define CSR6	6		/* csr 6 */
#define CSR7	7		/* csr 7 */
#define CSR8	8		/* csr 8 */
#define CSR9	9		/* csr 9 */
#define CSR10	10		/* csr 10 */
#define CSR11	11		/* csr 11 */
#define CSR12	12		/* csr 12 */
#define CSR13	13		/* csr 13 */
#define CSR14	14		/* csr 14 */
#define CSR15	15		/* csr 15 */

#define RDESC0	0		/* recv desc 0 */
#define RDESC1	1		/* recv desc 1 */
#define RDESC2	2		/* recv desc 2 */
#define RDESC3	3		/* recv desc 3 */

#define TDESC0	0		/* xmit desc 0 */
#define TDESC1	1		/* xmit desc 1 */
#define TDESC2	2		/* xmit desc 2 */
#define TDESC3	3		/* xmit desc 3 */
	
/* command status register read write */

#define CSR(base,x)		((ULONG)(base) + ((DECPCI_REG_OFFSET) * (x)))

#define READ_CSR(base,x)	(PCISWAP(*((ULONG *)CSR((base),(x)))))

#define WRITE_CSR(base,x,val)	(*((ULONG *)CSR((base),(x))) = PCISWAP((val)))


/* recv xmit descriptor read write */

#define DESC(base,x)		((ULONG)(base) + (4 * (x)))

#define READ_DESC(base,x)	(PCISWAP(*((ULONG *)(DESC((base),(x))))))

#define WRITE_DESC(base,x,val)	(*((ULONG *)(DESC((base),(x)))) = PCISWAP((val)))

/* Configuration ID Register added for DEC21140 */

#define SROM_SIZE	128
#define CFID_DEVID_MASK	0xFFFF0000
#define CFID_VENID_MASK	0x0000FFFF

#define DEC21040_ID	0x00020000
#define DEC21140_ID	0x00090000
#define PMC_ETHERNET	0x0000F801	/* Def MAC adrs for DEC PMC */
#define DEC_PMC_POS	10		/* MAC addr position on a DEC PMC ROM */

/* Definitions for fields and bits in the DC_DEVICE */

/* CSR0 Bus Mode Register */

#define CSR0_RML	0x00200000	/* Read Multiple */
#define CSR0_TAP_NO	0x00000000	/* no xmit auto polling */
#define CSR0_TAP_200	0x00020000	/* xmit poll every 200 usecs */
#define CSR0_TAP_800	0x00040000	/* xmit poll every 800 usecs */
#define CSR0_TAP_1600	0x00060000	/* xmit poll every 1.6 millsecs */
#define CSR0_CAL_NO	0x00000000	/* cache address alignment not used */
#define CSR0_CAL_08	0x00004000	/* 08 longword boundary aligned */
#define CSR0_CAL_16	0x00008000	/* 16 longword boundary aligned */
#define CSR0_CAL_32	0x0000c000	/* 32 longword boundary aligned */
#define CSR0_PBL_0	0x00000000	/* 0 longwords DMA'ed */
#define CSR0_PBL_1	0x00000100	/* 1 longwords DMA'ed */
#define CSR0_PBL_2	0x00000200	/* 2 longwords DMA'ed */
#define CSR0_PBL_4	0x00000400	/* 4 longwords DMA'ed */
#define CSR0_PBL_8	0x00000800	/* 8 longwords DMA'ed */
#define CSR0_PBL_16	0x00001000	/* 16 longwords DMA'ed */
#define CSR0_PBL_32	0x00002000	/* 32 longwords DMA'ed */
#define CSR0_DAS	0x00010000	/* Diagnostic Address Space */
#define CSR0_BLE	0x00000080	/* Big/little endian */
#define CSR0_BAR	0x00000002	/* Bus arbitration */
#define CSR0_SWR	0x00000001	/* software reset */

#define CSR0_PBL_MSK	0x00003F00	/* Dma burst length mask */
#define CSR0_PBL_VAL(x)	(((x) << 8) & CSR0_PBL_MSK)

#define CSR0_DSL_MSK	0x0000007C	/* Descriptor skip length */
#define CSR0_DSL_VAL(x) (((x) << 2) & CSR0_DSL_MSK)

/* CSR1 Transmit Poll Demand Register */

#define CSR1_TPD	0x00000001	/* Transmit poll demand */

/* CSR2 Recieve Poll Demand Register */

#define CSR2_RPD	0x00000001	/* Transmit poll demand */

/* CSR3 Receive List Base address Register */

#define CSR3_RDBA_MSK	0xFFFFFFFC	/* long word aligned */
#define CSR3_RDBA_VAL(x) ((x) & CSR3_RDBA_MSK)

/* CSR4 Transmit List Base address Register */

#define CSR4_TDBA_MSK	0xFFFFFFFC	/* long word aligned */
#define CSR4_TDBA_VAL(x) ((x) & CSR4_TDBA_MSK)

/* CSR5 Status register */

#define CSR5_ERR_PE	0x00000000	/* parity error */
#define CSR5_ERR_MA	0x00800000	/* Master abort */
#define CSR5_ERR_TA	0x01000000	/* target abort */
#define CSR5_TPS_ST	0x00000000	/* Stopped */
#define CSR5_TPS_RFTD	0x00100000	/* Running Fetch xmit descriptor */
#define CSR5_TPS_RWET	0x00200000	/* Running Wait for end of Xmission */
#define CSR5_TPS_RRBM	0x00300000	/* Running Read buff from memory */
#define CSR5_TPS_RSP	0x00500000	/* Running Set up packet */
#define CSR5_TPS_STFU	0x00600000	/* Suspended xmit FIFO underflow */
#define CSR5_TPS_RCTD	0x00700000	/* Running Close xmit descriptor */

#define CSR5_RPS_ST	0x00000000	/* stopped reset or stop rcv command */
#define CSR5_RPS_RFRD	0x00020000	/* Running Fetch rcv descriptor */
#define CSR5_RPS_RCEP	0x00040000	/* Running Check end of rcv packet */
#define CSR5_RPS_RWRP	0x00060000	/* Running Wait for rcv packet */
#define CSR5_RPS_SURB	0x00080000	/* Suspended - unavailable rcv buff */
#define CSR5_RPS_RCRD	0x000A0000	/* Running close rcv descriptor */
#define CSR5_RPS_RFFF	0x000C0000	/* flush frame from rcv FIFO */
#define CSR5_RPS_RQRF	0x000E0000	/* queue the rcv frame into rcv buff */

#define CSR5_NIS	0x00010000	/* normal interrupt summary */
#define CSR5_AIS	0x00008000	/* abnormal interrupt summary */
#define CSR5_SE		0x00002000	/* system error */
#define CSR5_LNF	0x00001000	/* link fail */

/* DEC21140 specific bit masks */
#define CSR5_GPTE	0x00000800	/* General Purpose Timer Expire */

#define CSR5_FD		0x00000800	/* Full-duplex short frame rcvd */
#define CSR5_AT		0x00000400	/* AUI / Ten base T Pin */
#define CSR5_RWT	0x00000200	/* rcv watchdog time-out */
#define CSR5_RPS	0x00000100	/* rcv process stopped */
#define CSR5_RU		0x00000080	/* rcv buffer unavailable */
#define CSR5_RI		0x00000040	/* rcv interrupt */
#define CSR5_UNF	0x00000020	/* xmit underflow */
#define CSR5_TJT	0x00000008	/* xmit jabber time-out */
#define CSR5_TU		0x00000004	/* xmit buffer unavailable */
#define CSR5_TPS	0x00000002	/* Xmit Process stopped */
#define CSR5_TI		0x00000001	/* xmit interrupt */

#define CSR5_RPS_MSK	0x000E0000	/* Rcv process state mask */
#define CSR5_TPS_MSK	0x00700000	/* Xmit process state mask */
#define CSR5_ERR_MSK	0x03800000	/* error mask */

/* CSR6 Operation Mode Register */

/* DEC21140 specific bit masks */
    
#define	CSR6_BIT25	0x02000000	/* BIT MUST ALWAYS BE 1 */
#define	CSR6_SCR	0x01000000	/* scrambler mode enable */
#define	CSR6_PCS	0x00800000	/* PCS mode enable */
#define	CSR6_TTM	0x00400000	/* transmit thresold mode */
#define	CSR6_SF		0x00200000	/* store forward mode */
#define	CSR6_HBD	0x00080000	/* heartbeat disabled */
#define	CSR6_PS		0x00040000	/* MII/SYM port selected */

/* Common Bit States for CSR6 */

#define	CSR6_CAE	0x00020000	/* capture effect enable */
#define	CSR6_BP		0x00010000	/* back pressure */
#define	CSR6_THR_072	0x00000000	/* threshold bytes 72 */
#define	CSR6_THR_096	0x00004000	/* threshold bytes 96 */
#define	CSR6_THR_128	0x00008000	/* threshold bytes 128 */
#define	CSR6_THR_160	0x0000C000	/* threshold bytes 160 */
#define	CSR6_ST		0x00002000	/* start/stop Xmit command */
#define	CSR6_FC		0x00001000	/* Force collision mode */
#define	CSR6_OM_NOR	0x00000000	/* normal mode */
#define	CSR6_OM_ILB	0x00000400	/* internal loopback mode */
#define	CSR6_OM_ELB	0x00000800	/* external loopback mode */
#define	CSR6_FD		0x00000200	/* Full Duplex mode */
#define	CSR6_FKD	0x00000100	/* Flaky oscillator disable */
#define	CSR6_PM		0x00000080	/* Pass all multicast */
#define	CSR6_PR		0x00000040	/* promiscuous mode */
#define	CSR6_SB		0x00000020	/* Start/Stop Back off counter */
#define	CSR6_IF		0x00000010	/* inverse filtering */
#define	CSR6_PB		0x00000008	/* pass bad frames */
#define	CSR6_HO		0x00000004	/* hash only filtering mode */
#define	CSR6_SR		0x00000002	/* start/stop receive command */
#define	CSR6_HP		0x00000001	/* hash/perfect recv filtering mode */

/* CSR7 Interrupt Mask register */

#define	CSR7_NIM	0x00010000	/* normal interrupt mask */
#define	CSR7_AIM	0x00008000	/* abnormal interrupt mask */
#define	CSR7_SEM	0x00002000	/* system error mask */
#define	CSR7_LFM	0x00001000	/* link fail mask */
#define	CSR7_FDM	0x00000800	/* full duplex mask */
#define	CSR7_ATM	0x00000400	/* aui/tp switch mask */
#define	CSR7_RWM	0x00000200	/* rcv watchdog time-out mask */
#define	CSR7_RSM	0x00000100	/* rcv stopped mask */
#define	CSR7_RUM	0x00000080	/* rcv buff unavailable mask */
#define	CSR7_RIM	0x00000040	/* rcv  interrupt mask */
#define	CSR7_UNM	0x00000020	/* underflow interrupt mask */ 
#define	CSR7_TJM	0x00000008	/* xmit jabber timer out mask */ 
#define	CSR7_TUM	0x00000004	/* xmit buff unavailable mask */
#define	CSR7_TSM	0x00000002	/* xmission stopped mask */
#define	CSR7_TIM	0x00000001	/* xmit interrupt mask */


/* CSR8 Missing Frame Counter */

#define	CSR8_MFO	0x00010000	/* missed frame overflow */
#define CSR8_MFC_MSK	0x0000FFFF	/* Missed frame counter mask */

/* CSR9 Ethernet Address ROM Register */

#define	CSR9_DNV	0x80000000	/* Data not valid */
#define CSR9_DAT_MSK	0x000000FF	/* data mask */
#define ENET_ROM_SIZE	8		/* ethernet rom register size */


/* CSR9 Serial Address ROM and MII Management Register for the DEC21140 */

#define	CSR9_040_DNVAL	0x80000000	/* Data not valid - 21040 */

#define	CSR9_MDI	0x00080000	/* MII mgmt data in - 21140+ */
#define	CSR9_MDI_SHF	19
#define	CSR9_MII_RD	0x00040000	/* MII mgmt read mode - 21140+ */
#define	CSR9_MII_WR	0x00000000	/* MII mgmt write mode - 21140+ */
#define	CSR9_MDO	0x00020000	/* MII mgmt write data - 21140+ */
#define	CSR9_MDO_SHF	17
#define	CSR9_MDC	0x00010000	/* MII mgmt clock - 21140+ */
#define	CSR9_RD		0x00004000	/* Read command - 21140+ */
#define	CSR9_WR		0x00002000	/* Write command - 21140+ */
#define	CSR9_BR		0x00001000	/* Boot rom select - 21140+ */
#define	CSR9_SR		0x00000800	/* Serial rom select - 21140+ */
#define	CSR9_REG	0x00000400	/* External register select - 21140+ */
#define CSR9_DATA	0x000000FF	/* Data */
#define CSR9_DATA_OUT	0x00000008	/* Shift read data from SROM - 21140+ */
#define	CSR9_DATA_IN	0x00000004	/* Shift write data into SROM - 21140+*/
#define CSR9_SROM_CLK	0x00000002	/* SCLK output to SROM - 21140+ */
#define	CSR9_SROM_CS	0x00000001	/* SerialROM chip select - 21140+ */

#define	CSR9_MII_DBIT_RD(X)	(((X) & CSR9_MDI) >> CSR9_MDI_SHF)
#define CSR9_MII_DBIT_WR(X)	(((X) & 0x1) << CSR9_MDO_SHF)