if_fei.h

IXP425的BSP代码

/* if_fei.h - Intel 82557 network interface header */

/* Copyright 1990-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01f,09nov01,dat  Adding obsolescence warnings to outdated drivers
01e,09mar99,cn   added typedef CSR_ID (SPR# 25242).
01d,17mar98,sbs  added PCI specific board definitions.
01c.13nov96,hdn  added two members to BOARD_INFO. removed two xxxAddrGet().
01b.06oct96,myz  added board specific data structure
01a,02sep96,dzb  written, based on v02h of h/drv/netif/if_ei.h.
*/

#ifndef __INCif_feih
#define __INCif_feih

#include "etherLib.h"

#warning "if_fei is obsolete, please use fei82557End driver"

#ifdef __cplusplus
extern "C" {
#endif

#if ((CPU_FAMILY==I960) && (defined __GNUC__))
#pragma align 1                 /* tell gcc960 not to optimize alignments */
#endif	/* CPU_FAMILY==I960 */

#define MC_FEI MC_EI  /* temp */

/* board specific infomation */
typedef struct
    {
    UINT32 vector;               /* interrupt vector number */
    UINT32 baseAddr;		 /* memory base address for CSR */
    UCHAR  enetAddr[6];		 /* ethernet address */
    int (*intEnable)(int unit);  /* board specific interrupt enable routine */
    int (*intDisable)(int unit); /* board specific interrupt disable routine */
    int (*intAck) (int unit);    /* interrupt ack */
    UINT32 (*sysLocalToBus)(int unit,UINT32 localAdr);
    UINT32 (*sysBusToLocal)(int unit,UINT32 sysAdr);

    /* configuration parameters, user can override in the BSP */
    UINT8 phyAddr;  /* PHY device address, valid addresses: 0-32 */
    UINT8 phySpeed;  
    UINT8 phyDpx;
    UINT8 fill0;

    UINT16 tcbTxThresh;

    UINT16 others; /* allow you write all bits to Mode Control Register in the
	   PHY device, don't touch it unless you know what you're doing. */

    UINT32 spare1;
    UINT32 spare2;
    UINT32 spare3;
    UINT32 spare4;
    } BOARD_INFO;

/* Intel PRO-100B PCI specific definitions */

#define PRO100B_PCI_VENDOR_ID   0x8086  /* PCI vendor ID */
#define PRO100B_PCI_DEVICE_ID   0x1229  /* PCI device ID */

/* constants needed within this file */

#define FEI_MAX_UNITS	4		/* max units supported */
#define FEI_CFD_DEF	32		/* default number of CFDs */
#define FEI_RFD_DEF	32		/* default number of RFDs */
#define FEI_RFD_LOAN	8		/* number RFDs that can be loaned */
#define EH_SIZE		14  		/* avoid structure padding issues */
#define N_MCAST		12

/* Intel 82557 endian safe link macros and structure definitions */

#define LINK_WR(pLink,value)						\
    (((pLink)->lsw = (UINT16)((UINT32)(value) & 0x0000ffff)),		\
    ((pLink)->msw  = (UINT16)(((UINT32)(value) >> 16) & 0x0000ffff)))

#define LINK_RD(pLink) ((pLink)->lsw | ((pLink)->msw << 16))

#define STAT_RD		LINK_RD		/* statistic read is a link read */
#define STAT_WR		LINK_WR		/* statistic write is a link write */
#define PORT_WR		LINK_WR		/* port write is a link write */

typedef struct fei_link 		/* FEI_LINK - endian resolvable link */
    {
    UINT16 		lsw;		/* least significant word */
    UINT16 		msw;		/* most significant word */
    } FEI_LINK;

/* Intel 82557 structure and offset */

typedef struct csr 		/* CSR - Control Status Registers */
    {
    volatile UINT16     scbStatus;
    volatile UINT16     scbCommand;

    FEI_LINK 		scbGP;		/* 0x04: SCB General Pointer */
    FEI_LINK 		port;		/* 0x08: PORT register */
    UINT16		flashCR;	/* 0x0c: FLASH Control Register */
    UINT16		eepromCR;	/* 0x0e: EEPROM Control Register */
    FEI_LINK		mdiCR;		/* 0x10: MDI Control Register */
    FEI_LINK 		rxbc;		/* 0x14: early RCV Byte Count */
    } CSR;

typedef CSR *	CSR_ID;

#define SCB_STATUS	0x00		/* SCB status byte */
#define SCB_CMD		0x02		/* SCB command byte */
#define SCB_POINTER	0x04		/* SCB pointer */
#define SCB_PORT	0x08		/* SCB port register */
#define SCB_FLASH	0x0c		/* SCB flash control register */
#define SCB_EEPROM	0x0e		/* SCB eeprom control register */
#define SCB_MDI		0x10		/* SCB mdi control register */
#define SCB_EARLYRX	0x14		/* SCB early receive byte count */

/* SCB Status Word byte mask definitions */

#define SCB_S_RUMASK	0x3c		/* RU status mask */
#define SCB_S_RUIDLE	0x00		/* RU is idle */
#define SCB_S_RUSUSP	0x04		/* RU is suspended */
#define SCB_S_RUNORSR	0x08		/* RU no more resources */
#define SCB_S_RURDY	0x10		/* RU is ready */
#define SCB_S_RUSUSPNR	0x24		/* RU is suspended/no more resources */
#define SCB_S_RUNORSRBD	0x28		/* RU no more resources/no more RBD's */
#define SCB_S_RURDYBD	0x30		/* RU is ready/no more RBD's */
#define SCB_S_CUMASK	0xc0		/* CU status mask */
#define SCB_S_CUIDLE	0x00		/* CU is idle */
#define SCB_S_CUSUSP	0x40		/* CU is suspended */
#define SCB_S_CUACTIVE	0x80		/* CU is active */
#define SCB_S_MASK      0xff

/* SCB STAT/ACK byte bit mask definitions */

#define SCB_S_STATMASK	0xfc00		/* stat mask */
#define SCB_S_SWI	0x0400		/* software generated interrupt */
#define SCB_S_MDI	0x0800		/* An MDI read or write cycle is done */
#define SCB_S_RNR	0x1000		/* RU left the ready state */
#define SCB_S_CNA	0x2000		/* CU left the active state */
#define SCB_S_CI	0x2000		/* CU entered the idle state */
#define SCB_S_FR	0x4000		/* RU finished receiveing a frame */
#define SCB_S_CX	0x8000		/* CU finished a cmd with I bit set */
#define SCB_S_TNO	0x8000		/* Tx command ended with not OK */

/* SCB Command byte bit mask definitions */

#define SCB_C_RUMASK	0x07		/* RU Command mask */
#define SCB_C_RUNOP	0x00		/* NOP */
#define SCB_C_RUSTART	0x01		/* RU start reception of frames */
#define SCB_C_RURESUME	0x02		/* RU resume reception of frames */
#define SCB_C_RUABORT	0x04		/* RU abort receiver immediately */
#define SCB_C_RULDHDS	0x05		/* RU load header data size */
#define SCB_C_RULDBASE	0x06		/* load RU base address */
#define SCB_C_RURBDRSM	0x07		/* RBD resume */
#define SCB_C_CUMASK	0x70		/* CU Command mask */
#define SCB_C_CUNOP	0x00		/* NOP */
#define SCB_C_CUSTART	0x10		/* CU start execution */
#define SCB_C_CURESUME	0x20		/* CU resume execution */
#define SCB_C_CULDDUMP	0x40		/* load dump counters address */
#define SCB_C_CUDUMP	0x50		/* dump stat counters */
#define SCB_C_CULDBASE	0x60		/* load CU base address */
#define SCB_C_CUDUMPRST	0x70		/* dump and reset stat counters */
#define SCB_CR_MASK     0xff

/* SCB Interrupt Control byte bit mask definitions */

#define SCB_C_M		0x0100		/* interrupt mask */
#define SCB_C_SI	0x0200		/* software generated interrupt */

typedef struct fei_count	/* FEI_COUNT - 82557 statistical counters */
    {
    FEI_LINK		txGood;		/* tx good frames */
    FEI_LINK		txMaxCol;	/* tx max collisions errors */
    FEI_LINK		txLateCol;	/* tx late collisions errors */
    FEI_LINK		txUnder;	/* tx underrun errors */
    FEI_LINK		txCRS;		/* tx carrier sense loss */
    FEI_LINK		txDefer;	/* tx deferred */
    FEI_LINK		txSglCol;	/* tx single collisions */
    FEI_LINK		txMultCol;	/* tx multiple collisions */
    FEI_LINK		txTotCol;	/* tx total collisions */
    FEI_LINK		rxGood;		/* rx good frames */
    FEI_LINK		rxCRC;		/* rx CRC errors */
    FEI_LINK		rxAllgn;	/* rx allignment errors */
    FEI_LINK		rxRsr;		/* rx resource errors */
    FEI_LINK		rxOver;		/* rx overrun errors */
    FEI_LINK		rxCDT;		/* rx collision detect errors */
    FEI_LINK		rxShort;	/* rx short frame errors */
    } FEI_COUNT;

/* PORT commands */

#define FEI_PORT_RESET		0x0	/* PORT reset command */
#define FEI_PORT_SELFTEST	0x1	/* PORT selftest command  */
#define FEI_PORT_SELRESET	0x2	/* PORT selective reset command */
#define FEI_PORT_DUMP		0x3	/* PORT dump command */

/* Action Command Descriptions */

typedef struct ac_iasetup 	/* AC_IASETUP - Individual Address Setup */
    {
    UINT8		ciAddress[6];	/* local ethernet address */
    UINT16		ciFill;
    } AC_IASETUP;