mcchip.h

IXP425的BSP代码

#define	SCC_ICR_IRQ	0x20	/* An Interrupt has occured		5 */

/* TIMER4_CR            0x1e    Tick Timer 4 Control Register   */
 
#define TIMER4_CR_CEN   0x01    /* Counter Enable                       0 */
#define TIMER4_CR_DIS   0x00    /* Counter Disable                      0 */
#define TIMER4_CR_COC   0x02    /* Clear On Compare                     1 */
#define TIMER4_CR_COVF  0x04    /* Clear Overflow Counter               2 */
 
/* TIMER3_CR            0x1f    Tick Timer 3 Control Register   */
 
#define TIMER3_CR_CEN   0x01    /* Counter Enable                       0 */
#define TIMER3_CR_DIS   0x00    /* Counter Disable                      0 */
#define TIMER3_CR_COC   0x02    /* Clear On Compare                     1 */
#define TIMER3_CR_COVF  0x04    /* Clear Overflow Counter               2 */

/* DRAM_SPACE_SIZE	0x24	DRAM Space Size Register */

#define	DRAM_SPACE_SIZE_1MB	0x00	/* 1 MB with 4 Mbit DRAMs        2-0 */
#define	DRAM_SPACE_SIZE_2MB	0x01	/* 2 MB with 4 Mbit DRAMs            */
#define	DRAM_SPACE_SIZE_4MB4	0x03	/* 4 MB with 4 Mbit DRAMs interleave */
#define	DRAM_SPACE_SIZE_4MB16	0x04	/* 4 MB with 16 Mbit DRAMs           */
#define	DRAM_SPACE_SIZE_8MB	0x05	/* 8 MB with 16 Mbit DRAMs           */
#define	DRAM_SPACE_SIZE_NONE	0x06	/* DRAM mezzanine is not present     */
#define	DRAM_SPACE_SIZE_16MB	0x07	/* 16 MB with 16 Mbit DRAMs int'leve */

/* DRAM_SRAM_OPTIONS	0x25	DRAM/SRAM Options Register */

#define	DRAM_SRAM_OPTIONS_DMASK	0x07	/* Mask for DRAM bits         2-0 */
#define	DRAM_SRAM_OPTIONS_SMASK 0x18	/* Mask for SRAM bits         4-3 */

/* SRAM_SPACE_SIZE	0x26	SRAM Space Size Register */

#define	SRAM_SPACE_512K		0x01	/* 512 KB */
#define	SRAM_SPACE_1MB		0x02	/* 1MB */
#define	SRAM_SPACE_2MB		0x03	/* 2MB */
#define	SRAM_SPACE_ENABLE	0x04	/* SRAM enable */

/* LANC_ERR_SR		0x28	LANC Error Status Register	*/

#define	LANC_ERR_SR_SCLR	0x01	/* Clear Error Status Bits	0 */
#define	LANC_ERR_SR_LTO		0x02	/* Local Time out error		1 */
#define	LANC_ERR_SR_EXT		0x04	/* VMEbus error			2 */
#define	LANC_ERR_SR_PRTY	0x08	/* DRAM Parity Error		3 */

/* LANC_IRQ_CR		0x2a	LANC Interrupt Control Register	*/

#define	LANC_IRQ_CR_ICLR	0x08	/* Clear IRQ in edge mode	3 */
#define	LANC_IRQ_CR_IEN		0x10	/* Interrupt Enable		4 */
#define	LANC_IRQ_CR_DIS		0x00	/* Interrupt Disable		4 */
#define	LANC_IRQ_CR_INT		0x20	/* Interrupt Status		5 */
#define	LANC_IRQ_CR_EDGE	0x40	/* Edge sensitive IRQ		6 */
#define	LANC_IRQ_CR_LEVEL	0x00	/* Level sensitive IRQ		6 */
#define	LANC_IRQ_CR_HIGH_LOW	0x00	/* IRQ on RISING or HIGH	7 */
#define	LANC_IRQ_CR_LOW_HIGH	0x80	/* IRQ on FALLING or LOW	7 */

/* LANC_BEICR		0x2b	LANC Bus Error Interrupt Control Register */

#define	LANC_BEICR_ICLR		0x08	/* Clear IRQ			3 */
#define	LANC_BEICR_IEN		0x10	/* Interrupt Enable		4 */
#define	LANC_BEICR_DIS		0x00	/* Interrupt Disable		4 */
#define	LANC_BEICR_IRQ		0x20	/* Interrupt Status		5 */
#define	LANC_BEICR_NO_SNOOP	0x00	/* Inhibit Snoop		7-6 */
#define	LANC_BEICR_SINK_DATA	0x40	/* Sink Data			7-6 */
#define	LANC_BEICR_INVALIDATE	0x80	/* Invalidate Line		7-6 */

/* SCSI_ERR_SR		0x2c	SCSI Error Status Register	*/

#define	SCSI_ERR_SR_SCLR	0x01	/* Clear Error Status Bits	0 */
#define	SCSI_ERR_SR_LTO		0x02	/* Local Time out error		1 */
#define	SCSI_ERR_SR_EXT		0x04	/* VMEbus error			2 */
#define	SCSI_ERR_SR_PRTY	0x08	/* DRAM Parity Error		3 */

/* VERSION_REG		0x2e	Version Register */

#define	VERSION_REG_SPEED	0x01	/* 0=25MHz, 1=33MHz             0 */
#define	VERSION_REG_VMECHIP	0x02	/* 0=present, 1=not installed   1 */
#define	VERSION_REG_SCSI	0x04	/* 0=present, 1=not installed   2 */
#define	VERSION_REG_ETHERNET	0x08	/* 0=present, 1=not installed   3 */
#define	VERSION_REG_MC68040	0x10	/* 1=MC68040, 0=MC68LC040       4 */
#define VERSION_REG_MC68060     0x10    /* 1=MC68060, 0=MC68LC060       4 */
#define	VERSION_REG_FLASH	0x20	/* address location             5 */
#define	VERSION_REG_IPIC2	0x40	/* 0=present, 1=not installed   6 */
#define	VERSION_REG_IPIC1	0x80	/* 0=present, 1=not installed   7 */

/* SCSI_IRQ_CR		0x2f	SCSI Interrupt Control Register	*/

#define	SCSI_IRQ_CR_IEN		0x10	/* Interrupt Enable		4 */
#define	SCSI_IRQ_CR_DIS		0x00	/* Interrupt Disable		4 */
#define	SCSI_IRQ_CR_IRQ		0x20	/* Interrupt Status		5 */

/* PROM_ACCESS_TIME	0x41	PROM Access Timer Control Register */

#define	PROM_ACCESS_25M_60NS	0x00	/* 25 MHz -  60 ns */
#define	PROM_ACCESS_25M_100NS	0x01	/*        - 100 ns */
#define	PROM_ACCESS_25M_140NS	0x02	/*        - 140 ns */
#define	PROM_ACCESS_25M_180NS	0x03	/*        - 180 ns */
#define	PROM_ACCESS_25M_220NS	0x04	/*        - 220 ns */
#define	PROM_ACCESS_25M_260NS	0x05	/*        - 260 ns */
#define	PROM_ACCESS_25M_300NS	0x06	/*        - 300 ns */
#define	PROM_ACCESS_25M_340NS	0x07	/*        - 340 ns */

#define PROM_ACCESS_33M_40NS    0x00    /* 33 MHz -  40 ns */
#define PROM_ACCESS_33M_70NS    0x01    /*        -  70 ns */
#define PROM_ACCESS_33M_100NS   0x02    /*        - 100 ns */
#define PROM_ACCESS_33M_130NS   0x03    /*        - 130 ns */
#define PROM_ACCESS_33M_160NS   0x04    /*        - 160 ns */
#define PROM_ACCESS_33M_190NS   0x05    /*        - 190 ns */
#define PROM_ACCESS_33M_210NS   0x06    /*        - 210 ns */
#define PROM_ACCESS_33M_240NS   0x07    /*        - 240 ns */

/* FLASH_ACCESS_TIME     0x42    PROM Access Timer Control Register */

#define FLASH_ACCESS_25M_60NS   0x00    /* 25 MHz -  60 ns */
#define FLASH_ACCESS_25M_100NS  0x01    /*        - 100 ns */
#define FLASH_ACCESS_25M_140NS  0x02    /*        - 140 ns */
#define FLASH_ACCESS_25M_180NS  0x03    /*        - 180 ns */
#define FLASH_ACCESS_25M_220NS  0x04    /*        - 220 ns */
#define FLASH_ACCESS_25M_260NS  0x05    /*        - 260 ns */
#define FLASH_ACCESS_25M_300NS  0x06    /*        - 300 ns */
#define FLASH_ACCESS_25M_340NS  0x07    /*        - 340 ns */

#define FLASH_ACCESS_33M_40NS   0x00    /* 33 MHz -  40 ns */
#define FLASH_ACCESS_33M_70NS   0x01    /*        -  70 ns */
#define FLASH_ACCESS_33M_100NS  0x02    /*        - 100 ns */
#define FLASH_ACCESS_33M_130NS  0x03    /*        - 130 ns */
#define FLASH_ACCESS_33M_160NS  0x04    /*        - 160 ns */
#define FLASH_ACCESS_33M_190NS  0x05    /*        - 190 ns */
#define FLASH_ACCESS_33M_210NS  0x06    /*        - 210 ns */
#define FLASH_ACCESS_33M_240NS  0x07    /*        - 240 ns */

/* ABORT_ICR            0x43    ABORT Switch Interrupt Control Register */

#define ABORT_ICR_ICLR  0x08    /* Clear IRQ                            3 */
#define ABORT_ICR_IEN   0x10    /* Interrupt Enable                     4 */
#define ABORT_ICR_DIS   0x00    /* Interrupt Disable                    4 */
#define ABORT_ICR_INT   0x20    /* Interrupt Status                     5 */

/* RESET_CR		0x44	RESET Switch Control Register */

#define	RESET_CR_BRFLI	0x10	/* Board Fail Status                    4 */
#define	RESET_CR_PURS	0x08	/* Power-up Reset Status                3 */
#define	RESET_CR_CPURS	0x04	/* Clear Power-up Reset                 2 */
#define	RESET_CR_BDFLO	0x02	/* Board Fail Assert                    1 */
#define	RESET_CR_RSWE	0x01	/* RESET Switch Enable                  0 */

/* WD_TIMER_CR		0x45	Watchdog Timer Control Register */

#define	WD_TIMER_CR_WDCS  0x40	/* Clear Watchdog Timeout Status        6 */
#define	WD_TIMER_CR_WDCC  0x20	/* Clear Watchdog Counter               5 */
#define	WD_TIMER_CR_WDTO  0x10	/* Watchdog Timer Status Bit            4 */
#define	WD_TIMER_CR_WDBFE 0x08	/* Watchdog Timeout Asserts Fail        3 */
#define	WD_TIMER_CR_WDRSE 0x02	/* Watchdog Timeout Asserts LRESET      1 */
#define	WD_TIMER_CR_WDEN  0x01	/* Watchdog Timer Enable                0 */
#define	WD_TIMER_CR_DIS   0x00  /* Watchdog Timer Disable                 */

/* WD_TIMEOUT_REG	0x46	Access and Watchdog Time Base Select Reg */

#define	WD_TIMEOUT_REG_WD_512US	0x00	/* Watchdog Timeout:  512us    3-0 */
#define	WD_TIMEOUT_REG_WD_1MS	0x01	/*                      1ms        */
#define	WD_TIMEOUT_REG_WD_2MS	0x02	/*                      2ms        */
#define WD_TIMEOUT_REG_WD_4MS   0x03    /*                      4ms        */
#define WD_TIMEOUT_REG_WD_8MS   0x04    /*                      8ms        */
#define WD_TIMEOUT_REG_WD_16MS  0x05    /*                     16ms        */
#define WD_TIMEOUT_REG_WD_32MS  0x06    /*                     32ms        */
#define WD_TIMEOUT_REG_WD_64MS  0x07    /*                     64ms        */
#define WD_TIMEOUT_REG_WD_128MS 0x08    /*                    128ms        */
#define WD_TIMEOUT_REG_WD_256MS 0x09    /*                    256ms        */
#define WD_TIMEOUT_REG_WD_512MS 0x0a    /*                    512ms        */
#define WD_TIMEOUT_REG_WD_1S    0x0b    /*                      1s         */
#define WD_TIMEOUT_REG_WD_4S    0x0c    /*                      4s         */
#define WD_TIMEOUT_REG_WD_16S   0x0d    /*                     16s         */
#define WD_TIMEOUT_REG_WD_32S   0x0e    /*                     32s         */
#define WD_TIMEOUT_REG_WD_64S   0x0f    /*                     64s         */

#define WD_TIMEOUT_REG_LB_8US   0x00    /* Local Bus Timeout:   8us    5-4 */
#define WD_TIMEOUT_REG_LB_64US  0x10    /*                     64us        */
#define WD_TIMEOUT_REG_LB_256US 0x20    /*                    256us        */
#define WD_TIMEOUT_REG_LB_NONE  0x30    /*                     none        */

/* DRAM_CONTROL_REG	0x48	DRAM Control Register */

#define	DRAM_CONTROL_REG_RAM_EN	0x01	/* DRAM Enable                   0 */
#define	DRAM_CONTROL_REG_PAR_EN	0x02	/* DRAM Parity Check Enable      1 */
#define	DRAM_CONTROL_REG_PAR_IN	0x04	/* DRAM Parity Error -> IRQ      2 */

/* MPU_STATUS_REG	0x4a	MPU Status Register */

#define	MPU_STATUS_REG_MLTO	0x01	/* MPU received Local Bus Timeout 0 */
#define	MPU_STATUS_REG_MLPE	0x02	/* MPU received Parity Error      1 */
#define	MPU_STATUS_REG_MLBE	0x04	/* MPU received TEA               2 */
#define	MPU_STATUS_REG_MCLR	0x08	/* Clear MPU status bits          3 */

#ifdef __cplusplus
}
#endif

#endif /* __INCmccchiph */