mcchip.h

IXP425的BSP代码

/* mcchip.h - Memory Controller ASIC (MCchip) */

/* Copyright 1984-1997 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,29sep98,fle  doc : made it refgen parsable
01c,10feb97,dat  added VERSION_REG_MC68060
01b,30sep96,db   fixed timeout constants(spr #7228)
01a,06jan93,ccc	 written.
*/

#ifdef	DOC
#define INCmcchiph
#endif	/* DOC */

#ifndef __INCmccchiph
#define __INCmccchiph

#ifdef __cplusplus
extern "C" {
#endif

/*
 * This file contains constants for the Memory Controller ASIC (MCchip).
 * The macro MCC_BASE_ADRS must be defined when including this header.
 */

#ifdef	_ASMLANGUAGE
#define CAST
#define	CASTINT
#else
#define CAST (char *)
#define	CASTINT (int *)
#endif	/* _ASMLANGUAGE */

/* on-board access, register definitions */

#define	MCC_REG_INTERVAL	1

#ifndef MCC_ADRS	/* to permit alternative board addressing */
#define MCC_ADRS(reg)   (CAST (MCC_BASE_ADRS + (reg * MCC_REG_INTERVAL)))
#define	MCC_ADRS_INT(reg)  (CASTINT (MCC_BASE_ADRS + \
				   (reg * MCC_REG_INTERVAL)))
#endif	/* MCC_ADRS */

#define MCC_ID			MCC_ADRS(0x00)	/* Chip ID 		      */
#define	MCC_REVISION		MCC_ADRS(0x01)	/* Chip Revision 	      */
#define	MCC_GCR			MCC_ADRS(0x02)	/* General Control Register   */
#define	MCC_VBR			MCC_ADRS(0x03)	/* Vector Base Register	      */
#define	MCC_TIMER1_CMP		MCC_ADRS_INT(0x04) /* Tick Timer 1 Comp Reg  */
#define	MCC_TIMER1_CMP_UU	MCC_ADRS(0x04)	/* Tick Timer 1 Comp Reg - UU */
#define	MCC_TIMER1_CMP_UL	MCC_ADRS(0x05)	/*			 - UL */
#define	MCC_TIMER1_CMP_LU	MCC_ADRS(0x06)	/*			 - LU */
#define	MCC_TIMER1_CMP_LL	MCC_ADRS(0x07)	/*			 - LL */
#define	MCC_TIMER1_CNT		MCC_ADRS_INT(0x08) /* Tick Timer 1 Count Reg */
#define	MCC_TIMER1_CNT_UU	MCC_ADRS(0x08)	/* Tick Timer 1 Cnt Reg - UU  */
#define	MCC_TIMER1_CNT_UL	MCC_ADRS(0x09)	/*			- UL  */
#define	MCC_TIMER1_CNT_LU	MCC_ADRS(0x0a)	/*			- LU  */
#define	MCC_TIMER1_CNT_LL	MCC_ADRS(0x0b)	/*			- LL  */
#define	MCC_TIMER2_CMP		MCC_ADRS_INT(0x0c) /* Tick Timer 2 Comp Reg  */
#define	MCC_TIMER2_CMP_UU	MCC_ADRS(0x0c)	/* Tick Timer 2 Comp Reg - UU */
#define	MCC_TIMER2_CMP_UL	MCC_ADRS(0x0d)	/*			 - UL */
#define	MCC_TIMER2_CMP_LU	MCC_ADRS(0x0e)	/*			 - LU */
#define	MCC_TIMER2_CMP_LL	MCC_ADRS(0x0f)	/*			 - LL */
#define	MCC_TIMER2_CNT		MCC_ADRS_INT(0x10) /* Tick Timer 2 Count Reg */
#define	MCC_TIMER2_CNT_UU	MCC_ADRS(0x10)	/* Tick Timer 2 Cnt Reg - UU  */
#define	MCC_TIMER2_CNT_UL	MCC_ADRS(0x11)	/*			- UL  */
#define	MCC_TIMER2_CNT_LU	MCC_ADRS(0x12)	/*			- LU  */
#define	MCC_TIMER2_CNT_LL	MCC_ADRS(0x13)	/*			- LL  */
#define	MCC_PRESCALE		MCC_ADRS(0x14)	/* Prescaler Count Register   */
#define	MCC_PRESCALE_CLK_ADJ	MCC_ADRS(0x15)	/* Prescaler Clock Adjust     */
#define	MCC_TIMER2_CR		MCC_ADRS(0x16)	/* Tick Timer 2 Ctrl Reg      */
#define	MCC_TIMER1_CR		MCC_ADRS(0x17)	/* Tick Timer 1 Ctrl Reg      */
#define	MCC_T4_IRQ_CR		MCC_ADRS(0x18)	/* Tick Timer 4 Inter CR      */
#define	MCC_T3_IRQ_CR		MCC_ADRS(0x19)	/* Tick Timer 3 Inter CR      */
#define	MCC_T2_IRQ_CR		MCC_ADRS(0x1a)	/* Tick Timer 2 Inter CR      */
#define	MCC_T1_IRQ_CR		MCC_ADRS(0x1b)	/* Tick Timer 1 Inter CR      */
#define	MCC_PARITY_ICR		MCC_ADRS(0x1c)	/* DRAM Parity Int Ctrl Reg   */
#define	MCC_SCC_ICR		MCC_ADRS(0x1d)	/* SCC Inter Ctrl Reg         */
#define	MCC_TIMER4_CR		MCC_ADRS(0x1e)	/* Tick Timer 4 Ctrl Reg      */
#define	MCC_TIMER3_CR		MCC_ADRS(0x1f)	/* Tick Timer 3 Ctrl Reg      */
#define	MCC_DRAM_BASE_AR_HIGH	MCC_ADRS(0x20)	/* DRAM Space Base Addr (hi)  */
#define	MCC_DRAM_BASE_AR_LOW	MCC_ADRS(0x21)	/* DRAM Space Base Addr (low) */
#define	MCC_SRAM_BASE_AR_HIGH	MCC_ADRS(0x22)	/* SRAM Space Base Addr (hi)  */
#define	MCC_SRAM_BASE_AR_LOW	MCC_ADRS(0x23)	/* SRAM Space Base Adrs (low) */
#define	MCC_DRAM_SPACE_SIZE	MCC_ADRS(0x24)	/* DRAM Space Size            */
#define	MCC_DRAM_SRAM_OPTIONS	MCC_ADRS(0x25)	/* DRAM/SRAM Options          */
#define	MCC_SRAM_SPACE_SIZE	MCC_ADRS(0x26)	/* SRAM Space Size            */
#define	MCC_LANC_ERR_SR		MCC_ADRS(0x28)	/* LANC Error Status Register */
#define	MCC_LANC_IRQ_CR		MCC_ADRS(0x2a)	/* LANC Inter Ctrl Reg	      */
#define	MCC_LANC_BEICR		MCC_ADRS(0x2b)	/* LANC Bus Error Inter CR    */
#define	MCC_SCSI_ERR_SR		MCC_ADRS(0x2c)	/* SCSI Error Status Register */
#define	MCC_GENERAL_INPUT	MCC_ADRS(0x2d)	/* General Purpose Input Reg  */
#define	MCC_VERSION_REG		MCC_ADRS(0x2e)	/* Board Version              */
#define	MCC_SCSI_IRQ_CR		MCC_ADRS(0x2f)	/* SCSI Inter Control Reg     */
#define	MCC_TIMER3_CMP		MCC_ADRS_INT(0x30) /* Tick Timer 3 Cmp Reg    */
#define	MCC_TIMER3_CMP_UU	MCC_ADRS(0x30)	/* Tick Timer 3 Cmp Reg - UU  */
#define	MCC_TIMER3_CMP_UL	MCC_ADRS(0x31)	/*                      - UL  */
#define	MCC_TIMER3_CMP_LU	MCC_ADRS(0x32)	/*                      - LU  */
#define	MCC_TIMER3_CMP_LL	MCC_ADRS(0x33)	/*                      - LL  */
#define	MCC_TIMER3_CNT		MCC_ADRS_INT(0x34) /* Tick Timer 3 Count Reg  */
#define	MCC_TIMER3_CNT_UU	MCC_ADRS(0x34)	/* Tick Timer 3 Cnt Reg - UU  */
#define	MCC_TIMER3_CNT_UL	MCC_ADRS(0x35)	/*                      - UL  */
#define	MCC_TIMER3_CNT_LU	MCC_ADRS(0x36)	/*                      - LU  */
#define	MCC_TIMER3_CNT_LL	MCC_ADRS(0x37)	/*                      - LL  */
#define	MCC_TIMER4_CMP		MCC_ADRS_INT(0x38) /* Tick Timer 4 Cmp Reg    */
#define MCC_TIMER4_CMP_UU       MCC_ADRS(0x38)  /* Tick Timer 4 Cmp Reg - UU  */
#define MCC_TIMER4_CMP_UL       MCC_ADRS(0x39)  /*                      - UL  */
#define MCC_TIMER4_CMP_LU       MCC_ADRS(0x3a)  /*                      - LU  */
#define MCC_TIMER4_CMP_LL       MCC_ADRS(0x3b)  /*                      - LL  */
#define MCC_TIMER4_CNT          MCC_ADRS_INT(0x3c) /* Tick Timer 4 Count Reg  */
#define MCC_TIMER4_CNT_UU       MCC_ADRS(0x3c)  /* Tick Timer 4 Cnt Reg - UU  */
#define MCC_TIMER4_CNT_UL       MCC_ADRS(0x3d)  /*                      - UL  */
#define MCC_TIMER4_CNT_LU       MCC_ADRS(0x3e)  /*                      - LU  */
#define MCC_TIMER4_CNT_LL       MCC_ADRS(0x3f)  /*                      - LL  */
#define	MCC_BUS_CLK_REG		MCC_ADRS(0x40)	/* Bus Clock Register         */
#define	MCC_PROM_ACCESS_TIME	MCC_ADRS(0x41)	/* PROM access time register  */
#define	MCC_FLASH_ACCESS_TIME	MCC_ADRS(0x42)	/* FLASH access time register */
#define	MCC_ABORT_ICR		MCC_ADRS(0x43)	/* ABORT switch int cont reg  */
#define	MCC_RESET_CR		MCC_ADRS(0x44)	/* RESET switch control reg   */
#define	MCC_WD_TIMER_CR		MCC_ADRS(0x45)	/* Watchdog timer control reg */
#define	MCC_WD_TIMEOUT_REG	MCC_ADRS(0x46)	/* Access and watchdog times  */
#define	MCC_DRAM_CONTROL_REG	MCC_ADRS(0x48)	/* DRAM control register      */
#define	MCC_MPU_STATUS_REG	MCC_ADRS(0x4a)	/* MPU status register        */
#define	MCC_PRESCALE_COUNT	MCC_ADRS_INT(0x4c) /* 32-bit prescale count   */

/* GCR			0x02	General Control Register	*/

#define	GCR_FAST_ON	0x01	/* Enable fast access for BBRAM		0 */
#define	GCR_FAST_OFF	0x00	/* Disable fast access for BBRAM	0 */
#define	GCR_MIEN_ON	0x02	/* Master Interrupt Enable		1 */
#define GCR_MIEN_OFF	0x00	/* Master Interrupt Enable OFF		1 */

/* VBR			0x03	Vector Base Register		*/

#define	MCC_INT_TT4		0x3	/* Tick Timer 4 IRQ		*/
#define	MCC_INT_TT3		0x4	/* Tick Timer 3 IRQ		*/
#define	MCC_INT_SCSI		0x5	/* SCSI IRQ			*/
#define	MCC_INT_LANC_ERR	0x6	/* LANC ERR			*/
#define	MCC_INT_LANC		0x7	/* LANC IRQ			*/
#define	MCC_INT_TT2		0x8	/* Tick Timer 2 IRQ		*/
#define	MCC_INT_TT1		0x9	/* Tick Timer 1 IRQ		*/
#define	MCC_INT_PARITY_ERROR	0xb	/* Parity Error IRQ		*/
#define	MCC_INT_ABORT		0xe	/* ABORT switch IRQ		*/

/* TIMER2_CR		0x16	Tick Timer 2 Control Register	*/

#define	TIMER2_CR_CEN	0x01	/* Counter Enable			0 */
#define	TIMER2_CR_DIS	0x00	/* Counter Disable			0 */
#define	TIMER2_CR_COC	0x02	/* Clear On Compare			1 */
#define	TIMER2_CR_COVF	0x04	/* Clear Overflow Counter		2 */

/* TIMER1_CR		0x17	Tick Timer 1 Control Register	*/

#define	TIMER1_CR_CEN	0x01	/* Counter Enable			0 */
#define	TIMER1_CR_DIS	0x00	/* Counter Disable			0 */
#define	TIMER1_CR_COC	0x02	/* Clear On Compare			1 */
#define	TIMER1_CR_COVF	0x04	/* Clear Overflow Counter		2 */

/* T4_IRQ_CR            0x18    Tick Timer 4 Interrupt Control Register */
 
#define T4_IRQ_CR_ICLR  0x08    /* Clear IRQ                            3 */
#define T4_IRQ_CR_IEN   0x10    /* Interrupt Enable                     4 */
#define T4_IRQ_CR_DIS   0x00    /* Interrupt Disable                    4 */
#define T4_IRQ_CR_INT   0x20    /* Interrupt Status                     5 */
 
/* T3_IRQ_CR            0x19    Tick Timer 3 Interrupt Control Register */
 
#define T3_IRQ_CR_ICLR  0x08    /* Clear IRQ                            3 */
#define T3_IRQ_CR_IEN   0x10    /* Interrupt Enable                     4 */
#define T3_IRQ_CR_DIS   0x00    /* Interrupt Disable                    4 */
#define T3_IRQ_CR_INT   0x20    /* Interrupt Status                     5 */

/* T2_IRQ_CR		0x1a	Tick Timer 2 Interrupt Control Register	*/

#define	T2_IRQ_CR_ICLR	0x08	/* Clear IRQ				3 */
#define	T2_IRQ_CR_IEN	0x10	/* Interrupt Enable			4 */
#define	T2_IRQ_CR_DIS	0x00	/* Interrupt Disable			4 */
#define	T2_IRQ_CR_INT	0x20	/* Interrupt Status			5 */

/* T1_IRQ_CR		0x1b	Tick Timer 1 Interrupt Control Register	*/

#define	T1_IRQ_CR_ICLR	0x08	/* Clear IRQ				3 */
#define	T1_IRQ_CR_IEN	0x10	/* Interrupt Enable			4 */
#define	T1_IRQ_CR_DIS	0x00	/* Interrupt Disable			4 */
#define	T1_IRQ_CR_INT	0x20	/* Interrupt Status			5 */

/* PARITY_ICR		0x1c	DRAM Parity Error Interrupt Control Register */

#define	PARITY_ICR_ICLR	0x08	/* Clear IRQ				3 */
#define	PARITY_ICR_IEN	0x10	/* Interrupt Enable			4 */
#define	PARITY_ICR_DIS	0x00	/* Interrupt Disable			4 */
#define	PARITY_ICR_INT	0x20	/* Interrupt Status			5 */

/* SCC_ICR		0x1d	SCC Interrupt Control Register	*/

#define	SCC_ICR_IEN	0x10	/* Interrupt Enable			4 */
#define	SCC_ICR_DIS	0x00	/* Interrupt Disable			4 */