m5206e.h

IXP425的BSP代码

/* UART 1/2 Input Auxilary Control Register */
#define M5206E_UART_ACR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x150, n))
/* UART 1/2 Interrupt Status Register */
#define M5206E_UART_ISR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x154, n))
/* UART 1/2 Interrupt Mask Register */
#define M5206E_UART_IMR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x154, n))
/* UART 1/2 Baud Rate Generator Prescale MSB */
#define M5206E_UART_BG1(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x158, n))
/* UART 1/2 Baud Rate Generator Prescale LSB */
#define M5206E_UART_BG2(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x15c, n))
/* UART 1/2 Interrupt Vector Register */
#define M5206E_UART_IVR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x170, n))
/* UART 1/2 Interrupt Port Register */
#define M5206E_UART_IP(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x174, n))
/* UART 1/2 Output Port Bit Set CMD */
#define M5206E_UART_OP1(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x178, n))
/* UART 1/2 Output Port Bit Reset CMD */
#define M5206E_UART_OP2(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x17c, n))

/* MBUS regs */
/* M-Bus Address Register */
#define M5206E_MADR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x1e0))
/* M-Bus Frequency Divider Register */
#define M5206E_MFDR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x1e4))
/* M-Bus Control Register */
#define M5206E_MBCR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x1e8))
/* M-Bus Control Register */
#define M5206E_MBSR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x1ec))
/* M-Bus Data I/O Register */
#define M5206E_MBDR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x1f0))

/* DMA 0 & 1 */
#define M5206E_DMA_REG(base, offset, chan)	\
		((base) + (offset) + ((chan) * 0x40))

/* Source Address Registers */
#define M5206E_DMA_DMASAR(base, n)	\
		(CAST_M5206E(volatile UINT32 *) M5206E_DMA_REG((base), 0x200, n))
/* Destination Address Registers */
#define M5206E_DMA_DMADAR(base, n)	\
		(CAST_M5206E(volatile UINT32 *) M5206E_DMA_REG((base), 0x204, n))
/* DMA Control Registers */
#define M5206E_DMA_DCR(base, n)	\
		(CAST_M5206E(volatile UINT16 *) M5206E_DMA_REG((base), 0x208, n))
/* Byte Count Registers */
#define M5206E_DMA_BCR(base, n)	\
		(CAST_M5206E(volatile UINT16 *) M5206E_DMA_REG((base), 0x20c, n))
/* Status Registers */
#define M5206E_DMA_DSR(base, n)	\
		(CAST_M5206E(volatile UINT8 *)  M5206E_DMA_REG((base), 0x210, n))
/* Interrupt Vector Registers */
#define M5206E_DMA_DIVR(base, n)	\
		(CAST_M5206E(volatile UINT8 *)  M5206E_DMA_REG((base), 0x214, n))


/* SIM Module Configuration Register definitions */

/* ICR - encode bits for ICR_xx registers */
#define M5206E_SIM_ICR_BITS(auto, level, priority)	\
			  ((((auto) & 0x01) << 7)	\
			   | (((level) & 0x07) << 2)	\
			   | ((priority) & 0x03))

/* IMR - Interrupt Mask Register bit definitions */
#define M5206E_IMR_IRQ1		(1 << 1)
#define M5206E_IMR_IRQ2		(1 << 2)
#define M5206E_IMR_IRQ3		(1 << 3)
#define M5206E_IMR_IRQ4		(1 << 4)
#define M5206E_IMR_IRQ5		(1 << 5)
#define M5206E_IMR_IRQ6		(1 << 6)
#define M5206E_IMR_IRQ7		(1 << 7)
#define M5206E_IMR_SWT		(1 << 8)
#define M5206E_IMR_TIMER1	(1 << 9)
#define M5206E_IMR_TIMER2	(1 << 10)
#define M5206E_IMR_MBUS		(1 << 11)
#define M5206E_IMR_UART1	(1 << 12)
#define M5206E_IMR_UART2	(1 << 13)
#define M5206E_IMR_DMA0		(1 << 14)
#define M5206E_IMR_DMA1		(1 << 15)

/* chip select mask registers */
#define M5206E_CS_CSMR_MASK_64k		0x00000000
#define M5206E_CS_CSMR_MASK_128k	0x00010000
#define M5206E_CS_CSMR_MASK_256k	0x00030000
#define M5206E_CS_CSMR_MASK_512k	0x00070000
#define M5206E_CS_CSMR_MASK_1M		0x000f0000
#define M5206E_CS_CSMR_MASK_2M		0x001f0000
#define M5206E_CS_CSMR_MASK_4M		0x003f0000
#define M5206E_CS_CSMR_MASK_8M		0x007f0000
#define M5206E_CS_CSMR_MASK_16M		0x00ff0000
#define M5206E_CS_CSMR_MASK_32M		0x01ff0000
#define M5206E_CS_CSMR_MASK_64M		0x03ff0000
#define M5206E_CS_CSMR_MASK_128M	0x07ff0000
#define M5206E_CS_CSMR_MASK_256M	0x0fff0000
#define M5206E_CS_CSMR_MASK_512M	0x1fff0000
#define M5206E_CS_CSMR_MASK_1G		0x3fff0000
#define M5206E_CS_CSMR_MASK_2G		0x7fff0000
#define M5206E_CS_CSMR_MASK_4G		0xffff0000
#define M5206E_CS_CSMR_CI		(1 << 5) 	/* /CS1 only */
#define M5206E_CS_CSMR_SC		(1 << 4)
#define M5206E_CS_CSMR_SD		(1 << 3)
#define M5206E_CS_CSMR_UC		(1 << 2)
#define M5206E_CS_CSMR_UD		(1 << 1)

/* chip select control regs (CSCR) & default mem control reg (DMCR) */
#define M5206E_CS_CSCR_WS(n)	((n) << 10)		/* wait-states */
#define M5206E_CS_CSCR_WS_15	M5206E_CS_CSCR_WS(15)
#define M5206E_CS_CSCR_WS_14	M5206E_CS_CSCR_WS(14)
#define M5206E_CS_CSCR_WS_13	M5206E_CS_CSCR_WS(13)
#define M5206E_CS_CSCR_WS_12	M5206E_CS_CSCR_WS(12)
#define M5206E_CS_CSCR_WS_11	M5206E_CS_CSCR_WS(11)
#define M5206E_CS_CSCR_WS_10	M5206E_CS_CSCR_WS(10)
#define M5206E_CS_CSCR_WS_9	M5206E_CS_CSCR_WS(9)
#define M5206E_CS_CSCR_WS_8	M5206E_CS_CSCR_WS(8)
#define M5206E_CS_CSCR_WS_7	M5206E_CS_CSCR_WS(7)
#define M5206E_CS_CSCR_WS_6	M5206E_CS_CSCR_WS(6)
#define M5206E_CS_CSCR_WS_5	M5206E_CS_CSCR_WS(5)
#define M5206E_CS_CSCR_WS_4	M5206E_CS_CSCR_WS(4)
#define M5206E_CS_CSCR_WS_3	M5206E_CS_CSCR_WS(3)
#define M5206E_CS_CSCR_WS_2	M5206E_CS_CSCR_WS(2)
#define M5206E_CS_CSCR_WS_1	M5206E_CS_CSCR_WS(1)
#define M5206E_CS_CSCR_WS_0	M5206E_CS_CSCR_WS(0)
#define M5206E_CS_CSCR_BRST	(1 << 9)	/* allow burst access */
#define M5206E_CS_CSCR_AA	(1 << 8)	/* auto-acknowledge */
#define M5206E_CS_CSCR_PS_32	(0 << 6)	/* 32-bit port size */
#define M5206E_CS_CSCR_PS_8	(1 << 6)	/* 8-bit port size */
#define M5206E_CS_CSCR_PS_16	(2 << 6)	/* 16-bit port size */
#define M5206E_CS_CSCR_EMAA	(1 << 5)	/* alternate master auto-ack */
#define M5206E_CS_CSCR_ASET	(1 << 4)	/* address setup enable */
#define M5206E_CS_CSCR_WRAH	(1 << 3)	/* write address hold enable */
#define M5206E_CS_CSCR_RDAH	(1 << 2)	/* read address hold enable */
#define M5206E_CS_CSCR_WR	(1 << 1)	/* write enable */
#define M5206E_CS_CSCR_RD	(1 << 0)	/* read enable */

/* DRAM Controller Timing Register (DCTR) */
#define M5206E_DCTR_DAEM	(1 << 15)	/* drive multiplexed addr */
#define M5206E_DCTR_EDO		(1 << 14)	/* EDO enable */
#define M5206E_DCTR_RCD		(1 << 12)	/* RAS-to-CAS delay */
#define M5206E_DCTR_RSH1	(1 << 10)	/* RAS hold time */
#define M5206E_DCTR_RSH0	(1 << 9)	/* RAS hold time */
#define M5206E_DCTR_RP1		(1 << 6)	/* RAS precharge time */
#define M5206E_DCTR_RP0		(1 << 5)	/* RAS prechange time */
#define M5206E_DCTR_CAS		(1 << 3)	/* CAS time */
#define M5206E_DCTR_CP		(1 << 1)	/* CAS precharge time */
#define M5206E_DCTR_CSR		(1 << 0)	/* CAS setup time */

/* dram controller mask registers */
#define M5206E_DCMR_MASK_128k	0x00000000
#define M5206E_DCMR_MASK_256k	0x00020000
#define M5206E_DCMR_MASK_512k	0x00060000
#define M5206E_DCMR_MASK_1M	0x000e0000
#define M5206E_DCMR_MASK_2M	0x001e0000
#define M5206E_DCMR_MASK_4M	0x003e0000
#define M5206E_DCMR_MASK_8M	0x007e0000
#define M5206E_DCMR_MASK_16M	0x00fe0000
#define M5206E_DCMR_MASK_32M	0x01fe0000
#define M5206E_DCMR_MASK_64M	0x03fe0000
#define M5206E_DCMR_MASK_128M	0x07fe0000
#define M5206E_DCMR_MASK_256M	0x0ffe0000
#define M5206E_DCMR_MASK_512M	0x1ffe0000
#define M5206E_DCMR_MASK_1G	0x3ffe0000
#define M5206E_DCMR_MASK_2G	0x7ffe0000
#define M5206E_DCMR_MASK_4G	0xfffe0000
#define M5206E_DCMR_SC		(1 << 4)
#define M5206E_DCMR_SD		(1 << 3)
#define M5206E_DCMR_UC		(1 << 2)
#define M5206E_DCMR_UD		(1 << 1)

/* DRAM Controller Control Register */
#define M5206E_DCCR_PS_32	(0 << 6)	/* 32-bit port size */
#define M5206E_DCCR_PS_8	(1 << 6)	/* 8-bit port size */
#define M5206E_DCCR_PS_16	(3 << 6)	/* 16-bit port size */
#define M5206E_DCCR_BPS_512B	(0 << 4)	/* 512byte bank page size */
#define M5206E_DCCR_BPS_1K	(1 << 4)	/* 1Kb bank page size */
#define M5206E_DCCR_BPS_2K	(2 << 4)	/* 2Kb bank page size */
#define M5206E_DCCR_MODE_NORMAL	(0 << 2)	/* normal page mode */
#define M5206E_DCCR_MODE_BURST	(1 << 2)	/* burst page mode */
#define M5206E_DCCR_MODE_FAST	(3 << 2)	/* fast page mode */
#define M5206E_DCCR_WR		(1 << 1)	/* Signal on write xfer */
#define M5206E_DCCR_RD		(1 << 0)	/* Signal on read xfer */

#ifdef __cplusplus
}
#endif

#endif /* __INCm5206eh */