m5206e.h

IXP425的BSP代码

/* m5206e.h - Motorola MCF5206e CPU control registers */

/* Copyright 1994-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,05mar01,hjg  Created from m5206.h
*/

/*
This file contains I/O addresses and related constants for the MCF5206e
*/

#ifndef __INCm5206eh
#define __INCm5206eh

#ifdef __cplusplus
extern "C" {
#endif

/*
Need to use a distinct cast macro in order to not conflict with other
include files.
*/

#ifdef	_ASMLANGUAGE
#define	CAST_M5206E(x)		
#else	/* _ASMLANGUAGE */
#define	CAST_M5206E(x)		(x)
#endif	/* _ASMLANGUAGE */

/* Size of internal SRAM */

#define M5206E_SRAM_SIZE		8192		/* size of internal SRAM */

/* System Integration Module register addresses */

#define M5206E_SIM_SIMR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x003))
/* External IP1-7 */
#define M5206E_SIM_ICR1(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x014))
#define M5206E_SIM_ICR2(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x015))
#define M5206E_SIM_ICR3(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x016))
#define M5206E_SIM_ICR4(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x017))
#define M5206E_SIM_ICR5(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x018))
#define M5206E_SIM_ICR6(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x019))
#define M5206E_SIM_ICR7(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x01a))
/* SWT */
#define M5206E_SIM_ICR8(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x01b))
/* Timer 1 INT */
#define M5206E_SIM_ICR9(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x01c))
/* Timer 2 INT */
#define M5206E_SIM_ICR10(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x01d))
/* MBUS interrupt */
#define M5206E_SIM_ICR11(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x01e))
/* UART 1 INT */
#define M5206E_SIM_ICR12(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x01f))
/* UART 2 INT */
#define M5206E_SIM_ICR13(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x020))
/* DMA Channel 0 Interrupt */
#define M5206E_SIM_ICR14(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x021))
/* DMA Channel 1 Interrupt */
#define M5206E_SIM_ICR15(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x022))
/* Interrupt Mask Register */
#define M5206E_SIM_IMR(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x036))
/* Interrupt Pending Register */
#define M5206E_SIM_IPR(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x03a))
/* Reset Status Register */
#define M5206E_SIM_RSR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x040))
/* System Protection Control Register */
#define M5206E_SIM_SYPCR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x041))
/* Software Watchdog Interrupt Vector Register */
#define M5206E_SIM_SWIVR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x042))
/* Software Watchdog Service Register */
#define M5206E_SIM_SWSR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x043))

/* DRAM */
/* DRAM Controller Refresh */
#define M5206E_DCRR(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x046))
/* DRAM Controller Timing Register */
#define M5206E_DCTR(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x04a))
/* DRAM Controller Address Register - Bank 0 */
#define M5206E_DCAR0(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x04c))
/* DRAM Controller Mask Register - Bank 0 */
#define M5206E_DCMR0(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x050))
/* DRAM Controller Control Register - Bank 0 */
#define M5206E_DCCR0(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x057))
/* DRAM Controller Address Register - Bank 1 */
#define M5206E_DCAR1(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x058))
/* DRAM Controller Mask Register - Bank 1 */
#define M5206E_DCMR1(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x05c))
/* DRAM Controller Control Register - Bank 1 */
#define M5206E_DCCR1(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x063))

/* Chip-Select Address Register - Bank 0 */
#define M5206E_SIM_CSAR0(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x064))
/* Chip-Select Mask Register - Bank 0 */
#define M5206E_SIM_CSMR0(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x068))
/* Chip-Select Control Register - Bank 0 */
#define M5206E_SIM_CSCR0(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x06e))
/* Chip-Select Address Register - Bank 1 */
#define M5206E_SIM_CSAR1(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x070))
/* Chip-Select Mask Register - Bank 1 */
#define M5206E_SIM_CSMR1(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x074))
/* Chip-Select Control Register - Bank 1 */
#define M5206E_SIM_CSCR1(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x07a))
/* Chip-Select Address Register - Bank 2 */
#define M5206E_SIM_CSAR2(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x07c))
/* Chip-Select Mask Register - Bank 2 */
#define M5206E_SIM_CSMR2(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x080))
/* Chip-Select Control Register - Bank 2 */
#define M5206E_SIM_CSCR2(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x086))
/* Chip-Select Address Register - Bank 3 */
#define M5206E_SIM_CSAR3(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x088))
/* Chip-Select Mask Register - Bank 3 */
#define M5206E_SIM_CSMR3(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x08c))
/* Chip-Select Control Register - Bank 3 */
#define M5206E_SIM_CSCR3(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x092))
/* Chip-Select Address Register - Bank 4 */
#define M5206E_SIM_CSAR4(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x094))
/* Chip-Select Mask Register - Bank 4 */
#define M5206E_SIM_CSMR4(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x098))
/* Chip-Select Control Register - Bank 4 */
#define M5206E_SIM_CSCR4(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x09e))
/* Chip-Select Address Register - Bank 5 */
#define M5206E_SIM_CSAR5(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0a0))
/* Chip-Select Mask Register - Bank 5 */
#define M5206E_SIM_CSMR5(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x0a4))
/* Chip-Select Control Register - Bank 5 */
#define M5206E_SIM_CSCR5(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0aa))
/* Chip-Select Address Register - Bank 6 */
#define M5206E_SIM_CSAR6(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0ac))
/* Chip-Select Mask Register - Bank 6 */
#define M5206E_SIM_CSMR6(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x0b0))
/* Chip-Select Control Register - Bank 6 */
#define M5206E_SIM_CSCR6(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0b6))
/* Chip-Select Address Register - Bank 7 */
#define M5206E_SIM_CSAR7(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0b8))
/* Chip-Select Mask Register - Bank 7 */
#define M5206E_SIM_CSMR7(base)	(CAST_M5206E(volatile UINT32 *)((base) + 0x0bc))
/* Chip-Select Control Register - Bank 7 */
#define M5206E_SIM_CSCR7(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0c2))
/* Default Memory Control Register */
#define M5206E_SIM_DMCR(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0c6))
/* Pin Assignment Register */
#define M5206E_SIM_PAR(base)	(CAST_M5206E(volatile UINT16 *)((base) + 0x0ca))
/* Port A Data Direction Register */
#define M5206E_SIM_PADDR(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x1c5))
/* Port A Data Register */
#define M5206E_SIM_PADAT(base)	(CAST_M5206E(volatile UINT8  *)((base) + 0x1c9))

/* Timers 1 and 2. */

#define M5206E_TIMER_REG(base, offset, timer)	\
			((base) + ((timer) * 0x20) + (offset))

/* Timer 1/2 Mode Register */
#define M5206E_TIMER_TMR(base, n)	\
		(CAST_M5206E(volatile UINT16 *) M5206E_TIMER_REG(base, 0x100, n))
/* Timer 1/2 Reference Register */
#define M5206E_TIMER_TRR(base, n)	\
		(CAST_M5206E(volatile UINT16 *) M5206E_TIMER_REG(base, 0x104, n))
/* Timer 1/2 Capture Register */
#define M5206E_TIMER_TCR(base, n)	\
		(CAST_M5206E(volatile UINT16 *) M5206E_TIMER_REG(base, 0x108, n))
/* Timer 1/2 Counter */
#define M5206E_TIMER_TCN(base, n)	\
		(CAST_M5206E(volatile UINT16 *) M5206E_TIMER_REG(base, 0x10c, n))
/* Timer 1/2 Event Register */
#define M5206E_TIMER_TER(base, n)	\
		(CAST_M5206E(volatile UINT8  *) M5206E_TIMER_REG(base, 0x111, n))

/* UART 1 & 2 */
#define M5206E_UART_REG(base, offset, chan)	\
		((base) + (offset) + ((chan) * 0x40))

/* UART 1/2 Mode Registers */
#define M5206E_UART_MR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x140, n))
/* UART 1/2 Status Register */
#define M5206E_UART_SR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x144, n))
/* UART 1/2 Clock-Select Register */
#define M5206E_UART_CSR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x144, n))
/* UART 1/2 Command Register */
#define M5206E_UART_CR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x148, n))
/* UART 1/2 Receive Buffer */
#define M5206E_UART_RB(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x14c, n))
/* UART 1/2 Transmit Buffer */
#define M5206E_UART_TB(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x14c, n))
/* UART 1/2 Input Port Change Register */
#define M5206E_UART_IPCR(base, n)	\
		(CAST_M5206E(volatile UINT8 *) M5206E_UART_REG((base), 0x150, n))