m5407.h

IXP425的BSP代码

/* m5407.h - Motorola MCF5407 CPU control registers */

/* Copyright 1994-2000 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,27sep00,dh   written (based on m5307.h)
*/

/*
This file contains I/O addresses and related constants for the MCF5407
*/

#ifndef __INCm5407h
#define __INCm5407h

#ifdef __cplusplus
extern "C" {
#endif

/*
Need to use a distinct cast macro in order to not conflict with other
include files.
*/

#ifdef	_ASMLANGUAGE
#define	CAST_M5407(x)		
#else	/* _ASMLANGUAGE */
#define	CAST_M5407(x)		(x)
#endif	/* _ASMLANGUAGE */

/* Size of internal SRAM */

#define M5407_SRAM_SIZE		4096		/* size of SRAM */
#define M5407_SRAM_BANK_SIZE	2048		/* size of SRAM bank */
#define M5407_DCACHE_SIZE	8192		/* size of data cache */
#define M5407_ICACHE_SIZE	16384		/* size of instruction cache */

/* ACRs (access control registers) */

#define M5407_ACR_ADDR_BASE(n)	((n) & 0xff000000)	/* region base */
#define M5407_ACR_ADDR_MASK(n)	(((n)>>8) & 0x00ff0000)	/* region mask */
#define M5407_ACR_ENABLE	(1 << 15)		/* enable ACR */
#define M5407_ACR_MODE_USER	(0 << 13)	/* match if user */
#define M5407_ACR_MODE_SUPER	(1 << 13)	/* match if supervisor */
#define M5407_ACR_MODE_ANY	(2 << 13)	/* match any */
#define M5407_ACR_WRITETHROUGH	(0 << 5)	/* cacheable, writethrough */
#define M5407_ACR_COPYBACK	(1 << 5)	/* cacheable, copyback */
#define M5407_ACR_INH_PRECISE	(2 << 5)	/* cache-inhibited, precise */
#define M5407_ACR_INH_IMPRECISE	(3 << 5)	/* cache-inhibited, imprecise*/
#define M5407_ACR_WP		(1 << 2)	/* write-protect */

/* System Integration Module register addresses */

#define M5407_SIM_RSR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x000))
#define M5407_SIM_SYPCR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x001))
#define M5407_SIM_SWIVR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x002))
#define M5407_SIM_SWSR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x003))

#define M5407_SIM_PAR(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x004))
#define M5407_SIM_IRQPAR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x006))
#define M5407_SIM_PLLCR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x008))
#define M5407_SIM_MPARK(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x00c))

#define M5407_SIM_IPR(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x040))
#define M5407_SIM_IMR(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x044))

/* Autovector control */
#define MCF5407_SIM_AVCR_BLK	(1 << 0)
#define MCF5407_SIM_AVCR_AVEC1	(1 << 1)
#define MCF5407_SIM_AVCR_AVEC2	(1 << 2)
#define MCF5407_SIM_AVCR_AVEC3	(1 << 3)
#define MCF5407_SIM_AVCR_AVEC4	(1 << 4)
#define MCF5407_SIM_AVCR_AVEC5	(1 << 5)
#define MCF5407_SIM_AVCR_AVEC6	(1 << 6)
#define MCF5407_SIM_AVCR_AVEC7	(1 << 7)

#define M5407_SIM_AVCR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x04b))

#define M5407_SIM_ICR_SWT(base)		\
	(CAST_M5407(volatile UINT8  *)((base) + 0x04c))
#define M5407_SIM_ICR_TIMER1(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x04d))
#define M5407_SIM_ICR_TIMER2(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x04e))
#define M5407_SIM_ICR_MBUS(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x04f))
#define M5407_SIM_ICR_UART1(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x050))
#define M5407_SIM_ICR_UART2(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x051))
#define M5407_SIM_ICR_DMA0(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x052))
#define M5407_SIM_ICR_DMA1(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x053))
#define M5407_SIM_ICR_DMA2(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x054))
#define M5407_SIM_ICR_DMA3(base)	\
	(CAST_M5407(volatile UINT8  *)((base) + 0x055))
#define M5407_SIM_ICR_ICR10(base)		\
	(CAST_M5407(volatile UINT8  *)((base) + 0x056))
#define M5407_SIM_ICR_ICR11(base)		\
	(CAST_M5407(volatile UINT8  *)((base) + 0x057))

/* Chip select registers */

#define M5407_SIM_CSAR0(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x080))
#define M5407_SIM_CSMR0(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x084))
#define M5407_SIM_CSCR0(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x08a))

#define M5407_SIM_CSAR1(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x08c))
#define M5407_SIM_CSMR1(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x090))
#define M5407_SIM_CSCR1(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x096))

#define M5407_SIM_CSAR2(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x098))
#define M5407_SIM_CSMR2(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x09c))
#define M5407_SIM_CSCR2(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0a2))

#define M5407_SIM_CSAR3(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0a4))
#define M5407_SIM_CSMR3(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x0a8))
#define M5407_SIM_CSCR3(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0ae))

#define M5407_SIM_CSAR4(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0b0))
#define M5407_SIM_CSMR4(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x0b4))
#define M5407_SIM_CSCR4(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0ba))

#define M5407_SIM_CSAR5(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0bc))
#define M5407_SIM_CSMR5(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x0c0))
#define M5407_SIM_CSCR5(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0c6))

#define M5407_SIM_CSAR6(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0c8))
#define M5407_SIM_CSMR6(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x0cc))
#define M5407_SIM_CSCR6(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0d2))

#define M5407_SIM_CSAR7(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0d4))
#define M5407_SIM_CSMR7(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x0d8))
#define M5407_SIM_CSCR7(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x0de))


#define M5407_SIM_DCR(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x100))
#define M5407_SIM_DACR0(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x108))
#define M5407_SIM_DMR0(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x10c))
#define M5407_SIM_DACR1(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x110))
#define M5407_SIM_DMR1(base)	(CAST_M5407(volatile UINT32 *)((base) + 0x114))
#define M5407_SIM_TMR0(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x140))
#define M5407_SIM_TRR0(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x144))
#define M5407_SIM_TCR0(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x148))
#define M5407_SIM_TCN0(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x14c))
#define M5407_SIM_TER0(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x151))
#define M5407_SIM_TMR1(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x180))
#define M5407_SIM_TRR1(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x184))
#define M5407_SIM_TCR1(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x188))
#define M5407_SIM_TCN1(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x18c))
#define M5407_SIM_TER1(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x191))

#define M5407_UART_MR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1c0 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_SR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1c4 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_CSR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1c4 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_CR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1c8 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_RB(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1cc + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_TB(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1cc + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_IPCR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1d0 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_ACR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1d0 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_ISR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1d4 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_IMR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1d4 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_BG1(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1d8 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_BG2(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1dc + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_IVR(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1f0 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_IP(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1f4 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_OP2(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1f8 + ((uart) ? 0x40 : 0x00)))
#define M5407_UART_OP1(base, uart)	\
	(CAST_M5407(volatile UINT8 *)((base) + 0x1fc + ((uart) ? 0x40 : 0x00)))

#define M5407_SIM_PADDR(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x244))
#define M5407_SIM_PADAT(base)	(CAST_M5407(volatile UINT16 *)((base) + 0x248))
#define M5407_SIM_MADR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x280))
#define M5407_SIM_MFDR(base)	(CAST_M5407(volatile UINT8  *)((base) + 0x284))