m68562.h

IXP425的BSP代码

/* m68562.h - Motorola M68562 Serial I/O Chip header */

/* Copyright 1984-1992 Wind River Systems, Inc. */
/*
modification history
--------------------
01k,22sep92,rrr  added support for c++
01j,02jul92,caf  added TY_CO_DEV and function declarations for 5.1 upgrade.
		 for 5.0.x compatibility, define INCLUDE_TY_CO_DRV_50 when
		 including this header.
01i,26may92,rrr  the tree shuffle
01h,04oct91,rrr  passed through the ansification filter
		  -changed ASMLANGUAGE to _ASMLANGUAGE
		  -changed copyright notice
01g,05oct90,shl  added copyright notice.
                 made #endif ANSI style.
01f,11jun90,gae  added _ASMLANGUAGE version.
		 simplified DUSCC macros, but kept 4.0.2 version temporarily.
		 fixed def'n of DUSCC_OMR_GPO1_1 to be O (oh) not 0 (zero).
01e,01mar89,jcc  incorporated DUSCC_REG_ADDR_INTERVAL into definitions.
01d,28nov88,jcf  change M562 to DUSCC because thats easier to remember.
01c,10aug88,gae  got rid of ^L which are unloved by some assemblers.
01b,21jun88,mcl  changed to be generic, not just mz7122; adds documentation.
01a,26jan88,sah  written.
*/

#ifndef __INCm68562h
#define __INCm68562h

#ifdef __cplusplus
extern "C" {
#endif

/*
 * The macro's DUSCC_BASE_ADRS and DUSCC_REG_INTERVAL must be defined
 * when including this header.
 *
 * define INCLUDE_TY_CO_DRV_50 when using this header if you are using
 * a VxWorks 5.0-style serial driver (tyCoDrv.c).
 */

#ifdef	_ASMLANGUAGE

#define	CAST

#else	/* _ASMLANGUAGE */

#define	CAST	(char *)

#include "tyLib.h"

#ifndef  INCLUDE_TY_CO_DRV_50

typedef struct          /* TY_CO_DEV */
    {
    TY_DEV	    tyDev;
    BOOL	    created;	    /* true if this device has been created */
    char	    numChannels;    /* number of channels to support */
    volatile char * rx_data;        /* receiver data port */
    volatile char * tx_data;        /* transmitter data port */
    volatile char * ttr;            /* transmitter timer register */
    volatile char * rtr;            /* receiver timer register */
    volatile char * ier;            /* interrupt enable register */
    volatile char * gsr;            /* general status register */
    volatile char * rsr;            /* receiver status register */
    volatile char * cmr1;
    volatile char * cmr2;
    volatile char * tpr;
    volatile char * rpr;
    volatile char * omr;
    volatile char * ccr;
    char	    rx_rdy;         /* receiver ready bit */
    char	    tx_rdy;         /* transmitter ready bit */
    } TY_CO_DEV;

#endif	/* INCLUDE_TY_CO_DRV_50 */

#endif	/* _ASMLANGUAGE */

#define DUSCC_ADRS(reg)   (CAST (DUSCC_BASE_ADRS+(reg*DUSCC_REG_INTERVAL)))

/* port registers */

#define DUSCC_CMR1A	DUSCC_ADRS(0x00)	/* channel mode reg. 1    */
#define DUSCC_CMR2A	DUSCC_ADRS(0x01)	/* channel mode reg. 2    */
#define DUSCC_S1RA	DUSCC_ADRS(0x02)	/* secondary adrs reg1    */
#define DUSCC_S2RA	DUSCC_ADRS(0x03)	/* secondary adrs reg2    */
#define DUSCC_TPRA	DUSCC_ADRS(0x04)	/* tx parameter reg.      */
#define DUSCC_TTRA	DUSCC_ADRS(0x05)	/* tx timing reg.         */
#define DUSCC_RPRA	DUSCC_ADRS(0x06)	/* rx parameter reg.      */
#define DUSCC_RTRA	DUSCC_ADRS(0x07)	/* rx timing reg.         */
#define DUSCC_CTPRHA	DUSCC_ADRS(0x08)	/* counter preset high    */
#define DUSCC_CTPRLA	DUSCC_ADRS(0x09)	/* counter preset low     */
#define DUSCC_CTCRA	DUSCC_ADRS(0x0a)	/* counter control reg.   */
#define DUSCC_OMRA	DUSCC_ADRS(0x0b)	/* output/misc. reg.      */
#define DUSCC_CTHA	DUSCC_ADRS(0x0c)	/* counter/timer high     */
#define DUSCC_CTLA	DUSCC_ADRS(0x0d)	/* counter/timer low      */
#define DUSCC_PCRA	DUSCC_ADRS(0x0e)	/* pin configuration      */
#define DUSCC_CCRA	DUSCC_ADRS(0x0f)	/* channel command reg.   */
#define DUSCC_TXFIFOA	DUSCC_ADRS(0x10)	/* tx FIFO                */
#define DUSCC_RXFIFOA	DUSCC_ADRS(0x14)	/* rx FIFO                */
#define DUSCC_RSRA	DUSCC_ADRS(0x18)	/* rx status reg.         */
#define DUSCC_TRSRA	DUSCC_ADRS(0x19)	/* tx/rx status reg.      */
#define DUSCC_ICTSRA	DUSCC_ADRS(0x1a)	/* counter status reg.    */
#define DUSCC_GSR	DUSCC_ADRS(0x1b)	/* general status         */
#define DUSCC_IERA	DUSCC_ADRS(0x1c)	/* interrupt enable       */
#define DUSCC_IVR	DUSCC_ADRS(0x1e)	/* interrupt vector       */
#define DUSCC_ICR	DUSCC_ADRS(0x1f)	/* interrupt control      */
#define DUSCC_CMR1B	DUSCC_ADRS(0x20)	/* channel mode reg. 1    */
#define DUSCC_CMR2B	DUSCC_ADRS(0x21)	/* channel mode reg. 2    */
#define DUSCC_S1RB	DUSCC_ADRS(0x22)	/* secondary adrs reg 1   */
#define DUSCC_S2RB	DUSCC_ADRS(0x23)	/* secondary adrs reg 2   */
#define DUSCC_TPRB	DUSCC_ADRS(0x24)	/* tx parameter reg.      */
#define DUSCC_TTRB	DUSCC_ADRS(0x25)	/* tx timing reg.         */
#define DUSCC_RPRB	DUSCC_ADRS(0x26)	/* rx parameter reg.      */
#define DUSCC_RTRB	DUSCC_ADRS(0x27)	/* rx timing reg.         */
#define DUSCC_CTPRHB	DUSCC_ADRS(0x28)	/* counter preset high    */
#define DUSCC_CTPRLB	DUSCC_ADRS(0x29)	/* counter preset low     */
#define DUSCC_CTCRB	DUSCC_ADRS(0x2a)	/* counter control reg.   */
#define DUSCC_OMRB	DUSCC_ADRS(0x2b)	/* output/misc. reg.      */
#define DUSCC_CTHB	DUSCC_ADRS(0x2c)	/* counter/timer high     */
#define DUSCC_CTLB	DUSCC_ADRS(0x2d)	/* counter/timer low      */
#define DUSCC_PCRB	DUSCC_ADRS(0x2e)	/* pin configuration      */
#define DUSCC_CCRB	DUSCC_ADRS(0x2f)	/* channel command reg.   */
#define DUSCC_TXFIFOB	DUSCC_ADRS(0x30)	/* tx FIFO                */
#define DUSCC_RXFIFOB	DUSCC_ADRS(0x34)	/* rx FIFO                */
#define DUSCC_RSRB	DUSCC_ADRS(0x38)	/* rx status reg.         */
#define DUSCC_TRSRB	DUSCC_ADRS(0x39)	/* tx/rx status reg.      */
#define DUSCC_ICTSRB	DUSCC_ADRS(0x3a)	/* count/timer status     */
#define DUSCC_IERB	DUSCC_ADRS(0x3c)	/* interrupt enable       */
#define DUSCC_IVRM	DUSCC_ADRS(0x3e)	/* int. vec. modified     */


/* vector number offsets */

#define DUSCC_INT_A_RXRDY		0x00	/* RxRDY interrupt */
#define DUSCC_INT_A_TXRDY		0x01	/* TxRDY interrupt */
#define DUSCC_INT_A_RX_TX_ERROR		0x02	/* rx/tx error interrupt */
#define DUSCC_INT_A_EXT			0x03	/* ext. & cnt/timer interrupt */
#define DUSCC_INT_B_RXRDY		0x04	/* RxRDY interrupt */
#define DUSCC_INT_B_TXRDY		0x05	/* TxRDY interrupt */
#define DUSCC_INT_B_RX_TX_ERROR		0x06	/* rx/tx error interrupt */
#define DUSCC_INT_B_EXT			0x07	/* ext. & cnt/timer interrupt */

#define N_CHANNELS	2	/* number of channels per chip */

/* channel mode register one (CMR1A, CMR1B) */

#define DUSCC_CMR1_BOP_PRIMARY		0x00	/* channel protocol mode */
#define DUSCC_CMR1_BOP_SECONDARY	0x01	/* channel protocol mode */
#define DUSCC_CMR1_BOP_LOOP		0x02	/* channel protocol mode */
#define DUSCC_CMR1_BOP_LOOP_NO_ADR_CMP	0x03	/* channel protocol mode */
#define DUSCC_CMR1_BOP_8BIT_ADRS	0x00	/* single octet address */
#define DUSCC_CMR1_BOP_EXT_ADRS		0x08	/* extended address */
#define DUSCC_CMR1_BOP_16BIT_ADRS	0x10	/* dual octet address */
#define DUSCC_CMR1_BOP_16BIT_GRP_ADRS	0x18	/* dual octet adrs with group */
#define DUSCC_CMR1_BOP_1_OCTET_CNT	0x00	/* 1 ctrl field follows adrs */
#define DUSCC_CMR1_BOP_2_OCTET_CNT	0x20	/* 2 ctrl fields follow adrs */

#define DUSCC_CMR1_COP_DUAL_SYN		0x04	/* channel protocol mode */
#define DUSCC_CMR1_COP_BISYNC		0x05	/* channel protocol mode */
#define DUSCC_CMR1_COP_SINGLE_SYN	0x06	/* channel protocol mode */
#define DUSCC_CMR1_COP_NO_PARITY	0x00	/* channel parity none */
#define DUSCC_CMR1_COP_WITH_PARITY	0x10	/* channel parity odd/even */
#define DUSCC_CMR1_COP_FORCE_PARITY	0x18	/* channel parity hi/lo */
#define DUSCC_CMR1_COP_EVEN_PARITY	0x00	/* channel parity even */
#define DUSCC_CMR1_COP_ODD_PARITY	0x20	/* channel parity odd */
#define DUSCC_CMR1_COP_BISYNC_EBCDIC	0x00	/* comparisons in EBCDIC */
#define DUSCC_CMR1_COP_BISYNC_ASCII	0x20	/* comparisons in ASCII */

#define DUSCC_CMR1_ASYNC		0x07	/* chnl protocol mode: async. */

#define DUSCC_CMR1_NRZ			0x00	/* non-return-to-zero */
#define DUSCC_CMR1_NRZI			0x40	/* non-return-to-zero, inv */
#define DUSCC_CMR1_FM0			0x80	/* bi-phase space */
#define DUSCC_CMR1_FM1			0xc0	/* bi-phase mark */


/* equates for channel mode register two (CMR2A, CMR2B) */

#define DUSCC_CMR2_FCS_SEL_NONE		0x00	/* frame check seq. select */
#define DUSCC_CMR2_FCS_SEL_LRC_8_PRS0	0x02	/* frame check seq. select */
#define DUSCC_CMR2_FCS_SEL_LRC_8_PRS1	0x03	/* frame check seq. select */
#define DUSCC_CMR2_FCS_SEL_CRC_16_PRS0	0x04	/* frame check seq. select */
#define DUSCC_CMR2_FCS_SEL_CRC_16_PRS1	0x05	/* frame check seq. select */
#define DUSCC_CMR2_FCS_SEL_CRC_CC_PRS0	0x06	/* frame check seq. select */
#define DUSCC_CMR2_FCS_SEL_CRC_CC_PRS1	0x07	/* frame check seq. select */

#define DUSCC_CMR2_DTI_HLFDUP_SADRDMA	0x00	/* data transfer interface */
#define DUSCC_CMR2_DTI_HLFDUP_DADRDMA	0x08	/* data transfer interface */
#define DUSCC_CMR2_DTI_FULDUP_SADRDMA	0x10	/* data transfer interface */
#define DUSCC_CMR2_DTI_FULDUP_DADRDMA	0x18	/* data transfer interface */
#define DUSCC_CMR2_DTI_WAIT_RX		0x20	/* data transfer interface */
#define DUSCC_CMR2_DTI_WAIT_TX		0x28	/* data transfer interface */
#define DUSCC_CMR2_DTI_WAIT_RX_TX	0x30	/* data transfer interface */
#define DUSCC_CMR2_DTI_POLL_OR_INT	0x38	/* data transfer interface */

#define DUSCC_CMR2_CHN_CON_NORNAL	0x00	/* channel connection */
#define DUSCC_CMR2_CHN_CON_AUTO_ECHO	0x40	/* channel connection */
#define DUSCC_CMR2_CHN_CON_LOCAL_LOOP	0x80	/* channel connection */


/* equates for transmit parameter register (TPRA, TPRB) */

#define DUSCC_TPR_5BITS			0x00	/* tx 5 bits per character */
#define DUSCC_TPR_6BITS			0x01	/* tx 6 bits per character */
#define DUSCC_TPR_7BITS			0x02	/* tx 7 bits per character */
#define DUSCC_TPR_8BITS			0x03	/* tx 8 bits per character */

#define DUSCC_TPR_CTS_EN_TX_ENABLE	0x04	/* CTS_N affects tx */

#define DUSCC_TPR_TX_RTS_CONT_YES	0x08	/* RTS_N affected by tx */

#define DUSCC_TPR_ASYNC_9_16		0x00	/* async: 9/16 stop bits */
#define DUSCC_TPR_ASYNC_10_16		0x10	/* async: 10/16 stop bits */
#define DUSCC_TPR_ASYNC_11_16		0x20	/* async: 11/16 stop bits */
#define DUSCC_TPR_ASYNC_12_16		0x30	/* async: 12/16 stop bits */
#define DUSCC_TPR_ASYNC_13_16		0x40	/* async: 13/16 stop bits */
#define DUSCC_TPR_ASYNC_14_16		0x50	/* async: 14/16 stop bits */
#define DUSCC_TPR_ASYNC_15_16		0x60	/* async: 15/16 stop bits */
#define DUSCC_TPR_ASYNC_1		0x70	/* async: 16/16 stop bits */
#define DUSCC_TPR_ASYNC_1_9_16		0x80	/* async: 1 stop bit */
#define DUSCC_TPR_ASYNC_1_10_16		0x90	/* async: 10/16 stop bits */
#define DUSCC_TPR_ASYNC_1_11_16		0xa0	/* async: 11/16 stop bits */
#define DUSCC_TPR_ASYNC_1_12_16		0xb0	/* async: 12/16 stop bits */
#define DUSCC_TPR_ASYNC_1_13_16		0xc0	/* async: 13/16 stop bits */
#define DUSCC_TPR_ASYNC_1_14_16		0xd0	/* async: 14/16 stop bits */
#define DUSCC_TPR_ASYNC_1_15_16		0xe0	/* async: 15/16 stop bits */
#define DUSCC_TPR_ASYNC_2		0xf0	/* async: 2 stop bits */

#define DUSCC_TPR_COP_TEOM_NO		0x00	/* no EOM on zero or done */
#define DUSCC_TPR_COP_TEOM_YES		0x10	/* tx EOM on zero or done */
#define DUSCC_TPR_COP_IDLE_MARK		0x00	/* idle in marking condition */
#define DUSCC_TPR_COP_IDLE_SYN		0x20	/* idle sending SYNs */
#define DUSCC_TPR_COP_UNDR_FCS		0x00	/* EOM termination */
#define DUSCC_TPR_COP_UNDR_MARK		0x80	/* TxD in marking condition */
#define DUSCC_TPR_COP_UNDR_SYN		0xc0	/* send SYNs */

#define DUSCC_TPR_BOP_TEOM_NO		0x00	/* no EOM on zero or done */
#define DUSCC_TPR_BOP_TEOM_YES		0x10	/* tx EOM on zero or done */
#define DUSCC_TPR_BOP_IDLE_MARK		0x00	/* idle in marking condition */
#define DUSCC_TPR_BOP_IDLE_SYN		0x20	/* idle sending FLAGs */
#define DUSCC_TPR_BOP_UNDR_FCS		0x00	/* EOM termination */
#define DUSCC_TPR_BOP_UNDR_ABORT_MARK	0x80	/* TxD in marking condition */
#define DUSCC_TPR_BOP_UNDR_ABORT_FLAG	0xc0	/* send ABORTs */


/* equates for transmitter timing register (TTRA, TTRB) */

#define DUSCC_TTR_BAUD_50		0x00	/* transmit speed */
#define DUSCC_TTR_BAUD_75		0x01	/* transmit speed */
#define DUSCC_TTR_BAUD_110		0x02	/* transmit speed */
#define DUSCC_TTR_BAUD_134_5		0x03	/* transmit speed */
#define DUSCC_TTR_BAUD_150		0x04	/* transmit speed */
#define DUSCC_TTR_BAUD_200		0x05	/* transmit speed */
#define DUSCC_TTR_BAUD_300		0x06	/* transmit speed */
#define DUSCC_TTR_BAUD_600		0x07	/* transmit speed */
#define DUSCC_TTR_BAUD_1050		0x08	/* transmit speed */
#define DUSCC_TTR_BAUD_1200		0x09	/* transmit speed */
#define DUSCC_TTR_BAUD_2000		0x0a	/* transmit speed */
#define DUSCC_TTR_BAUD_2400		0x0b	/* transmit speed */
#define DUSCC_TTR_BAUD_4800		0x0c	/* transmit speed */
#define DUSCC_TTR_BAUD_9600		0x0d	/* transmit speed */
#define DUSCC_TTR_BAUD_19200		0x0e	/* transmit speed */
#define DUSCC_TTR_BAUD_38400		0x0f	/* transmit speed */

#define DUSCC_TTR_CLK_1x_EXT		0x00	/* ext. clock, 1x baud rate */
#define DUSCC_TTR_CLK_16x_EXT		0x10	/* ext. clock, 16x, async */
#define DUSCC_TTR_CLK_DPLL		0x20	/* int., DPLL, half duplex */
#define DUSCC_TTR_CLK_BRG		0x30	/* int., BRG, 32x, baud rate */
#define DUSCC_TTR_CLK_2x_OTHER_CHAN	0x40	/* int., C/T, 2x baud rate */
#define DUSCC_TTR_CLK_32x_OTHER_CHAN	0x50	/* int., C/T, 32x baud rate */
#define DUSCC_TTR_CLK_2x_OWN_CHAN	0x60	/* int., C/T, 2x baud rate */
#define DUSCC_TTR_CLK_32x_OWN_CHAN	0x70	/* int., C/T, 32x baud rate */

#define DUSCC_TTR_EXT_SOURCE_RTXC	0x00	/* ext. input from RTxC */
#define DUSCC_TTR_EXT_SOURCE_TRXC	0x80	/* ext. input from TRxC */

/* equates for receiver parameter register (RPRA, RPRB) */

#define DUSCC_RPR_5BITS			0x00	/* rx 5 bits per character */
#define DUSCC_RPR_6BITS			0x01	/* rx 6 bits per character */
#define DUSCC_RPR_7BITS			0x02	/* rx 7 bits per character */
#define DUSCC_RPR_8BITS			0x03	/* rx 8 bits per character */

#define DUSCC_RPR_DCD_EN_RX_DISABLE	0x00	/* not used to enable rx */
#define DUSCC_RPR_DCD_EN_RX_ENABLE	0x04	/* used to enable receiver */

#define DUSCC_RPR_ASYNC_STRIP_PARITY_NO	0x00	/* do not strip RX parity */
#define DUSCC_RPR_ASYNC_STRIP_PARITY_YES 0x08	/* strip RX parity */
#define DUSCC_RPR_ASYNC_RX_RTS_CONT_NO	0x00	/* rx can't negate RTS_N */
#define DUSCC_RPR_ASYNC_RX_RTS_CONT_YES	0x10	/* async: rx can negate RTS_N */

#define DUSCC_RPR_COP_STRIP_PARITY_NO	0x00	/* don't strip RX parity */
#define DUSCC_RPR_COP_STRIP_PARITY_YES	0x08	/* strip RX parity */
#define DUSCC_RPR_COP_EXT_SYNC_NO	0x00	/* external SYNC disable */
#define DUSCC_RPR_COP_EXT_SYNC_YES	0x10	/* external SYNC enable */
#define DUSCC_RPR_COP_AUTO_HUNT_NO	0x00	/* disable auto-hunt/PAD check*/
#define DUSCC_RPR_COP_AUTO_HUNT_YES	0x20	/* enable auto-hunt/PAD check */
#define DUSCC_RPR_COP_FCS_FIFO_NO	0x00	/* don't trans to RxFIFO */
#define DUSCC_RPR_COP_FCS_FIFO_YES	0x40	/* trans. FCS to RxFIFO */
#define DUSCC_RPR_COP_SYN_STRIP_LEADING	0x00	/* strip leading SYNs */
#define DUSCC_RPR_COP_SYN_STRIP_ALL	0x80	/* strip all SYNs */

#define DUSCC_RPR_BOP_ALL_PARITY_ADR_NO	0x00	/* BOP: don't recognize all */
#define DUSCC_RPR_BOP_ALL_PARITY_ADR_YES 0x08	/* BOP: recognize all parties */
#define DUSCC_RPR_BOP_OVRUN_HUNT	0x00	/* BOP: hunt for FLAG on over */