m68302.h

IXP425的BSP代码

/* m68302.h - Motorola MC68302 CPU control registers */

/* Copyright 1984-1996, Wind River Systems, Inc. */

/*
modification history
--------------------
01i,16dec96,dat  fixed some hdlc values, SPR 2260
01h,31may96,dat  correct use of volatile type for SCC_BUFF & SCC_REG
01g,10may96,dat  added IMP_SCCX_PARAM and IMP_SCCX_PROT for m68302Sio.
01f,22sep92,rrr  added support for c++
01e,10aug92,caf  added TY_CO_DEV and function declarations for 5.1 upgrade.
		 for 5.0.x compatibility, define INCLUDE_TY_CO_DRV_50 when
		 including this header.
01d,26may92,rrr  the tree shuffle
01c,04oct91,rrr  passed through the ansification filter
		  -fixed #else and #endif
		  -changed ASMLANGUAGE to _ASMLANGUAGE
		  -changed copyright notice
01b,30sep91,caf  added _ASMLANGUAGE conditional.
01a,19sep91,jcf  written.
*/

/*
This file contains I/O address and related constants for the MC68302.
*/

#ifndef __INCm68302h
#define __INCm68302h

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#ifndef	INCLUDE_TY_CO_DRV_50
#include "tyLib.h"
#endif	/* INCLUDE_TY_CO_DRV_50 */

/* System Configuration Registers */

#define IMP_BAR	((UINT16 *)0xf2)	/* Base Address Register */
#define IMP_SCR	((UINT32 *)0xf4)	/* System Control Register */

/* MC68302 parameter register addresses */

#define IMP_SCC1	((SCC *)    (IMP_BASE_ADRS + 0x400))
#define IMP_SCC1_PARAM	((SCC_PARAM *)(IMP_BASE_ADRS + 0x480))
#define IMP_SCC1_PROT	((PROT_UART *) (IMP_BASE_ADRS + 0x49c))
#define IMP_SCC2	((SCC *)    (IMP_BASE_ADRS + 0x500))
#define IMP_SCC2_PARAM	((SCC_PARAM *)(IMP_BASE_ADRS + 0x580))
#define IMP_SCC2_PROT	((PROT_UART *) (IMP_BASE_ADRS + 0x59c))
#define IMP_SCC3	((SCC3 *)   (IMP_BASE_ADRS + 0x600))
#define IMP_SCC3_PARAM	((SCC_PARAM *)(IMP_BASE_ADRS + 0x680))
#define IMP_SCC3_PROT	((PROT_UART *) (IMP_BASE_ADRS + 0x69c))
#define	IMP_CMR		((UINT16 *) (IMP_BASE_ADRS + 0x802))
#define	IMP_SAPR	((UINT32 *) (IMP_BASE_ADRS + 0x804))
#define	IMP_DAPR	((UINT32 *) (IMP_BASE_ADRS + 0x808))
#define	IMP_BCR		((UINT16 *) (IMP_BASE_ADRS + 0x80c))
#define	IMP_CSR		((UINT8 *)  (IMP_BASE_ADRS + 0x80e))
#define	IMP_FCR		((UINT8 *)  (IMP_BASE_ADRS + 0x810))
#define	IMP_GIMR	((UINT16 *) (IMP_BASE_ADRS + 0x812))
#define	IMP_IPR		((UINT16 *) (IMP_BASE_ADRS + 0x814))
#define	IMP_IMR		((UINT16 *) (IMP_BASE_ADRS + 0x816))
#define	IMP_ISR		((UINT16 *) (IMP_BASE_ADRS + 0x818))
#define IMP_PACNT	((UINT16 *) (IMP_BASE_ADRS + 0x81e))
#define IMP_PADDR	((UINT16 *) (IMP_BASE_ADRS + 0x820))
#define IMP_PADAT	((UINT16 *) (IMP_BASE_ADRS + 0x822))
#define IMP_PBCNT	((UINT16 *) (IMP_BASE_ADRS + 0x824))
#define IMP_PBDDR	((UINT16 *) (IMP_BASE_ADRS + 0x826))
#define IMP_PBDAT	((UINT16 *) (IMP_BASE_ADRS + 0x828))
#define IMP_BR0		((UINT16 *) (IMP_BASE_ADRS + 0x830))
#define IMP_OR0		((UINT16 *) (IMP_BASE_ADRS + 0x832))
#define IMP_BR1		((UINT16 *) (IMP_BASE_ADRS + 0x834))
#define IMP_OR1		((UINT16 *) (IMP_BASE_ADRS + 0x836))
#define IMP_BR2		((UINT16 *) (IMP_BASE_ADRS + 0x838))
#define IMP_OR2		((UINT16 *) (IMP_BASE_ADRS + 0x83a))
#define IMP_BR3		((UINT16 *) (IMP_BASE_ADRS + 0x83c))
#define IMP_OR3		((UINT16 *) (IMP_BASE_ADRS + 0x83e))
#define IMP_TMR1	((UINT16 *) (IMP_BASE_ADRS + 0x840))
#define IMP_TRR1	((UINT16 *) (IMP_BASE_ADRS + 0x842))
#define IMP_TCR1	((UINT16 *) (IMP_BASE_ADRS + 0x844))
#define IMP_TCN1	((UINT16 *) (IMP_BASE_ADRS + 0x846))
#define IMP_TER1	((UINT8 *)  (IMP_BASE_ADRS + 0x849))
#define IMP_WRR		((UINT16 *) (IMP_BASE_ADRS + 0x84a))
#define IMP_WCN		((UINT16 *) (IMP_BASE_ADRS + 0x84c))
#define IMP_TMR2	((UINT16 *) (IMP_BASE_ADRS + 0x850))
#define IMP_TRR2	((UINT16 *) (IMP_BASE_ADRS + 0x852))
#define IMP_TCR2	((UINT16 *) (IMP_BASE_ADRS + 0x854))
#define IMP_TCN2	((UINT16 *) (IMP_BASE_ADRS + 0x856))
#define IMP_TER2	((UINT8 *)  (IMP_BASE_ADRS + 0x859))
#define IMP_CR		((UINT8 *)  (IMP_BASE_ADRS + 0x860))
#define IMP_SCC1_REG	((SCC_REG *)(IMP_BASE_ADRS + 0x880))
#define IMP_SCC2_REG	((SCC_REG *)(IMP_BASE_ADRS + 0x890))
#define IMP_SCC3_REG	((SCC_REG *)(IMP_BASE_ADRS + 0x8a0))
#define IMP_SPMODE	((UINT16 *) (IMP_BASE_ADRS + 0x8b0))
#define IMP_SIMASK	((UINT16 *) (IMP_BASE_ADRS + 0x8b2))
#define IMP_SIMODE	((UINT16 *) (IMP_BASE_ADRS + 0x8b4))


/* Internal Register Defines */

/* CR - Command Registers */

#define CR_FLG		0x01		/* CP/IMP spinlock flag */
#define CR_GCI		0x40		/* GCI command */
#define CR_GCI_TAR	0x00		/* GCI - Transmit abort request */
#define CR_GCI_TOUT	0x10		/* GCI - Timeout */
#define CR_RST		0x80		/* software reset command */

/* GIMR - Global Interrupt Mode Registers */

#define GIMR_VEC_MASK 	0x00e0		/* vector bits 7 - 5 */
#define GIMR_EDGE1 	0x0100		/* IRQ1 edge triggered (else level) */
#define GIMR_EDGE6 	0x0200		/* IRQ6 edge triggered (else level) */
#define GIMR_EDGE7 	0x0400		/* IRQ7 edge triggered (else level) */
#define GIMR_EXT_VEC1 	0x1000		/* level 1 vector external */
#define GIMR_EXT_VEC6 	0x2000		/* level 6 vector external */
#define GIMR_EXT_VEC7 	0x4000		/* level 7 vector external */
#define GIMR_DISCRETE 	0x8000		/* IPL0-IPL2 are IRQ1/IRQ6/IRQ7 */

/* IPR/IMR/ISR - Interrupt Pending/Mask/In-Service Registers */

#define INT_ERR		0x0001		/* response to ext. level 4 */
#define INT_PB8		0x0002		/* parrallel port B (bit 8) */
#define INT_SMC2 	0x0004		/* serial management controller 2 */
#define INT_SMC1 	0x0008		/* serial management controller 1 */
#define INT_TMR3 	0x0010		/* timer 3 */
#define INT_SCP 	0x0020		/* serial comunication port */
#define INT_TMR2 	0x0040		/* timer 2 */
#define INT_PB9 	0x0080		/* parrallel port B (bit 9) */
#define INT_SCC3 	0x0100		/* serial comunication controller 3 */
#define INT_TMR1 	0x0200		/* timer 1 */
#define INT_SCC2 	0x0400		/* serial comunication controller 2 */
#define INT_IDMA 	0x0800		/* independent direct memory access */
#define INT_SDMA 	0x1000		/* serial direct memory access */
#define INT_SCC1 	0x2000		/* serial comunication controller 1 */
#define INT_PB10 	0x4000		/* parrallel port B (bit 10) */
#define INT_PB11 	0x8000		/* parrallel port B (bit 11) */

/* Interrupt Vectors */

#define INT_VEC_ERR	(0x0 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_PB8	(0x1 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_SMC2	(0x2 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_SMC1	(0x3 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_TMR3	(0x4 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_SCP	(0x5 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_TMR2	(0x6 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_PB9	(0x7 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_SCC3	(0x8 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_TMR1	(0x9 | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_SCC2	(0xa | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_IDMA	(0xb | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_SDMA	(0xc | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_SCC1	(0xd | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_PB10	(0xe | (*IMP_GIMR & GIMR_VEC_MASK))
#define INT_VEC_PB11	(0xf | (*IMP_GIMR & GIMR_VEC_MASK))

/* TMR1/TMR2 - Timer Mode Register */

#define TMR_ENABLE 	0x0001		/* enable timer */
#define TMR_STOP	0x0000		/* stop count */
#define TMR_CLK		0x0002		/* count source is master clock */
#define TMR_CLK16	0x0004		/* count source is master clock/16 */
#define TMR_CLK_EXT	0x0006		/* count source is falling edge TIN */
#define TMR_RESTART	0x0008		/* count is restarted upon ref cnt */
#define TMR_INT		0x0010		/* enable interrupt upon ref cnt */
#define TMR_TOGGLE	0x0020		/* toggle output */
#define TMR_CAP_DIS	0x0000		/* disable interrupt on capture event */
#define TMR_CAP_RISE	0x0040		/* enable int w/ capture rising edge */
#define TMR_CAP_FALL	0x0080		/* enable int w/ capture falling edge */
#define TMR_CAP_ANY	0x00c0		/* enable int w/ capture any edge */

/* TER1/TER2 - Timer Event Register */

#define TER_CAPTURE 	0x01		/* counter value has been captured */
#define TER_REF_CNT	0x02		/* counter value reached ref. cnt */

/* CS_BR - Chip Select Base Register */

#define CS_BR_ENABLE	0x0001		/* chip select pin is enabled */
#define CS_BR_WRITE	0x0002		/* chip select pin write only */

/* CS_OR - Chip Select Options Register */

#define CS_OR_CFC	0x0001		/* function code of CS_BR compared */
#define CS_OR_UNMASK_RW	0x0002		/* r/w bit of CS_BR is not masked */

/* SCR - System Control Register */

#define SCR_LPEN 	0x00000020	/* low power mode enabled */
#define SCR_LPP16 	0x00000040	/* low power clock/16 prescale enable */
#define SCR_LPREC 	0x00000080	/* destructive low power recovery */
#define SCR_HWDEN 	0x00000800	/* hardware watchdog enable */
#define SCR_SAM 	0x00001000	/* synchronous access mode */
#define SCR_FRZ1 	0x00002000	/* freeze timer 1 */
#define SCR_FRZ2 	0x00004000	/* freeze timer 2 */
#define SCR_FRZW 	0x00008000	/* freeze watchdog timer */
#define SCR_BCLM 	0x00010000	/* BCLR derived from IPEND */
#define SCR_ADCE 	0x00020000	/* BERR on address decode conflict */
#define SCR_EMWS 	0x00040000	/* external master wait state */
#define SCR_RMCST 	0x00080000	/* RMC cycle special treatment */
#define SCR_WPVE 	0x00100000	/* BERR on write protect violation */
#define SCR_VGE 	0x00200000	/* vector generation enable (discpu) */
#define SCR_ERRE 	0x00400000	/* external RISC request enable */
#define SCR_ADC 	0x01000000	/* address decode conflict */
#define SCR_WPV 	0x02000000	/* write protect violation */
#define SCR_HWT 	0x04000000	/* hardware watchdog timeout */
#define SCR_IPA 	0x08000000	/* interrupt priority active */

/* SCC - Serial Comunications Controller */

typedef volatile struct		/* SCC_BUF */
    {
    UINT16	statusMode;	/* status/mode protocal specific */
    UINT16	dataLength;		/* length of buffer in bytes */
    char *	dataPointer;		/* points to data buffer */
    } SCC_BUF;

typedef struct		/* SCC_PARAM */
    {
    UINT8	rfcr;			/* receive function code */
    UINT8	tfcr;			/* transmit function code */
    UINT16	mrblr;			/* maximum receive buffer length */
    UINT16	res1;			/* reserved/internal */
    UINT8	res2;			/* reserved/internal */
    UINT8	rbd;			/* receive internal buffer number */
    UINT16	res3[5];		/* reserved/internal */
    UINT8	res4;			/* reserved/internal */
    UINT8	tbd;			/* transmit internal buffer number */
    UINT16	res5[4];		/* reserved/internal */
    } SCC_PARAM;

typedef struct		/* SCC */
    {
    SCC_BUF	rxBd[8];		/* receive buffer descriptors */
    SCC_BUF	txBd[8];		/* transmit buffer descriptors */
    SCC_PARAM	param;			/* SCC parameters */
    char	prot[64];		/* protocol specific area */
    } SCC;

typedef struct		/* SCC3 */
    {
    SCC_BUF	rxBd[8];		/* receive buffer descriptors */
    SCC_BUF	txBd[4];		/* transmit buffer descriptors */
    UINT16	res1[3];		/* reserved/internal */
    UINT16	smc1RxBd;		/* SMC1 receive buffer descriptor */
    UINT16	smc1TxBd;		/* SMC1 transmit buffer descriptor */
    UINT16	smc2RxBd;		/* SMC2 receive buffer descriptor */
    UINT16	smc2TxBd;		/* SMC2 transmit buffer descriptor */
    UINT16	res2[6];		/* reserved/internal */
    UINT16	scpBd;			/* SCP buffer descriptor */
    UINT16	sccBerr;		/* SCC channel bus error status */
    UINT16	rev;			/* MC68302 revision number */
    SCC_PARAM	param;			/* SCC parameters */
    char	prot[64];		/* protocol specific area */
    } SCC3;

typedef volatile struct		/* SCC_REG */
    {
    UINT16	res1;			/* reserved/internal */
    UINT16	scon;			/* configuration register */
    UINT16	scm;			/* mode register */
    UINT16	dsr;			/* data sync. register */
    UINT8	scce;			/* event register */
    UINT8	res2;			/* reserved/internal */
    UINT8	sccm;			/* mask register */
    UINT8	res3;			/* reserved/internal */
    UINT8	sccs;			/* status register */
    UINT8	res4;			/* reserved/internal */
    UINT16	res5;			/* reserved/internal */
    } SCC_REG;

/* SCC Configuration Register */

#define SCON_DIV4		0x0001	/* SCC clock prescaler divide by 4 */
#define SCON_EXT_RX_CLK		0x1000	/* RCLK pin is rx baud rate source */
#define SCON_EXT_TX_CLK		0x2000	/* RCLK pin is tx baud rate source */
#define SCON_EXT_BAUD		0x4000	/* TIN1 pin is baud rate clk source */
#define SCON_WIRED_OR		0x8000	/* TXD pin is placed in open drain */

/* UART Protocol - SCC protocol specific parameters */

typedef volatile struct		/* PROT_UART */
    {
    UINT16	maxIdl;			/* maximum idle characters */
    UINT16	idlc;			/* temporary receive idle counter */
    UINT16	brkcr;			/* break count register */
    UINT16	parec;			/* receive parity error counter */
    UINT16	frmec;			/* receive framing error counter */
    UINT16	nosec;			/* receive noise counter */
    UINT16	brkec;			/* receive break character counter */
    UINT16	uaddr1;			/* uart address character 1 */
    UINT16	uaddr2;			/* uart address character 2 */
    UINT16	rccr;			/* receive control character register */
    UINT16	cntChar1;		/* control character 1 */
    UINT16	cntChar2;		/* control character 2 */
    UINT16	cntChar3;		/* control character 3 */
    UINT16	cntChar4;		/* control character 4 */
    UINT16	cntChar5;		/* control character 5 */
    UINT16	cntChar6;		/* control character 6 */
    UINT16	cntChar7;		/* control character 7 */
    UINT16	cntChar8;		/* control character 8 */
    } PROT_UART;

/* UART Protocol - SCC Mode Register */

#define UART_SCM_HDLC		0x0000	/* hdlc mode */
#define UART_SCM_ASYNC		0x0001	/* asynchronous mode (uart/ddcmp) */
#define UART_SCM_SYNC		0x0002	/* synchronous mode (ddcmp/v.110) */
#define UART_SCM_BISYNC		0x0003	/* bisync/promiscuous mode */
#define UART_SCM_ENT		0x0004	/* enable transmitter */
#define UART_SCM_ENR		0x0008	/* enable receiver */
#define UART_SCM_LOOPBACK	0x0010	/* transmitter hooked to receiver */
#define UART_SCM_ECHO		0x0020	/* transmitter echoes received chars */
#define UART_SCM_MANUAL		0x0030	/* cts/cd under software control */
#define UART_SCM_STOP_2		0x0040	/* two stop bits (one otherwise) */
#define UART_SCM_RTSM		0x0080	/* 0:rts w/ tx char; 1:rts w/ tx enbl */
#define UART_SCM_8BIT		0x0100	/* 8 bit char. length (7 otherwise) */
#define UART_SCM_FRZ_TX		0x0200	/* freeze transmitter */
#define UART_SCM_DROP1		0x0400	/* multidrop w/o adrs. recognition */
#define UART_SCM_DDCMP		0x0800	/* ddcmp protocol selected */
#define UART_SCM_DROP2		0x0c00	/* multidrop w adrs. recognition */
#define UART_SCM_PARITY		0x1000	/* parity is enabled */
#define UART_SCM_RX_EVEN	0x2000	/* rx even parity */
#define UART_SCM_TX_ODD		0x0000	/* tx odd parity */
#define UART_SCM_TX_SPACE	0x4000	/* tx space parity */
#define UART_SCM_TX_EVEN	0x8000	/* tx even parity */
#define UART_SCM_TX_MARK	0xc000	/* tx mark parity */

/* UART Protocol - SCC Event Register */

#define UART_SCCE_RX 		0x01	/* buffer received */
#define UART_SCCE_TX 		0x02	/* buffer transmitted */
#define UART_SCCE_BSY 		0x04	/* character discarded, no buffers */
#define UART_SCCE_CCR 		0x08	/* control character received */