m5272.h

IXP425的BSP代码

#define M5272_DMA_DMR_EN	(1 << 30)	/* enable */ 
#define M5272_DMA_DMR_RQM	(3 << 18)	/* request mode */ 
#define M5272_DMA_DMR_DSTM	(3 << 13)	/* dest. addressing mode */ 
#define M5272_DMA_DMR_DSTT	(7 << 10)	/* dest. addressing type */ 
#define M5272_DMA_DMR_DSTS	(3 << 8)	/* dest. data transfer type */ 
#define M5272_DMA_DMR_SRCM	(1 << 5)	/* source addressing mode */ 
#define M5272_DMA_DMR_SRCT	(7 << 2)	/* source addressing type */ 
#define M5272_DMA_DMR_SRCS	(3 << 0)	/* source data transfer type */ 

#define M5272_DMA_DIR_INVEN	(1 << 12)	/* inval. combin. interrupt */ 
#define M5272_DMA_DIR_ASCEN	(1 << 11)	/* addr. seq. compl. interr. */ 
#define M5272_DMA_DIR_TEEN	(1 << 9)	/* Transfer error interrupt */ 
#define M5272_DMA_DIR_TCEN	(1 << 8)	/* Transfer compl. interrupt */ 
#define M5272_DMA_DIR_INV	(1 << 4)	/* invalid combination */ 
#define M5272_DMA_DIR_ASC	(1 << 3)	/* addr. sequence complete */ 
#define M5272_DMA_DIR_TE	(1 << 1)	/* transfer error */ 
#define M5272_DMA_DIR_TC	(1 << 0)	/* transfer complete */ 

/* UART 0 & 1 */
#define M5272_UART_REG(base, offset, chan)	\
		((base) + (offset) + ((chan) * 0x40))
#define M5272_UART_UMR1(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x100, n))
#define M5272_UART_UMR2(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x100, n))
#define M5272_UART_USR(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x104, n))
#define M5272_UART_UCSR(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x104, n))
#define M5272_UART_UCR(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x108, n))
#define M5272_UART_URB(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x10c, n))
#define M5272_UART_UTB(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x10c, n))
#define M5272_UART_UIPCR(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x110, n))
#define M5272_UART_UACR(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x110, n))
#define M5272_UART_UISR(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x114, n))
#define M5272_UART_UIMR(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x114, n))
#define M5272_UART_UDU(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x118, n))
#define M5272_UART_UDL(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x11c, n))
#define M5272_UART_UABU(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x120, n))
#define M5272_UART_UABL(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x124, n))
#define M5272_UART_UTF(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x128, n))
#define M5272_UART_URF(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x12c, n))
#define M5272_UART_UFPD(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x130, n))
#define M5272_UART_UIP(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x134, n))
#define M5272_UART_UOP1(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x138, n))
#define M5272_UART_UOP0(base, n)	\
		(CAST_M5272(volatile UINT8 *) M5272_UART_REG((base), 0x13c, n))

#define M5272_UART_UMR1_RxRTS	(1 << 7)	/* receiver request-to-send */ 
#define M5272_UART_UMR1_RxIRQ_FFULL	(1 << 6)	/* rec. interr. sel. */ 
#define M5272_UART_UMR1_ERR	(1 << 5)	/* error mode-to-send */ 
#define M5272_UART_UMR1_PM	(3 << 3)	/* parity mode */ 
#define M5272_UART_UMR1_PT	(1 << 2)	/* parity type */ 
#define M5272_UART_UMR1_B_C	(3 << 0)	/* bits per character */ 

#define M5272_UART_UMR2_CM	(3 << 6)	/* channel mode */ 
#define M5272_UART_UMR2_TxRTS	(1 << 5)	/* transmitter ready-to-send */ 
#define M5272_UART_UMR2_TxCTS	(1 << 4)	/* transmitter clear-to-send */ 
#define M5272_UART_UMR2_SB	(0xf << 0)	/* stop-bit length control */ 

#define M5272_UART_USR_RB	(1 << 7)	/* received break */ 
#define M5272_UART_USR_FE	(1 << 6)	/* framing error */ 
#define M5272_UART_USR_PE	(1 << 5)	/* parity error */ 
#define M5272_UART_USR_OE	(1 << 4)	/* overrun error */ 
#define M5272_UART_USR_TxEMP	(1 << 3)	/* transmitter empty */ 
#define M5272_UART_USR_TxRDY	(1 << 2)	/* transmitter ready */ 
#define M5272_UART_USR_FFULL	(1 << 1)	/* FIFO full */ 
#define M5272_UART_USR_RxRDY	(1 << 0)	/* receiver ready */ 

#define M5272_UART_UCSR_RCS	(0xf << 4)	/* receiver clock select */ 
#define M5272_UART_UCSR_TCS	(0xf << 0)	/* transmitter clock select */ 

#define M5272_UART_UCR_ENAB	(1 << 7)	/* enable autobaud */ 
#define M5272_UART_UCR_MISC	(7 << 4)	/* misc field */ 
#define M5272_UART_UCR_TC	(3 << 2)	/* TC field */ 
#define M5272_UART_UCR_RC	(3 << 0)	/* RC field */ 

#define M5272_UART_UIPCR_COS	(1 << 4)	/* change of state */ 
#define M5272_UART_UIPCR_CTS	(1 << 0)	/* current state */ 

#define M5272_UART_UACR_RTSL	(3 << 1)	/* /RTS level */ 
#define M5272_UART_UACR_IEC	(1 << 0)	/* input enable control */ 

#define M5272_UART_UISR_UIMR_COS	(1 << 7)	/* change of state */ 
#define M5272_UART_UISR_UIMR_ABC	(1 << 6)	/* autobaud calc. */ 
#define M5272_UART_UISR_UIMR_RxFIFO	(1 << 5)	/* rec. FIFO status */ 
#define M5272_UART_UISR_UIMR_TxFIFO	(1 << 4)	/* trans. FIFO status */ 
#define M5272_UART_UISR_UIMR_RxFTO	(1 << 3)	/* rec. FIFO timeout */ 
#define M5272_UART_UISR_UIMR_DB		(1 << 2)	/* delta break */ 
#define M5272_UART_UISR_UIMR_FFULL_RxRDY	(1 << 1)	/* FFULL/RxRDY*/ 
#define M5272_UART_UISR_UIMR_TxRDY	(1 << 0)	/* transmitter ready */ 

#define M5272_UART_UTF_TXS	(3 << 6)	/* transmitter status */ 
#define M5272_UART_UTF_FULL	(1 << 5)	/* transmitter FIFO full */ 
#define M5272_UART_UTF_TXB	(0x1f << 0)	/* transmitter buf data level */ 

#define M5272_UART_URF_RXS	(3 << 6)	/* receiver status */ 
#define M5272_UART_URF_FULL	(1 << 5)	/* receiver FIFO full */ 
#define M5272_UART_URF_RXB	(0x1f << 0)	/* receiver buf data level */ 

/* SDRAM Controller Memory Map */
#define M5272_SDRAM_SDCR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x180))
#define M5272_SDRAM_SDTR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x184))

/* SDCR - SDRAM Configuration register */
#define M5272_SDRAM_SDCR_MCAS	(3 << 13)	/* Maximum CAS address */
#define M5272_SDRAM_SDCR_MCAS_A7	(0 << 13)
#define M5272_SDRAM_SDCR_MCAS_A8	(1 << 13)
#define M5272_SDRAM_SDCR_MCAS_A9	(2 << 13)
#define M5272_SDRAM_SDCR_MCAS_A10	(3 << 13)
#define M5272_SDRAM_SDCR_BALOC	(7 << 8)	/* Bank address location */
#define M5272_SDRAM_SDCR_BALOC_A20	(1 << 8) /* SDBA0 = A20, SDBA1 = A21 */
#define M5272_SDRAM_SDCR_BALOC_A21	(2 << 8) /* SDBA0 = A21, SDBA1 = A22 */
#define M5272_SDRAM_SDCR_BALOC_A22	(3 << 8) /* SDBA0 = A22, SDBA1 = A23 */
#define M5272_SDRAM_SDCR_BALOC_A23	(4 << 8) /* SDBA0 = A23, SDBA1 = A24 */
#define M5272_SDRAM_SDCR_BALOC_A24	(5 << 8) /* SDBA0 = A24, SDBA1 = A25 */
#define M5272_SDRAM_SDCR_GSL	(1 << 7)	/* Go to sleep */
#define M5272_SDRAM_SDCR_REG	(1 << 4)	/* Register read data */
#define M5272_SDRAM_SDCR_INV	(1 << 3)	/* Invert clock */
#define M5272_SDRAM_SDCR_SLEEP	(1 << 2)	/* Sleep mode */
#define M5272_SDRAM_SDCR_ACT	(1 << 1)	/* Active */
#define M5272_SDRAM_SDCR_INIT	(1 << 0)	/* Initialisation enable */

/* SDTR - SDRAM Timing Register */
#define M5272_SDRAM_SDTR_RTP	0xfc00		/* Refresh timing prescalar */
#define M5272_SDRAM_SDTR_RTP_66	(61 << 10)	/* 66MHz */
#define M5272_SDRAM_SDTR_RTP_48	(43 << 10)	/* 48MHz */
#define M5272_SDRAM_SDTR_RTP_33	(29 << 10)	/* 33MHz */
#define M5272_SDRAM_SDTR_RTP_25	(22 << 10)	/* 25MHz */
#define M5272_SDRAM_SDTR_RTP_5	(4 << 10)	/* 5MHz (emulator) */
#define M5272_SDRAM_SDTR_RC	(3 << 8)	/* Refresh count */
#define M5272_SDRAM_SDTR_RC_5	(0 << 8)	/* 5 cycles */
#define M5272_SDRAM_SDTR_RC_6	(1 << 8)	/* 6 cycles */
#define M5272_SDRAM_SDTR_RC_7	(2 << 8)	/* 7 cycles */
#define M5272_SDRAM_SDTR_RC_8	(3 << 8)	/* 8 cycles */
#define M5272_SDRAM_SDTR_RP	(3 << 4)	/* Precharge time */
#define M5272_SDRAM_SDTR_RP_1	(0 << 4)	/* 1 cycles */
#define M5272_SDRAM_SDTR_RP_2	(1 << 4)	/* 2 cycles */
#define M5272_SDRAM_SDTR_RP_3	(2 << 4)	/* 3 cycles */
#define M5272_SDRAM_SDTR_RP_4	(3 << 4)	/* 4 cycles */
#define M5272_SDRAM_SDTR_RCD	(3 << 2)	/* RAS-CAS delay */
#define M5272_SDRAM_SDTR_RCD_1	(0 << 2)	/* 1 cycles */
#define M5272_SDRAM_SDTR_RCD_2	(1 << 2)	/* 2 cycles */
#define M5272_SDRAM_SDTR_RCD_3	(2 << 2)	/* 3 cycles */
#define M5272_SDRAM_SDTR_RCD_4	(3 << 2)	/* 4 cycles */
#define M5272_SDRAM_SDTR_CLT	(3 << 0)	/* CAS latency */
#define M5272_SDRAM_SDTR_CLT_2	(1 << 0)	/* 2 cycles */

/* Timers 0 and 1 */
#define M5272_TIMER_REG(base, offset, timer)	\
			((base) + ((timer) * 0x20) + (offset))
#define M5272_TIMER_TMR(base, n)	\
		(CAST_M5272(volatile UINT16 *) M5272_TIMER_REG(base, 0x200, n))
#define M5272_TIMER_TRR(base, n)	\
		(CAST_M5272(volatile UINT16 *) M5272_TIMER_REG(base, 0x204, n))
#define M5272_TIMER_TCR(base, n)	\
		(CAST_M5272(volatile UINT16 *) M5272_TIMER_REG(base, 0x208, n))
#define M5272_TIMER_TCN(base, n)	\
		(CAST_M5272(volatile UINT16 *) M5272_TIMER_REG(base, 0x20c, n))
#define M5272_TIMER_TER(base, n)	\
		(CAST_M5272(volatile UINT16 *) M5272_TIMER_REG(base, 0x210, n))

#define M5272_TIMER_TMR_PRESCALER	(0xffff << 8)	/* prescaler */ 
#define M5272_TIMER_TMR_CE	(3 << 6)	/* capture edge */ 
#define M5272_TIMER_TMR_OM	(1 << 5)	/* output mode */ 
#define M5272_TIMER_TMR_ORI	(1 << 4)	/* output reference */ 
#define M5272_TIMER_TMR_FRR	(1 << 3)	/* free run/restart */ 
#define M5272_TIMER_TMR_CLK	(3 << 1)	/* input clock source */ 
#define M5272_TIMER_TMR_RST	(1 << 0)	/* reset timer */ 

#define M5272_TIMER_TER_REF	(1 << 1)	/* output reference event */ 
#define M5272_TIMER_TER_CAP	(1 << 0)	/* capture event */ 

/* PLIC Module Memory Map */
#define M5272_PLIC_BASE(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x300))

/* Ethernet Module Memory Map */
#define M5272_FEC_BASE(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x840))

/* USB Module Memory Map */
#define M5272_USB_BASE(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x1000))

/* ISR - Interrupt Source Register bit definitions */
#define M5272_ISR_INT1		(1 << 31)
#define M5272_ISR_INT2		(1 << 30)
#define M5272_ISR_INT3		(1 << 29)
#define M5272_ISR_INT4		(1 << 28)
#define M5272_ISR_TMR1		(1 << 27)
#define M5272_ISR_TMR2		(1 << 26)
#define M5272_ISR_TMR3		(1 << 25)
#define M5272_ISR_TMR4		(1 << 24)
#define M5272_ISR_UART1		(1 << 23)
#define M5272_ISR_UART2		(1 << 22)
#define M5272_ISR_PLI_P		(1 << 21)
#define M5272_ISR_PLI_A		(1 << 20)
#define M5272_ISR_USB0		(1 << 19)
#define M5272_ISR_USB1		(1 << 18)
#define M5272_ISR_USB2		(1 << 17)
#define M5272_ISR_USB3		(1 << 16)
#define M5272_ISR_USB4		(1 << 15)
#define M5272_ISR_USB5		(1 << 14)
#define M5272_ISR_USB6		(1 << 13)
#define M5272_ISR_USB7		(1 << 12)
#define M5272_ISR_DMA		(1 << 11)
#define M5272_ISR_ERx		(1 << 10)
#define M5272_ISR_ETx		(1 <<  9)
#define M5272_ISR_ENTC		(1 <<  8)
#define M5272_ISR_QSPI		(1 <<  7)
#define M5272_ISR_INT5		(1 <<  6)
#define M5272_ISR_INT6		(1 <<  5)
#define M5272_ISR_SWTO		(1 <<  4)

/* Interrupt numbers on the 5272 are at fixed positions above
   the base value (INT_NUM_BASE) defined in the BSP (config.h.)
   INT_NUM_BASE must be a multiple of 32, and not less than 64.
*/
#define INT_NUM_SPURIOUS    (INT_NUM_BASE+0x00)     /* reserved */
#define INT_NUM_INT1        (INT_NUM_BASE+0x01)     /* external int 1 */
#define INT_NUM_INT2        (INT_NUM_BASE+0x02)     /* external int 2 */
#define INT_NUM_INT3        (INT_NUM_BASE+0x03)     /* external int 3 */
#define INT_NUM_INT4        (INT_NUM_BASE+0x04)     /* external int 4 */
#define INT_NUM_TMR1        (INT_NUM_BASE+0x05)     /* timer 1 */
#define INT_NUM_TMR2        (INT_NUM_BASE+0x06)     /* timer 2 */
#define INT_NUM_TMR3        (INT_NUM_BASE+0x07)     /* timer 3 */
#define INT_NUM_TMR4        (INT_NUM_BASE+0x08)     /* timer 4 */
#define INT_NUM_UART1       (INT_NUM_BASE+0x09)     /* uart 1 */
#define INT_NUM_UART2       (INT_NUM_BASE+0x0a)     /* uart 2 */
#define INT_NUM_PLIP        (INT_NUM_BASE+0x0b)     /* plic 2kHz periodic */
#define INT_NUM_PLIA        (INT_NUM_BASE+0x0c)     /* plic async */
#define INT_NUM_USB0        (INT_NUM_BASE+0x0d)     /* usb endpoint 0 */
#define INT_NUM_USB1        (INT_NUM_BASE+0x0e)     /* usb endpoint 1 */
#define INT_NUM_USB2        (INT_NUM_BASE+0x0f)     /* usb endpoint 2 */
#define INT_NUM_USB3        (INT_NUM_BASE+0x10)     /* usb endpoint 3 */
#define INT_NUM_USB4        (INT_NUM_BASE+0x11)     /* usb endpoint 4 */
#define INT_NUM_USB5        (INT_NUM_BASE+0x12)     /* usb endpoint 5 */
#define INT_NUM_USB6        (INT_NUM_BASE+0x13)     /* usb endpoint 6 */
#define INT_NUM_USB7        (INT_NUM_BASE+0x14)     /* usb endpoint 7 */
#define INT_NUM_DMA         (INT_NUM_BASE+0x15)     /* dma controller */
#define INT_NUM_ERX         (INT_NUM_BASE+0x16)     /* ethernet receiver */
#define INT_NUM_ETX         (INT_NUM_BASE+0x17)     /* ethernet transmitter */
#define INT_NUM_ENTC        (INT_NUM_BASE+0x18)     /* ethernet module */
#define INT_NUM_QSPI        (INT_NUM_BASE+0x19)     /* queued serial i'f */
#define INT_NUM_INT5        (INT_NUM_BASE+0x1a)     /* external int 5 */
#define INT_NUM_INT6        (INT_NUM_BASE+0x1b)     /* external int 6 */
#define INT_NUM_SWTO        (INT_NUM_BASE+0x1c)     /* s/w watchdog */
#define INT_NUM_RES1        (INT_NUM_BASE+0x1d)     /* reserved */
#define INT_NUM_RES2        (INT_NUM_BASE+0x1e)     /* reserved */
#define INT_NUM_RES3        (INT_NUM_BASE+0x1f)     /* reserved */

#ifdef __cplusplus
}
#endif

#endif /* __INCm5272h */