m5272.h

IXP425的BSP代码

/* m5272.h - Motorola MCF5272 CPU control registers */

/* Copyright 1994-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,20mar01,hjg  Created from m5206e.h
*/

/*
This file contains I/O addresses and related constants for the MCF5272
*/

#ifndef __INCm5272h
#define __INCm5272h

#ifdef __cplusplus
extern "C" {
#endif

/*
Need to use a distinct cast macro in order to not conflict with other
include files.
*/

#ifdef	_ASMLANGUAGE
#define	CAST_M5272(x)		
#else	/* _ASMLANGUAGE */
#define	CAST_M5272(x)		(x)
#endif	/* _ASMLANGUAGE */

/* Size of internal SRAM */

#define M5272_SRAM_SIZE		4096		/* size of internal SRAM */

/* System Integration Module register addresses */
#define M5272_SIM_MBAR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x000))
#define M5272_SIM_SCR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x004))
#define M5272_SIM_SPR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x006))
#define M5272_SIM_PMR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x008))
#define M5272_SIM_ALPR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x00e))
#define M5272_SIM_DIR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x010))

#define M5272_SIM_MBAR_BA	(0xffff << 16)	/* base address */
#define M5272_SIM_MBAR_SC	(1 << 4)	/* set masks supervisor code */
#define M5272_SIM_MBAR_SD	(1 << 3)	/* set masks supervisor data */
#define M5272_SIM_MBAR_UC	(1 << 2)	/* set masks user code */
#define M5272_SIM_MBAR_UD	(1 << 1)	/* set masks user data */
#define M5272_SIM_MBAR_V	(1 << 0)	/* settings are valid */

#define M5272_SIM_SCR_RSTSRC	(3 << 12)	/* reset source */
#define M5272_SIM_SCR_Priority	(1 << 8)	/* select bus priority scheme */
#define M5272_SIM_SCR_AR	(1 << 7)	/* assume request */
#define M5272_SIM_SCR_SoftRST	(1 << 6)	/* reset on-chip peripherals */
#define M5272_SIM_SCR_BusLock	(1 << 3)	/* lock ownership of the bus */
#define M5272_SIM_SCR_HWR_128	(0x0)		/* hw watchdog   128 clocks */
#define M5272_SIM_SCR_HWR_256	(0x1)		/* hw watchdog   256 clocks */
#define M5272_SIM_SCR_HWR_512	(0x2)		/* hw watchdog   512 clocks */
#define M5272_SIM_SCR_HWR_1024	(0x3)		/* hw watchdog  1024 clocks */
#define M5272_SIM_SCR_HWR_2048	(0x4)		/* hw watchdog  2048 clocks */
#define M5272_SIM_SCR_HWR_4096	(0x5)		/* hw watchdog  4096 clocks */
#define M5272_SIM_SCR_HWR_8192	(0x6)		/* hw watchdog  8192 clocks */
#define M5272_SIM_SCR_HWR_16384	(0x7)		/* hw watchdog 16384 clocks */

#define M5272_SIM_SPR_ADC	(1 << 15)	/* addr decode conflict */
#define M5272_SIM_SPR_WPV	(1 << 14)	/* wr protect violation */
#define M5272_SIM_SPR_SMV	(1 << 13)	/* stopped module viol */
#define M5272_SIM_SPR_PE	(1 << 12)	/* peripheral error */
#define M5272_SIM_SPR_HWT	(1 << 11)	/* hw watchdog timer */
#define M5272_SIM_SPR_RPV	(1 << 10)	/* read protect viol */
#define M5272_SIM_SPR_EXT	(1 << 9)	/* extern. transf. err. */
#define M5272_SIM_SPR_SUV	(1 << 8)	/* superv./user viol */
#define M5272_SIM_SPR_ADCEN	(1 << 7)	/* addr decode conflict, excp */
#define M5272_SIM_SPR_WPVEN	(1 << 6)	/* wr protect violation, excp */
#define M5272_SIM_SPR_SMVEN	(1 << 5)	/* stopped module viol, excp */
#define M5272_SIM_SPR_PEVEN	(1 << 4)	/* peripheral error, excp */
#define M5272_SIM_SPR_HWTEN	(1 << 3)	/* hw watchdog timer, excp */
#define M5272_SIM_SPR_RPVEN	(1 << 2)	/* read protect viol, excp */
#define M5272_SIM_SPR_EXTEN	(1 << 1)	/* extern. transf. err., excp */
#define M5272_SIM_SPR_SUVEN	(1 << 0)	/* superv./user viol, excp */

#define M5272_SIM_PMR_BDMPDN	(1 << 31)	/* debug power-down enable */
#define M5272_SIM_PMR_ENETPDN	(1 << 26)	/* ethernet power-down enable */
#define M5272_SIM_PMR_PLIPDN	(1 << 25)	/* PLIC power-down enable */
#define M5272_SIM_PMR_DRAMPDN	(1 << 24)	/* DRAM contr. pwrdwn enable */
#define M5272_SIM_PMR_DMAPDN	(1 << 23)	/* DMA contr. pwrdwn enable */
#define M5272_SIM_PMR_PWMPDN	(1 << 22)	/* PWM power-down enable */
#define M5272_SIM_PMR_QSPIPDN	(1 << 21)	/* QSPI power-down enable */
#define M5272_SIM_PMR_TIMERPDN	(1 << 20)	/* timer power-down enable */
#define M5272_SIM_PMR_GPIOPDN	(1 << 19)	/* Parallel port pwrdwn enable*/
#define M5272_SIM_PMR_USBPDN	(1 << 18)	/* USB power-down enable */
#define M5272_SIM_PMR_UART1PDN	(1 << 17)	/* UART1 power-down enable */
#define M5272_SIM_PMR_UART0PDN	(1 << 16)	/* UART0 power-down enable */ 
#define M5272_SIM_PMR_USBWK	(1 << 10)	/* USB wakeup enable */ 
#define M5272_SIM_PMR_UART1WK	(1 << 9)	/* UART1 wakeup enable */ 
#define M5272_SIM_PMR_UART0WK	(1 << 8)	/* UART0 wakeup enable */ 
#define M5272_SIM_PMR_MOS	(1 << 5)	/* main oscillator stop */ 
#define M5272_SIM_PMR_SLPEN	(1 << 4)	/* sleep enable */ 

#define M5272_SIM_DIR_VERSION	(0xf << 28)	/* version number */ 
#define M5272_SIM_DIR_DSGNCNTR	(0x3f << 22)	/* design center */ 
#define M5272_SIM_DIR_DEVNR	(0x3ff << 12)	/* device number */ 
#define M5272_SIM_DIR_JEDEC	(0xfff << 1)	/* reduced Motorola-JEDEC-ID */ 

/* Interrupt Controller Registers */
#define M5272_SIM_ICR1(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x020))
#define M5272_SIM_ICR2(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x024))
#define M5272_SIM_ICR3(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x028))
#define M5272_SIM_ICR4(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x02c))
#define M5272_SIM_ISR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x030))
#define M5272_SIM_PITR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x034))
#define M5272_SIM_PIWR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x038))
#define M5272_SIM_PIVR(base)	(CAST_M5272(volatile UINT8  *)((base) + 0x03f))

#define M5272_SIM_PITR_POS_EDGE	(0x00000000)	/* positive edge triggered */
#define M5272_SIM_PITR_NEG_EDGE	(0xf0000060)	/* negative edge triggered */

/* Chip Select Registers */
#define M5272_CS_CSBR0(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x040))
#define M5272_CS_CSOR0(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x044))
#define M5272_CS_CSBR1(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x048))
#define M5272_CS_CSOR1(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x04c))
#define M5272_CS_CSBR2(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x050))
#define M5272_CS_CSOR2(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x054))
#define M5272_CS_CSBR3(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x058))
#define M5272_CS_CSOR3(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x05c))
#define M5272_CS_CSBR4(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x060))
#define M5272_CS_CSOR4(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x064))
#define M5272_CS_CSBR5(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x068))
#define M5272_CS_CSOR5(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x06c))
#define M5272_CS_CSBR6(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x070))
#define M5272_CS_CSOR6(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x074))
#define M5272_CS_CSBR7(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x078))
#define M5272_CS_CSOR7(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x07c))

#define M5272_CS_CSBR_BA	(0xfffff << 12)	/* base address */
#define M5272_CS_CSBR_EBI	(3 << 10)	/* ext. bus interface modes */
#define M5272_CS_CSBR_BW	(3 << 8)	/* bus width */
#define M5272_CS_CSBR_SUPER	(1 << 7)	/* supervisor mode */
#define M5272_CS_CSBR_TT	(3 << 5)	/* transfer type */
#define M5272_CS_CSBR_TM	(7 << 2)	/* transfer modifier */
#define M5272_CS_CSBR_CTM	(1 << 1)	/* compare TM */
#define M5272_CS_CSBR_ENABLE	(1 << 0)	/* enable/disable chip select */

#define M5272_CS_CSBR_BW_LONGW	(0x0 << 8)	/* bus width = 32 bit */
#define M5272_CS_CSBR_BW_BYTE	(0x1 << 8)	/* bus width = 8 bit */
#define M5272_CS_CSBR_BW_WORD	(0x2 << 8)	/* bus width = 16 bit */
#define M5272_CS_CSBR_BW_LINE	(0x3 << 8)	/* bus width = cache line (32)*/
#define M5272_CS_CSBR_EBI_1632	(0x0 << 10)		/* 16/32 bit SRAM/ROM */
#define M5272_CS_CSBR_EBI_SDRAM	(0x1 << 10)		/* SDRAM (CS7 only) */
#define M5272_CS_CSBR_EBI_8	(0x3 << 10)		/* 8 bit SRAM/ROM */

#define M5272_CS_CSOR_BAM	(0xfffff << 12)	/* address mask */
#define M5272_CS_CSOR_ASET	(1 << 11)	/* address setup enable */
#define M5272_CS_CSOR_WRAH	(1 << 10)	/* write address hold enable */
#define M5272_CS_CSOR_RDAH	(1 << 9)	/* read address hold enable */
#define M5272_CS_CSOR_EXTBURST	(1 << 8)	/* enable extended burst */
#define M5272_CS_CSOR_WS(a)	(((a)&0x1f)<<2)	/* wait state generator */
#define M5272_CS_CSOR_RW	(1 << 1)	/* RW and MRW determine if */
#define M5272_CS_CSOR_MRW	(1 << 0)	/* read only or write only  */

#define M5272_CS_CSOR_BAM_32M	(0xfe000000)
#define M5272_CS_CSOR_BAM_16M	(0xff000000)
#define M5272_CS_CSOR_BAM_8M	(0xff800000)
#define M5272_CS_CSOR_BAM_4M	(0xffc00000)
#define M5272_CS_CSOR_BAM_2M	(0xffe00000)
#define M5272_CS_CSOR_BAM_1M	(0xfff00000)
#define M5272_CS_CSOR_BAM_512K	(0xfff80000)
#define M5272_CS_CSOR_BAM_256K	(0xfffc0000)
#define M5272_CS_CSOR_BAM_128K	(0xfffe0000)
#define M5272_CS_CSOR_BAM_64K	(0xffff0000)
#define M5272_CS_CSOR_BAM_32K	(0xffff8000)
#define M5272_CS_CSOR_BAM_16K	(0xffffc000)
#define M5272_CS_CSOR_BAM_8K	(0xffffe000)
#define M5272_CS_CSOR_BAM_4K	(0xfffff000)

/* Software Watchdog Registers */
#define M5272_SIM_WRRR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x282))
#define M5272_SIM_WIRR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x286))
#define M5272_SIM_WCR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x28a))
#define M5272_SIM_WER(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x28e))

#define M5272_SIM_WRRR_REF	(0x7fff << 1)	/* reference value */ 
#define M5272_SIM_WRRR_EN	(1 << 0)	/* enable watchdog */ 

#define M5272_SIM_WIRR_REF	(0x7fff << 1)	/* reference value */ 
#define M5272_SIM_WIRR_IEN	(1 << 0)	/* enable interrupt */ 

#define M5272_SIM_WCR_COUNT	(0xffff << 0)	/* counter value */ 

#define M5272_SIM_WER_WIE	(1 << 0)	/* watchdog interrupt event */ 

/* GPIO Port Register Memory Map */
#define M5272_GPIO_PACNT(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x080))
#define M5272_GPIO_PADDR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x084))
#define M5272_GPIO_PADAT(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x086))
#define M5272_GPIO_PBCNT(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x088))
#define M5272_GPIO_PBDDR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x08c))
#define M5272_GPIO_PBDAT(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x08e))
#define M5272_GPIO_PCDDR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x094))
#define M5272_GPIO_PCDAT(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x096))
#define M5272_GPIO_PDCNT(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x098))

#define M5272_GPIO_PACNT_PACNT15	(3 << 30)	/* configure pin M3 */ 
#define M5272_GPIO_PACNT_PACNT14	(3 << 28)	/* configure pin M2 */ 
#define M5272_GPIO_PACNT_PACNT13	(3 << 26)	/* configure pin L3 */ 
#define M5272_GPIO_PACNT_PACNT12	(3 << 24)	/* configure pin L2 */ 
#define M5272_GPIO_PACNT_PACNT11	(3 << 22)	/* configure pin L1 */ 
#define M5272_GPIO_PACNT_PACNT10	(3 << 20)	/* configure pin K5 */ 
#define M5272_GPIO_PACNT_PACNT9		(3 << 18)	/* configure pin J3 */ 
#define M5272_GPIO_PACNT_PACNT8		(3 << 16)	/* configure pin J2 */ 
#define M5272_GPIO_PACNT_PACNT7		(3 << 14)	/* configure pin P1 */ 
#define M5272_GPIO_PACNT_PACNT6		(3 << 12)	/* configure pin E1 */ 
#define M5272_GPIO_PACNT_PACNT5		(3 << 10)	/* configure pin E2 */ 
#define M5272_GPIO_PACNT_PACNT4		(3 << 8)	/* configure pin E3 */ 
#define M5272_GPIO_PACNT_PACNT3		(3 << 6)	/* configure pin E4 */ 
#define M5272_GPIO_PACNT_PACNT2		(3 << 4)	/* configure pin E5 */ 
#define M5272_GPIO_PACNT_PACNT1		(3 << 2)	/* configure pin D1 */ 
#define M5272_GPIO_PACNT_PACNT0		(3 << 0)	/* configure pin D2 */ 

#define M5272_GPIO_PBCNT_PBCNT15	(3 << 30)	/* configure pin P10 */ 
#define M5272_GPIO_PBCNT_PBCNT14	(3 << 28)	/* configure pin L9 */ 
#define M5272_GPIO_PBCNT_PBCNT13	(3 << 26)	/* configure pin M9 */ 
#define M5272_GPIO_PBCNT_PBCNT12	(3 << 24)	/* configure pin N9 */ 
#define M5272_GPIO_PBCNT_PBCNT11	(3 << 22)	/* configure pin P9 */ 
#define M5272_GPIO_PBCNT_PBCNT10	(3 << 20)	/* configure pin L8 */ 
#define M5272_GPIO_PBCNT_PBCNT9		(3 << 18)	/* configure pin M8 */ 
#define M5272_GPIO_PBCNT_PBCNT8		(3 << 16)	/* configure pin N8 */ 
#define M5272_GPIO_PBCNT_PBCNT7		(3 << 14)	/* configure pin M6 */ 
#define M5272_GPIO_PBCNT_PBCNT6		(3 << 12)	/* configure pin G4 */ 
#define M5272_GPIO_PBCNT_PBCNT5		(3 << 10)	/* configure pin F3 */ 
#define M5272_GPIO_PBCNT_PBCNT4		(3 << 8)	/* configure pin G3 */ 
#define M5272_GPIO_PBCNT_PBCNT3		(3 << 6)	/* configure pin H3 */ 
#define M5272_GPIO_PBCNT_PBCNT2		(3 << 4)	/* configure pin H2 */ 
#define M5272_GPIO_PBCNT_PBCNT1		(3 << 2)	/* configure pin H1 */ 
#define M5272_GPIO_PBCNT_PBCNT0		(3 << 0)	/* configure pin H4 */ 

#define M5272_GPIO_PDCNT_PDCNT7	(3 << 14)	/* configure pin K6 */ 
#define M5272_GPIO_PDCNT_PDCNT6	(3 << 12)	/* configure pin P5 */ 
#define M5272_GPIO_PDCNT_PDCNT5	(3 << 10)	/* configure pin P2 */ 
#define M5272_GPIO_PDCNT_PDCNT4	(3 << 8)	/* configure pin K1 */ 
#define M5272_GPIO_PDCNT_PDCNT3	(3 << 6)	/* configure pin K3 */ 
#define M5272_GPIO_PDCNT_PDCNT2	(3 << 4)	/* configure pin K2 */ 
#define M5272_GPIO_PDCNT_PDCNT1	(3 << 2)	/* configure pin K1 */ 
#define M5272_GPIO_PDCNT_PDCNT0	(3 << 0)	/* configure pin J4 */ 

/* QSPI Module Memory Map */
#define M5272_QSPI_QMR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x0a0))
#define M5272_QSPI_QDLYR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x0a4))
#define M5272_QSPI_QWR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x0a8))
#define M5272_QSPI_QIR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x0ac))
#define M5272_QSPI_QAR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x0b0))
#define M5272_QSPI_QDR(base)	(CAST_M5272(volatile UINT16 *)((base) + 0x0b4))

/* PWM Module Memory Map */
#define M5272_PWM_PWCR1(base)	(CAST_M5272(volatile UINT8  *)((base) + 0x0c0))
#define M5272_PWM_PWCR2(base)	(CAST_M5272(volatile UINT8  *)((base) + 0x0c4))
#define M5272_PWM_PWCR3(base)	(CAST_M5272(volatile UINT8  *)((base) + 0x0c8))
#define M5272_PWM_PWWD1(base)	(CAST_M5272(volatile UINT8  *)((base) + 0x0d0))
#define M5272_PWM_PWWD2(base)	(CAST_M5272(volatile UINT8  *)((base) + 0x0d4))
#define M5272_PWM_PWWD3(base)	(CAST_M5272(volatile UINT8  *)((base) + 0x0d8))

/* DMA Module Memory Map */
#define M5272_DMA_DMR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x0e0))
#define M5272_DMA_DIR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x0e6))
#define M5272_DMA_DBCR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x0e8))
#define M5272_DMA_DSAR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x0ec))
#define M5272_DMA_DDAR(base)	(CAST_M5272(volatile UINT32 *)((base) + 0x0f0))

#define M5272_DMA_DMR_RESET	(1 << 31)	/* reset */