m68360.h

IXP425的BSP代码

    UINT16	character2;		/* control character 2 */
    UINT16	character3;		/* control character 3 */
    UINT16	character4;		/* control character 4 */
    UINT16	character5;		/* control character 5 */
    UINT16	character6;		/* control character 6 */
    UINT16	character7;		/* control character 7 */
    UINT16	character8;		/* control character 8 */
    UINT16	rccm;			/* receive control character mask */
    UINT16	rccr;			/* receive control character register */
    UINT16	rlbc;			/* receive last break character */
    } SCC_UART_PROTO;

/* SCC UART Protocol Specific Mode Register definitions */

#define SCC_UART_PSMR_TPM_ODD	0x0000		/* odd parity mode (Tx) */
#define SCC_UART_PSMR_TPM_LOW	0x0001		/* low parity mode (Tx) */
#define SCC_UART_PSMR_TPM_EVEN	0x0002		/* even parity mode (Tx) */
#define SCC_UART_PSMR_TPM_HIGH	0x0003		/* high parity mode (Tx) */
#define SCC_UART_PSMR_RPM_ODD	0x0000		/* odd parity mode (Rx) */
#define SCC_UART_PSMR_RPM_LOW	0x0004		/* low parity mode (Rx) */
#define SCC_UART_PSMR_RPM_EVEN	0x0008		/* even parity mode (Rx) */
#define SCC_UART_PSMR_RPM_HIGH	0x000c		/* high parity mode (Rx) */
#define SCC_UART_PSMR_PEN	0x0010		/* parity enable */
#define SCC_UART_PSMR_DRT	0x0040		/* disable Rx while Tx */
#define SCC_UART_PSMR_SYN	0x0080		/* synchronous mode */
#define SCC_UART_PSMR_RZS	0x0100		/* receive zero stop bits */
#define SCC_UART_PSMR_FRZ	0x0200		/* freeze transmission */
#define SCC_UART_PSMR_UM_NML	0x0000		/* noraml UART operation */
#define SCC_UART_PSMR_UM_MULT_M	0x0400		/* multidrop non-auto mode */
#define SCC_UART_PSMR_UM_MULT_A	0x0c00		/* multidrop automatic mode */
#define SCC_UART_PSMR_CL_5BIT	0x0000		/* 5 bit character length */
#define SCC_UART_PSMR_CL_6BIT	0x1000		/* 6 bit character length */
#define SCC_UART_PSMR_CL_7BIT	0x2000		/* 7 bit character length */
#define SCC_UART_PSMR_CL_8BIT	0x3000		/* 8 bit character length */
#define SCC_UART_PSMR_SL	0x4000		/* 1 or 2 bit stop length */
#define SCC_UART_PSMR_FLC	0x8000		/* flow control */
	
/* SCC UART Event and Mask Register definitions */

#define SCC_UART_SCCX_RX 	0x0001		/* buffer received */
#define SCC_UART_SCCX_TX 	0x0002		/* buffer transmitted */
#define SCC_UART_SCCX_BSY 	0x0004		/* busy condition */
#define SCC_UART_SCCX_CCR 	0x0008		/* control character received */
#define SCC_UART_SCCX_BRK_S 	0x0020	 	/* break start */
#define SCC_UART_SCCX_BRK_E 	0x0040		/* break end */
#define SCC_UART_SCCX_GRA 	0x0080		/* graceful stop complete */
#define SCC_UART_SCCX_IDL	0x0100		/* idle sequence stat changed */
#define SCC_UART_SCCX_AB  	0x0200		/* autobaud lock */
#define SCC_UART_SCCX_GL_T 	0x0800		/* glitch on Tx */
#define SCC_UART_SCCX_GL_R 	0x1000		/* glitch on Rx */

/* SCC UART Receive Buffer Descriptor definitions */

#define SCC_UART_RX_BD_CD	0x0001		/* carrier detect loss */
#define SCC_UART_RX_BD_OV	0x0002		/* receiver overrun */
#define SCC_UART_RX_BD_PR	0x0008		/* parity error */
#define SCC_UART_RX_BD_FR	0x0010		/* framing error */
#define SCC_UART_RX_BD_BR	0x0020		/* break received */
#define SCC_UART_RX_BD_AM	0x0080		/* address match */
#define SCC_UART_RX_BD_ID	0x0100		/* buf closed on IDLES */
#define SCC_UART_RX_BD_CM	0x0200		/* continous mode */
#define SCC_UART_RX_BD_ADDR	0x0400		/* buffer contains address */
#define SCC_UART_RX_BD_CNT	0x0800		/* control character */
#define SCC_UART_RX_BD_INT	0x1000		/* interrupt generated */
#define SCC_UART_RX_BD_WRAP	0x2000		/* wrap back to first BD */
#define SCC_UART_RX_BD_EMPTY	0x8000		/* buffer is empty */

/* SCC UART Transmit Buffer Descriptor definitions */

#define SCC_UART_TX_BD_CT	0x0001		/* cts was lost during tx */
#define SCC_UART_TX_BD_NS	0x0080		/* no stop bit transmitted */
#define SCC_UART_TX_BD_PREAMBLE	0x0100		/* enable preamble */
#define SCC_UART_TX_BD_CM	0x0200		/* continous mode */
#define SCC_UART_TX_BD_ADDR	0x0400		/* buffer contains address */
#define SCC_UART_TX_BD_CTSR	0x0800		/* normal cts error reporting */
#define SCC_UART_TX_BD_INT	0x1000		/* interrupt generated */
#define SCC_UART_TX_BD_WRAP	0x2000		/* wrap back to first BD */
#define SCC_UART_TX_BD_READY	0x8000		/* buffer is being sent */

/* SCC Ethernet protocol specific parameters */

typedef struct		/* SCC_ETHER_PROTO */
    {
    UINT32	c_pres;			/* preset CRC */
    UINT32	c_mask;			/* constant mask for CRC */
    UINT32	crcec;			/* CRC error counter */
    UINT32	alec;			/* alignment error counter */
    UINT32	disfc;			/* discard frame counter */
    UINT16	pads;			/* short frame pad value */
    UINT16	ret_lim;		/* retry limit threshold */
    UINT16	ret_cnt;		/* retry limit counter */
    UINT16	mflr;			/* maximum frame length register */
    UINT16	minflr;			/* minimum frame length register */
    UINT16	maxd1;			/* max DMA1 length register */
    UINT16	maxd2;			/* max DMA2 length register */
    UINT16	maxd;			/* Rx max DMA */
    UINT16	dma_cnt;		/* Rx DMA counter */
    UINT16	max_b;			/* max BD byte count */
    UINT16	gaddr1;			/* group address filter 1 */
    UINT16	gaddr2;			/* group address filter 2 */
    UINT16	gaddr3;			/* group address filter 3 */
    UINT16	gaddr4;			/* group address filter 4 */
    UINT32	tbuf0_data0;		/* save area 0 - current frame */
    UINT32	tbuf0_data1;		/* save area 1 - current frame */
    UINT32	tbuf0_rba0;		/* ? */
    UINT32	tbuf0_crc;		/* ? */
    UINT16	tbuf0_bcnt;		/* ? */
    UINT16	paddr1_h;		/* physical address 1 (MSB) */
    UINT16	paddr1_m;		/* physical address 1 */
    UINT16	paddr1_l;		/* physical address 1 (LSB) */
    UINT16	p_per;			/* persistence */
    UINT16	rfbd_ptr;		/* Rx first BD pointer */
    UINT16	tfbd_ptr;		/* Tx first BD pointer */
    UINT16	tlbd_ptr;		/* Tx last BD pointer */
    UINT32	tbuf1_data0;		/* save area 0 - next frame */
    UINT32	tbuf1_data1;		/* ? */
    UINT32	tbuf1_rba0;		/* ? */
    UINT32	tbuf1_crc;		/* ? */
    UINT16	tbuf1_bcnt;		/* ? */
    UINT16	tx_len;			/* Tx frame length counter */
    UINT16	iaddr1;			/* individual address filter 1 */
    UINT16	iaddr2;			/* individual address filter 2 */
    UINT16	iaddr3;			/* individual address filter 3 */
    UINT16	iaddr4;			/* individual address filter 4 */
    UINT16	boff_cnt;		/* backoff counter */
    UINT16	taddr_h;		/* temp address (MSB) */
    UINT16	taddr_m;		/* temp address */
    UINT16	taddr_l;		/* temp address (LSB) */
    } SCC_ETHER_PROTO;

/* SCC Ethernet Protocol Specific Mode Register definitions */

#define SCC_ETHER_PSMR_NIB_13	0x0000		/* SFD 13 bits after TENA */
#define SCC_ETHER_PSMR_NIB_14	0x0002		/* SFD 14 bits after TENA */
#define SCC_ETHER_PSMR_NIB_15	0x0004		/* SFD 15 bits after TENA */
#define SCC_ETHER_PSMR_NIB_16	0x0006		/* SFD 16 bits after TENA */
#define SCC_ETHER_PSMR_NIB_21	0x0008		/* SFD 21 bits after TENA */
#define SCC_ETHER_PSMR_NIB_22	0x000a		/* SFD 22 bits after TENA */
#define SCC_ETHER_PSMR_NIB_23	0x000c		/* SFD 23 bits after TENA */
#define SCC_ETHER_PSMR_NIB_24	0x000e		/* SFD 24 bits after TENA */
#define SCC_ETHER_PSMR_LCW	0x0100		/* late collision window */
#define SCC_ETHER_PSMR_SIP	0x0200		/* sample input pins */
#define SCC_ETHER_PSMR_LPB	0x0400		/* loopback operation */
#define SCC_ETHER_PSMR_SBT	0x0800		/* stop backoff timer */
#define SCC_ETHER_PSMR_BRO	0x0100		/* broadcast address */
#define SCC_ETHER_PSMR_PRO	0x0200		/* promiscuous mode */
#define SCC_ETHER_PSMR_CRC	0x0800		/* CRC selection */
#define SCC_ETHER_PSMR_IAM	0x1000		/* individual address mode */
#define SCC_ETHER_PSMR_RSH	0x2000		/* receive short frame */
#define SCC_ETHER_PSMR_FC	0x4000		/* force collision */
#define SCC_ETHER_PSMR_HBC	0x8000		/* heartbeat checking*/

/* SCC Ethernet Event and Mask Register definitions */

#define SCC_ETHER_SCCX_RXB 	0x0001		/* buffer received event */
#define SCC_ETHER_SCCX_TXB 	0x0002		/* buffer transmitted event */
#define SCC_ETHER_SCCX_BSY 	0x0004		/* busy condition */
#define SCC_ETHER_SCCX_RXF 	0x0008		/* frame received event */
#define SCC_ETHER_SCCX_TXE	0x0010		/* transmission error event */
#define SCC_ETHER_SCCX_GRA 	0x0080		/* graceful stop event */

/* SCC Ethernet Receive Buffer Descriptor definitions */

#define SCC_ETHER_RX_BD_CL	0x0001		/* collision condition */
#define SCC_ETHER_RX_BD_OV	0x0002		/* overrun condition */
#define SCC_ETHER_RX_BD_CR	0x0004		/* Rx CRC error */
#define SCC_ETHER_RX_BD_SH	0x0008		/* short frame received */
#define SCC_ETHER_RX_BD_NO	0x0010		/* Rx nonoctet aligned frame */
#define SCC_ETHER_RX_BD_LG	0x0020		/* Rx frame length violation */
#define SCC_ETHER_RX_BD_M	0x0100		/* miss bit for prom mode */
#define SCC_ETHER_RX_BD_F	0x0400		/* buffer is first in frame */
#define SCC_ETHER_RX_BD_L	0x0800		/* buffer is last in frame */
#define SCC_ETHER_RX_BD_I	0x1000		/* interrupt on receive */
#define SCC_ETHER_RX_BD_W	0x2000		/* last BD in ring */
#define SCC_ETHER_RX_BD_E	0x8000		/* buffer is empty */

/* SCC Ethernet Transmit Buffer Descriptor definitions */

#define SCC_ETHER_TX_BD_CSL	0x0001		/* carrier sense lost */
#define SCC_ETHER_TX_BD_UN	0x0002		/* underrun */
#define SCC_ETHER_TX_BD_RC	0x003c		/* retry count */
#define SCC_ETHER_TX_BD_RL	0x0040		/* retransmission limit */
#define SCC_ETHER_TX_BD_LC	0x0080		/* late collision */
#define SCC_ETHER_TX_BD_HB	0x0100		/* heartbeat */
#define SCC_ETHER_TX_BD_DEF	0x0200		/* defer indication */
#define SCC_ETHER_TX_BD_TC	0x0400		/* auto transmit CRC */
#define SCC_ETHER_TX_BD_L	0x0800		/* buffer is last in frame */
#define SCC_ETHER_TX_BD_I	0x1000		/* interrupt on transmit */
#define SCC_ETHER_TX_BD_W	0x2000		/* last BD in ring */
#define SCC_ETHER_TX_BD_PAD	0x4000		/* auto pad short frames */
#define SCC_ETHER_TX_BD_R	0x8000		/* buffer is ready */

/* SCC - Serial Comunications Controller */
 
typedef struct          /* SCC_BUF */
    {
    UINT16	statusMode;		/* status and control */
    UINT16	dataLength;		/* length of data buffer in bytes */
    u_char *	dataPointer;		/* points to data buffer */
    } SCC_BUF;
 
typedef struct          /* SCC_PARAM */
    {
    UINT16	rbase;			/* Rx buffer descriptor base address */
    UINT16	tbase;			/* Tx buffer descriptor base address */
    UINT8	rfcr;			/* Rx function code */
    UINT8	tfcr;			/* Tx function code */
    UINT16	mrblr;			/* maximum receive buffer length */
    UINT32	rstate;			/* Rx internal state */
    UINT32	res1;			/* reserved/internal */
    UINT16	rbptr;			/* Rx buffer descriptor pointer */
    UINT16	res2;			/* reserved/internal */
    UINT32	res3;			/* reserved/internal */
    UINT32	tstate;			/* Tx internal state */
    UINT32	res4;			/* reserved/internal */
    UINT16	tbptr;			/* Tx buffer descriptor pointer */
    UINT16	res5;			/* reserved/internal */
    UINT32	res6;			/* reserved/internal */
    UINT32	rcrc;			/* temp receive CRC */
    UINT32	tcrc;			/* temp transmit CRC */
    } SCC_PARAM;
 
typedef struct          /* SCC */
    {
    SCC_PARAM	param;			/* SCC parameters */
    char	prot[64];		/* protocol specific area */
    } SCC;

typedef struct          /* SCC_REG */
    {
    UINT32	gsmrl;			/* SCC general mode register - low */
    UINT32	gsmrh;			/* SCC eneral mode register - high */
    UINT16	psmr;			/* SCC protocol mode register */
    UINT16	res1;			/* reserved */
    UINT16	todr;			/* SCC transmit on demand */
    UINT16	dsr;			/* SCC data sync. register */
    UINT16	scce;			/* SCC event register */
    UINT16	res2;			/* reserved */
    UINT16	sccm;			/* SCC mask register */
    UINT8	res3;			/* reserved */
    UINT8	sccs;			/* SCC status register */
    } SCC_REG;

/* SCC device descriptor */

typedef struct          /* SCC_DEV */
    {
    int 		sccNum;		/* number of SCC device */
    int 		txBdNum;	/* number of transmit buf descriptors */
    int 		rxBdNum;	/* number of receive buf descriptors */
    SCC_BUF * 		txBdBase;	/* transmit BD base address */
    SCC_BUF * 		rxBdBase;	/* receive BD base address */
    u_char * 		txBufBase;	/* transmit buffer base address */
    u_char *		rxBufBase;	/* receive buffer base address */
    UINT32 		txBufSize;	/* transmit buffer size */
    UINT32 		rxBufSize;	/* receive buffer size */
    int			txBdNext;	/* next transmit BD to fill */
    int			rxBdNext;	/* next receive BD to read */
    volatile SCC *	pScc;		/* SCC parameter RAM */
    volatile SCC_REG *	pSccReg;	/* SCC registers */
    UINT32		intMask;	/* interrupt acknowledge mask */
    } SCC_DEV;
 
#ifndef INCLUDE_TY_CO_DRV_50

/* UART SCC device descriptor */

typedef struct          /* TY_CO_DEV */
    {
    TY_DEV		tyDev;		/* tyLib will handle this portion */
    BOOL		created;	/* device has been created */
    char		numChannels;	/* number of channels to support */
    int			clockRate;	/* CPU clock frequency (Hz) */
    int 		bgrNum;		/* number of BRG being used */
    UINT32 *		pBaud;		/* BRG registers */
    UINT32		regBase;	/* register/DPR base address */
    SCC_DEV		uart;		/* UART SCC device */
    } TY_CO_DEV;

/* function declarations */

#if defined(__STDC__) || defined(__cplusplus)

IMPORT  void    tyCoInt (TY_CO_DEV * pDv);

#else	/* __STDC__ */

IMPORT	void	tyCoInt ();

#endif	/* __STDC__ */
#endif	/* INCLUDE_TY_CO_DRV_50 */
#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCm68360h */