m68360.h

IXP425的BSP代码

#define CPIC_CICR_SCbP_4	0x000c0000	/* SCCb will be used by SCC4 */
#define CPIC_CICR_SCcP_1	0x00000000	/* SCCc will be used by SCC1 */
#define CPIC_CICR_SCcP_2	0x00100000	/* SCCc will be used by SCC2 */
#define CPIC_CICR_SCcP_3	0x00200000	/* SCCc will be used by SCC3 */
#define CPIC_CICR_SCcP_4	0x00300000	/* SCCc will be used by SCC4 */
#define CPIC_CICR_SCdP_1	0x00000000	/* SCCd will be used by SCC1 */
#define CPIC_CICR_SCdP_2	0x00400000	/* SCCd will be used by SCC2 */
#define CPIC_CICR_SCdP_3	0x00800000	/* SCCd will be used by SCC3 */
#define CPIC_CICR_SCdP_4	0x00c00000	/* SCCd will be used by SCC4 */

/* CPM Interrupt Pending, Mask, and In-Serivice Register definitions */

#define CPIC_CIXR_PC11		0x00000002	/* PC11 interrupt source */
#define CPIC_CIXR_PC10		0x00000004	/* PC10 interrupt source */
#define CPIC_CIXR_SMC2		0x00000008	/* SMC2 interrupt source */
#define CPIC_CIXR_SMC1		0x00000010	/* SMC1 interrupt source */
#define CPIC_CIXR_SPI		0x00000020	/* SPI interrupt source */
#define CPIC_CIXR_PC9		0x00000040	/* PC9 interrupt source */
#define CPIC_CIXR_TMR4		0x00000080	/* TMR4 interrupt source */
#define CPIC_CIXR_PC8		0x00000200	/* PC8 interrupt source */
#define CPIC_CIXR_PC7		0x00000400	/* PC7 interrupt source */
#define CPIC_CIXR_PC6		0x00000800	/* PC6 interrupt source */
#define CPIC_CIXR_TMR3		0x00001000	/* TMR3 interrupt source */
#define CPIC_CIXR_PC5		0x00004000	/* PC5 interrupt source */
#define CPIC_CIXR_PC4		0x00008000	/* PC4 interrupt source */
#define CPIC_CIXR_RTT		0x00020000	/* RTT interrupt source */
#define CPIC_CIXR_TMR2		0x00040000	/* TMR2 interrupt source */
#define CPIC_CIXR_IDMA2		0x00100000	/* IDMA2 interrupt source */
#define CPIC_CIXR_IDMA1		0x00200000	/* IDMA1 interrupt source */
#define CPIC_CIXR_SDMA		0x00400000	/* SDMA interrupt source */
#define CPIC_CIXR_PC3		0x00800000	/* PC3 interrupt source */
#define CPIC_CIXR_PC2		0x01000000	/* PC2 interrupt source */
#define CPIC_CIXR_TMR1		0x02000000	/* TMR1 interrupt source */
#define CPIC_CIXR_PC1		0x04000000	/* PC1 interrupt source */
#define CPIC_CIXR_SCC4		0x08000000	/* SCC4 interrupt source */
#define CPIC_CIXR_SCC3		0x10000000	/* SCC3 interrupt source */
#define CPIC_CIXR_SCC2		0x20000000	/* SCC2 interrupt source */
#define CPIC_CIXR_SCC1		0x40000000	/* SCC1 interrupt source */
#define CPIC_CIXR_PC0		0x80000000	/* PC0 interrupt source */

/* CPM Based Interrupt Vectors offsets */

#define INT_OFF_ERR		0x0
#define INT_OFF_PC11		0x1
#define INT_OFF_PC10		0x2
#define INT_OFF_SMC2		0x3
#define INT_OFF_SMC1		0x4
#define INT_OFF_SPI		0x5
#define INT_OFF_PC9		0x6
#define INT_OFF_TMR4		0x7
#define INT_OFF_RES1		0x8
#define INT_OFF_PC8		0x9
#define INT_OFF_PC7		0xa
#define INT_OFF_PC6		0xb
#define INT_OFF_TMR3		0xc
#define INT_OFF_RES2		0xd
#define INT_OFF_PC5		0xe
#define INT_OFF_PC4		0xf
#define INT_OFF_RES3		0x10
#define INT_OFF_RISC		0x11
#define INT_OFF_TMR2		0x12
#define INT_OFF_RES4		0x13
#define INT_OFF_IDMA2		0x14
#define INT_OFF_IDMA1		0x15
#define INT_OFF_SDMA		0x16
#define INT_OFF_PC3		0x17
#define INT_OFF_PC2		0x18
#define INT_OFF_TMR1		0x19
#define INT_OFF_PC1		0x1a
#define INT_OFF_SCC4		0x1b
#define INT_OFF_SCC3		0x1c
#define INT_OFF_SCC2		0x1d
#define INT_OFF_SCC1		0x1e
#define INT_OFF_PC0		0x1f

/* CPM Based Interrupt Vectors addresses */

#define INT_CPM_BASE(base)	(*M360_CPM_CICR(base) & CPIC_CICR_VBA)

#define INT_VEC_ERR(base)	(INT_OFF_ERR   | INT_CPM_BASE(base))
#define INT_VEC_PC11(base)	(INT_OFF_PC11  | INT_CPM_BASE(base))
#define INT_VEC_PC10(base)	(INT_OFF_PC10  | INT_CPM_BASE(base))
#define INT_VEC_SMC2(base)	(INT_OFF_SMC2  | INT_CPM_BASE(base))
#define INT_VEC_SMC1(base)	(INT_OFF_SMC1  | INT_CPM_BASE(base))
#define INT_VEC_SPI(base)	(INT_OFF_SPI   | INT_CPM_BASE(base))
#define INT_VEC_PC9(base)	(INT_OFF_PC9   | INT_CPM_BASE(base))
#define INT_VEC_TMR4(base)	(INT_OFF_TMR4  | INT_CPM_BASE(base))
#define INT_VEC_RES1(base)	(INT_OFF_RES1  | INT_CPM_BASE(base))
#define INT_VEC_PC8(base)	(INT_OFF_PC8   | INT_CPM_BASE(base))
#define INT_VEC_PC7(base)	(INT_OFF_PC7   | INT_CPM_BASE(base))
#define INT_VEC_PC6(base)	(INT_OFF_PC6   | INT_CPM_BASE(base))
#define INT_VEC_TMR3(base)	(INT_OFF_TMR3  | INT_CPM_BASE(base))
#define INT_VEC_RES2(base)	(INT_OFF_RES2  | INT_CPM_BASE(base))
#define INT_VEC_PC5(base)	(INT_OFF_PC5   | INT_CPM_BASE(base))
#define INT_VEC_PC4(base)	(INT_OFF_PC4   | INT_CPM_BASE(base))
#define INT_VEC_RES3(base)	(INT_OFF_RES3  | INT_CPM_BASE(base))
#define INT_VEC_RISC(base)	(INT_OFF_RISC  | INT_CPM_BASE(base))
#define INT_VEC_TMR2(base)	(INT_OFF_TMR2  | INT_CPM_BASE(base))
#define INT_VEC_RES4(base)	(INT_OFF_RES4  | INT_CPM_BASE(base))
#define INT_VEC_IDMA2(base)	(INT_OFF_IDMA2 | INT_CPM_BASE(base))
#define INT_VEC_IDMA1(base)	(INT_OFF_IDMA1 | INT_CPM_BASE(base))
#define INT_VEC_SDMA(base)	(INT_OFF_SDMA  | INT_CPM_BASE(base))
#define INT_VEC_PC3(base)	(INT_OFF_PC3   | INT_CPM_BASE(base))
#define INT_VEC_PC2(base)	(INT_OFF_PC2   | INT_CPM_BASE(base))
#define INT_VEC_TMR1(base)	(INT_OFF_TMR1  | INT_CPM_BASE(base))
#define INT_VEC_PC1(base)	(INT_OFF_PC1   | INT_CPM_BASE(base))
#define INT_VEC_SCC4(base)	(INT_OFF_SCC4  | INT_CPM_BASE(base))
#define INT_VEC_SCC3(base)	(INT_OFF_SCC3  | INT_CPM_BASE(base))
#define INT_VEC_SCC2(base)	(INT_OFF_SCC2  | INT_CPM_BASE(base))
#define INT_VEC_SCC1(base)	(INT_OFF_SCC1  | INT_CPM_BASE(base))
#define INT_VEC_PC0(base)	(INT_OFF_PC0   | INT_CPM_BASE(base))

/* IDMA - Independent Direct Memory Access */
 
/* IDMA Configuration Register definitions */

#define IDMA_ICCR_IAID		0x0070		/* IDMA arbitration ID */
#define IDMA_ICCR_ISM		0x0700		/* interrupt service mask */
#define IDMA_ICCR_ARBP_1	0x0000		/* ch 1 priority over ch 2 */
#define IDMA_ICCR_ARBP_2	0x1000		/* ch 2 priority over ch 1 */
#define IDMA_ICCR_ARBP_ROT	0x2000		/* rotating priority of IDMAs */
#define IDMA_ICCR_FRZ_DIS	0x0000		/* ignore the FREEZE signal */
#define IDMA_ICCR_FRZ_EN	0x4000		/* freeze on FREEZE signal */
#define IDMA_ICCR_STP		0x8000		/* stop sys clk to IDMA chnls */

/* SDMA - Serial Direct Memory Access */
 
/* SDMA Configuration Register definitions */

#define SDMA_SDCR_INTB		0x0001		/* breakpoint interrupt mask */
#define SDMA_SDCR_INTE		0x0002		/* bus error interrupt mask */
#define SDMA_SDCR_INTR		0x0004		/* reserved interrupt mask */
#define SDMA_SDCR_SAID		0x0070		/* SDMA arbitration ID */
#define SDMA_SDCR_SISM		0x0700		/* interrupt service mask */
#define SDMA_SDCR_FRZ_DIS	0x0000		/* ignore the FREEZE signal */
#define SDMA_SDCR_FRZ_EN	0x4000		/* freeze on FREEZE signal */

/* TMR - Timers */

/* TMR Global Configuration Register definitions */

#define TMR_TGCR_RST1		0x0001		/* reset/enable timer 1 */
#define TMR_TGCR_STP1		0x0002		/* stop timer 1 */
#define TMR_TGCR_FRZ1		0x0004		/* halt timer 1 on FREEZE */
#define TMR_TGCR_GM1		0x0008		/* normal gate mode on TGATE1 */
#define TMR_TGCR_RST2		0x0010		/* reset/enable timer 2 */
#define TMR_TGCR_STP2		0x0020		/* stop timer 2 */
#define TMR_TGCR_FRZ2		0x0040		/* halt timer 2 on FREEZE */
#define TMR_TGCR_CAS2		0x0080		/* cascade timers 1 and 2 */
#define TMR_TGCR_RST3		0x0100		/* reset/enable timer 3 */
#define TMR_TGCR_STP3		0x0200		/* stop timer 3 */
#define TMR_TGCR_FRZ3		0x0400		/* halt timer 3 on FREEZE */
#define TMR_TGCR_GM2		0x0800		/* normal gate mode on TGATE2 */
#define TMR_TGCR_RST4		0x1000		/* reset/enable timer 4 */
#define TMR_TGCR_STP4		0x2000		/* stop timer 4 */
#define TMR_TGCR_FRZ4		0x4000		/* halt timer 4 on FREEZE */
#define TMR_TGCR_CAS4		0x8000		/* cascade timers 3 and 4 */

/* TMR Mode Register definitions */

#define TMR_TMR_GE		0x0001		/* enable TGATE signal */
#define TMR_TMR_ICLK_CAS	0x0000		/* input is output of timer */
#define TMR_TMR_ICLK_CLK	0x0002		/* input is general sys clock */
#define TMR_TMR_ICLK_CLK16	0x0004		/* input is sys clock div 16 */
#define TMR_TMR_ICLK_TIN	0x0006		/* input is TIN pin */
#define TMR_TMR_FRR		0x0008		/* free run/restart timer */
#define TMR_TMR_ORI		0x0010		/* output interrupt enable */
#define TMR_TMR_OM		0x0020		/* output mode */
#define TMR_TMR_CE		0x00c0		/* capture edge for TIN input */
#define TMR_TMR_PS		0xff00		/* prescaler value */

/* TMR Event Register definitions */

#define TMR_TER_CAP		0x0001		/* capture event occurred */
#define TMR_TER_REF		0x0002		/* reference event occurred */

/* SI - Serial Interface */

/* SI Mode Register definitions */

#define SI_SIMODE_TFSDa		0x00000003	/* transmit frame sync delay */
#define SI_SIMODE_GMa		0x00000004	/* grant mode TDM a */
#define SI_SIMODE_FEa		0x00000008	/* frame sync edge TDM a */
#define SI_SIMODE_CEa		0x00000010	/* clock edge TDM a */
#define SI_SIMODE_STZa		0x00000020	/* set L1TXDa to zero TDM a */
#define SI_SIMODE_CRTa		0x00000040	/* common Rx/Tx pins TDM a */
#define SI_SIMODE_DSCa		0x00000080	/* double speed clk TDM a */
#define SI_SIMODE_RFSDa		0x00000300	/* receive frame sync delay */
#define SI_SIMODE_SDMa		0x00000c00	/* SI diagnostic mode TDM a */
#define SI_SIMODE_SMC1CS	0x00007000	/* SMC1 clk source (NMSI) */
#define SI_SIMODE_SMC1		0x00008000	/* SMC1 connection (NMSI) */
#define SI_SIMODE_TFSDb		0x00030000	/* transmit frame sync delay */
#define SI_SIMODE_GMb		0x00040000	/* grant mode TDM b */
#define SI_SIMODE_FEb		0x00080000	/* frame sync edge TDM b */
#define SI_SIMODE_CEb		0x00100000	/* clock edge TDM b */
#define SI_SIMODE_STZb		0x00200000	/* set L1TXDb to zero TDM b */
#define SI_SIMODE_CRTb		0x00400000	/* common Rx/Tx pins TDM a */
#define SI_SIMODE_DSCb		0x00800000	/* double speed clock TDM b */
#define SI_SIMODE_RFSDb		0x03000000	/* receive frame sync delay */
#define SI_SIMODE_SDMb		0x0c000000	/* SI diagnostic mode TDM b */
#define SI_SIMODE_SMC2CS	0x70000000	/* SMC2 clk source (NMSI) */
#define SI_SIMODE_SMC2		0x80000000	/* SMC2 connection (NMSI) */

/* SI Clock Route Register definitions */

#define SI_SICR_TCS		0x07		/* transmit clock source SCC */
#define SI_SICR_RCS		0x38		/* receive clock source SCC */
#define SI_SICR_SC		0x40		/* SCC connection (NMSI) */
#define SI_SICR_GR		0x80		/* grant support by SCC */

/* BRG - Baud Rate Generator */

/* BRG Configuration Register definitions */

#define BRG_CR_DIV16		0x00001		/* BRG clock prescale div 16 */
#define BRG_CR_CD		0x01ffe		/* clock divider */
#define BRG_CR_ATB		0x02000		/* autobaud support */
#define BRG_CR_EXT_BRGCLK	0x00000		/* external clk source BRGCLK */
#define BRG_CR_EXT_CLK2		0x04000		/* external clk source CLK2 */
#define BRG_CR_EXT_CLK6		0x08000		/* external clk source CLK6 */
#define BRG_CR_EN		0x10000		/* enable BRG count */
#define BRG_CR_RST		0x20000		/* perform reset on BRG */

/* SCC - Serial Communication Controller */

/* General SCC Mode Register definitions */

#define SCC_GSMRL_HDLC		0x00000000	/* HDLC mode */
#define SCC_GSMRL_APPLETALK	0x00000002	/* AppleTalk mode (LocalTalk) */
#define SCC_GSMRL_SS7		0x00000003	/* SS7 mode (microcode) */
#define SCC_GSMRL_UART		0x00000004	/* UART mode */
#define SCC_GSMRL_PROFI_BUS	0x00000005	/* Profi-Bus mode (microcode) */
#define SCC_GSMRL_ASYNC_HDLC	0x00000006	/* async HDLC mode (microcode)*/
#define SCC_GSMRL_V14		0x00000007	/* V.14 mode */
#define SCC_GSMRL_BISYNC	0x00000008	/* BISYNC mode */
#define SCC_GSMRL_DDCMP		0x00000009	/* DDCMP mode (microcode) */
#define SCC_GSMRL_ETHERNET	0x0000000c	/* ethernet mode (SCC1 only) */
#define SCC_GSMRL_ENT		0x00000010	/* enable transmitter */
#define SCC_GSMRL_ENR		0x00000020	/* enable receiver */
#define SCC_GSMRL_LOOPBACK	0x00000040	/* local loopback mode */
#define SCC_GSMRL_ECHO		0x00000080	/* automatic echo mode */
#define SCC_GSMRL_TENC		0x00000700	/* transmitter encoding method*/
#define SCC_GSMRL_RENC		0x00003800	/* receiver encoding method */
#define SCC_GSMRL_RDCR_X8	0x00004000	/* receive DPLL clock x8 */
#define SCC_GSMRL_RDCR_X16	0x00008000	/* receive DPLL clock x16 */
#define SCC_GSMRL_RDCR_X32	0x0000c000	/* receive DPLL clock x32 */
#define SCC_GSMRL_TDCR_X8	0x00010000	/* transmit DPLL clock x8 */
#define SCC_GSMRL_TDCR_X16	0x00020000	/* transmit DPLL clock x16 */
#define SCC_GSMRL_TDCR_X32	0x00030000	/* transmit DPLL clock x32 */
#define SCC_GSMRL_TEND		0x00040000	/* transmitter frame ending */
#define SCC_GSMRL_TPP_00	0x00180000	/* Tx preamble pattern = 00 */
#define SCC_GSMRL_TPP_10	0x00080000	/* Tx preamble pattern = 10 */
#define SCC_GSMRL_TPP_01	0x00100000	/* Tx preamble pattern = 01 */
#define SCC_GSMRL_TPP_11	0x00180000	/* Tx preamble pattern = 11 */
#define SCC_GSMRL_TPL_NONE	0x00000000	/* no Tx preamble (default) */
#define SCC_GSMRL_TPL_8		0x00200000	/* Tx preamble = 1 byte */
#define SCC_GSMRL_TPL_16	0x00400000	/* Tx preamble = 2 bytes */
#define SCC_GSMRL_TPL_32	0x00600000	/* Tx preamble = 4 bytes */
#define SCC_GSMRL_TPL_48	0x00800000	/* Tx preamble = 6 bytes */
#define SCC_GSMRL_TPL_64	0x00a00000	/* Tx preamble = 8 bytes */
#define SCC_GSMRL_TPL_128	0x00c00000	/* Tx preamble = 16 bytes */
#define SCC_GSMRL_TINV		0x01000000	/* DPLL transmit input invert */
#define SCC_GSMRL_RINV		0x02000000	/* DPLL receive input invert */
#define SCC_GSMRL_TSNC		0x0c000000	/* transmit sense */
#define SCC_GSMRL_TCI		0x10000000	/* transmit clock invert */
#define SCC_GSMRL_EDGE		0x60000000	/* adjustment edge +/- */

#define SCC_GSMRH_RSYN		0x00000001	/* receive sync timing*/
#define SCC_GSMRH_RTSM		0x00000002	/* RTS* mode */
#define SCC_GSMRH_SYNL		0x0000000c	/* sync length */
#define SCC_GSMRH_TXSY		0x00000010	/* transmitter/receiver sync */
#define SCC_GSMRH_RFW		0x00000020	/* Rx FIFO width */
#define SCC_GSMRH_TFL		0x00000040	/* transmit FIFO length */
#define SCC_GSMRH_CTSS		0x00000080	/* CTS* sampling */
#define SCC_GSMRH_CDS		0x00000100	/* CD* sampling */
#define SCC_GSMRH_CTSP		0x00000200	/* CTS* pulse */
#define SCC_GSMRH_CDP		0x00000400	/* CD* pulse */
#define SCC_GSMRH_TTX		0x00000800	/* transparent transmitter */
#define SCC_GSMRH_TRX		0x00001000	/* transparent receiver */
#define SCC_GSMRH_REVD		0x00002000	/* reverse data */
#define SCC_GSMRH_TCRC		0x0000c000	/* transparent CRC */
#define SCC_GSMRH_GDE		0x00010000	/* glitch detect enable */

/* SCC UART protocol specific parameters */

typedef struct		/* SCC_UART_PROTO */
    {
    UINT32	res1;			/* reserved */
    UINT32	res2;			/* reserved */
    UINT16	maxIdl;			/* maximum idle characters */
    UINT16	idlc;			/* temporary idle counter */
    UINT16	brkcr;			/* break count register (transmit) */
    UINT16	parec;			/* receive parity error counter */
    UINT16	frmer;			/* receive framing error counter */
    UINT16	nosec;			/* receive noise counter */
    UINT16	brkec;			/* receive break condition counter */
    UINT16	brkln;			/* last received break length */
    UINT16	uaddr1;			/* uart address character 1 */
    UINT16	uaddr2;			/* uart address character 2 */
    UINT16	rtemp;			/* temp storage */
    UINT16	toseq;			/* transmit out-of-sequence character */
    UINT16	character1;		/* control character 1 */