m68360.h

IXP425的BSP代码

/* SIRAM fields */

#define	SI_SWTR			0x4000
#define	SI_SSEL4		0x2000
#define	SI_SSEL3		0x1000
#define	SI_SSEL2		0x0800
#define	SI_SSEL1		0x0400
#define	SI_CSEL_NS1		0x0000
#define	SI_CSEL_SCC1		0x0040
#define	SI_CSEL_SCC2		0x0080
#define	SI_CSEL_SCC3		0x00C0
#define	SI_CSEL_SCC4		0x0100
#define	SI_CSEL_SMC1		0x0140
#define	SI_CSEL_SMC2		0x0180
#define	SI_CSEL_NS2		0x01C0
#define	SI_CNT_1		0x0000
#define	SI_CNT_2		0x0004
#define	SI_CNT_3		0x0008
#define	SI_CNT_4		0x000C
#define	SI_CNT_5		0x0010
#define	SI_CNT_6		0x0014
#define	SI_CNT_7		0x0018
#define	SI_CNT_8		0x001C
#define	SI_CNT_9		0x0020
#define	SI_CNT_10		0x0024
#define	SI_CNT_11		0x0028
#define	SI_CNT_12		0x002C
#define	SI_CNT_13		0x0030
#define	SI_CNT_14		0x0034
#define	SI_CNT_15		0x0038
#define	SI_CNT_16		0x003C
#define SI_BYT			0x0002
#define	SI_LST			0x0001

/* SIM - System Integration Module */

/* SIM Module Configuration Register definitions */

#define SIM_MCR_IARB_OFF	0x00000000	/* interrupt arb = off */
#define SIM_MCR_IARB_LO		0x00000001	/* interrupt arb = 0x1 */
#define SIM_MCR_IARB_HI		0x0000000f	/* interrupt arb = 0xf */
#define SIM_MCR_BCLRISM		0x00000070	/* bus clear in arb ID */
#define SIM_MCR_BCLRIID		0x00000070	/* bus clear int service mask */
#define SIM_MCR_SUPV		0x00000080	/* supervisor/user data space */
#define SIM_MCR_SHEN		0x00000300	/* show cycle enable */
#define SIM_MCR_BCLROID		0x00001c00	/* bus clear out arb ID */
#define SIM_MCR_FRZ0		0x00002000	/* freeze enable - bus mon */
#define SIM_MCR_FRZ1		0x00004000	/* freeze enable - SWE & PIT */
#define SIM_MCR_ASTM		0x00008000	/* arb synch timing mode */
#define SIM_MCR_BSTM		0x00010000	/* bus synch timing mode */
#define SIM_MCR_BR040ID		0xe0000000	/* bus request 68040 arb ID */

/* SIM Clock Out Control Register definitions */

#define SIM_CLKOCR_COM1_FULL	0x00		/* CLKO1 full strength output */
#define SIM_CLKOCR_COM1_TWO	0x01		/* CLKO1 two thirds strength */
#define SIM_CLKOCR_COM1_ONE	0x02		/* CLKO1 one third strength */
#define SIM_CLKOCR_COM1_DIS	0x03		/* CLKO1 disabled */
#define SIM_CLKOCR_COM2_FULL	0x00		/* CLKO2 full strength output */
#define SIM_CLKOCR_COM2_TWO	0x04		/* CLKO2 two thirds strength */
#define SIM_CLKOCR_COM2_ONE	0x08		/* CLKO2 one third strength */
#define SIM_CLKOCR_COM2_DIS	0x0c		/* CLKO2 disabled */
#define SIM_CLKOCR_RSTEN	0x20		/* loss of lock causes reset */
#define SIM_CLKOCR_CLKOWP	0x80		/* CLKOCR write protect */

/* SIM PLL Control Register definitions */

#define SIM_PLLCR_MF		0x0fff		/* multiplication factor */
#define SIM_PLLCR_STSIM		0x1000		/* stop mode - VCO drives SIM */
#define SIM_PLLCR_PREEN		0x2000		/* prescaller enable */
#define SIM_PLLCR_PLLWP		0x4000		/* PLLCR write protect */
#define SIM_PLLCR_PLLEN		0x8000		/* PLL enable */

/* SIM Clock Divider Control Register defintions */

#define SIM_CDVCR_CSRC		0x0001		/* high/low freq system clk */
#define SIM_CDVCR_DFNH_1	0x0000		/* divide high freq clk by 1 */
#define SIM_CDVCR_DFNH_2	0x0002		/* divide high freq clk by 2 */
#define SIM_CDVCR_DFNH_4	0x0004		/* divide high freq clk by 4 */
#define SIM_CDVCR_DFNH_8	0x0006		/* divide high freq clk by 8 */
#define SIM_CDVCR_DFNH_16	0x0008		/* divide high freq clk by 16 */
#define SIM_CDVCR_DFNH_32	0x000a		/* divide high freq clk by 32 */
#define SIM_CDVCR_DFNH_64	0x000c		/* divide high freq clk by 64 */
#define SIM_CDVCR_DFNL_2	0x0000		/* divide low freq clk by 2 */
#define SIM_CDVCR_DFNL_4	0x0010		/* divide low freq clk by 4 */
#define SIM_CDVCR_DFNL_8	0x0020		/* divide low freq clk by 8 */
#define SIM_CDVCR_DFNL_16	0x0030		/* divide low freq clk by 16 */
#define SIM_CDVCR_DFNL_32	0x0040		/* divide low freq clk by 32 */
#define SIM_CDVCR_DFNL_64	0x0050		/* divide low freq clk by 64 */
#define SIM_CDVCR_DFNL_256	0x0070		/* divide low freq clk by 256 */
#define SIM_CDVCR_RRQEN		0x0080		/* RISC idle -> high freq clk */
#define SIM_CDVCR_INTEN		0x0700		/* interrupt -> high freq clk */
#define SIM_CDVCR_DFTM_1	0x0000		/* divide BRGCLK by 1 - norm */
#define SIM_CDVCR_DFTM_4	0x0800		/* divide BRGCLK by 4 */
#define SIM_CDVCR_DFTM_16	0x1000		/* divide BRGCLK by 16 */
#define SIM_CDVCR_DFTM_64	0x1800		/* divide BRGCLK by 64 */
#define SIM_CDVCR_DFSY_1	0x0000		/* divide SyncClk by 1 - norm */
#define SIM_CDVCR_DFSY_4	0x2000		/* divide SyncClk by 4 */
#define SIM_CDVCR_DFSY_16	0x4000		/* divide SyncClk by 16 */
#define SIM_CDVCR_DFSY_64	0x6000		/* divide SyncClk by 64 */
#define SIM_CDVCR_CDVWP		0x8000		/* CDVCR write protect */

/* SIM Auto Vector Register definitions */

#define SIM_AVR_LVL1		0x02		/* auto vector on IRQ1 */
#define SIM_AVR_LVL2		0x04		/* auto vector on IRQ2 */
#define SIM_AVR_LVL3		0x08		/* auto vector on IRQ3 */
#define SIM_AVR_LVL4		0x10		/* auto vector on IRQ4 */
#define SIM_AVR_LVL5		0x20		/* auto vector on IRQ5 */
#define SIM_AVR_LVL6		0x40		/* auto vector on IRQ6 */
#define SIM_AVR_LVL7		0x80		/* auto vector on IRQ7 */

/* SIM Based Interrupt Autovector addresses */

#define INT_VEC_AV1		0x19		/* vector location of AV1 */
#define INT_VEC_AV2		0x1a		/* vector location of AV2 */
#define INT_VEC_AV3		0x1b		/* vector location of AV3 */
#define INT_VEC_AV4		0x1c		/* vector location of AV4 */
#define INT_VEC_AV5		0x1d		/* vector location of AV5 */
#define INT_VEC_AV6		0x1e		/* vector location of AV6 */
#define INT_VEC_AV7		0x1f		/* vector location of AV7 */

/* SIM Reset Status Register definitions */

#define SIM_RSR_SRSTP		0x01		/* soft reset pin */
#define SIM_RSR_SRST		0x02		/* soft reset */
#define SIM_RSR_LOC		0x04		/* loss of clock reset */
#define SIM_RSR_DBF		0x10		/* double bus fault reset */
#define SIM_RSR_SW		0x20		/* software watchdog reset */
#define SIM_RSR_POW		0x40		/* power up reset */
#define SIM_RSR_EXT		0x80		/* external reset */

/* SIM System Protection Control Register definitions (write once only) */

#define SIM_SYPCR_BMT_1024	0x00		/* 1024 clk monitor timeout */
#define SIM_SYPCR_BMT_512	0x01		/* 512 clk monitor timeout */
#define SIM_SYPCR_BMT_256	0x02		/* 256 clk monitor timeout */
#define SIM_SYPCR_BMT_128	0x03		/* 128 clk monitor timeout */
#define SIM_SYPCR_BME		0x04		/* bus monitor enable */
#define SIM_SYPCR_DBFE		0x08		/* double bus fault enable */
#define SIM_SYPCR_SWT_9		0x00		/* 2^9  clk cycles (SWP=0) */
#define SIM_SYPCR_SWT_11 	0x10		/* 2^11 clk cycles (SWP=0) */
#define SIM_SYPCR_SWT_13	0x20		/* 2^13 clk cycles (SWP=0) */
#define SIM_SYPCR_SWT_15	0x30		/* 2^15 clk cycles (SWP=0) */
#define SIM_SYPCR_SWT_18	0x00		/* 2^18 clk cycles (SWP=1) */
#define SIM_SYPCR_SWT_20	0x10		/* 2^20 clk cycles (SWP=1) */
#define SIM_SYPCR_SWT_22	0x20		/* 2^22 clk cycles (SWP=1) */
#define SIM_SYPCR_SWT_24	0x30		/* 2^24 clk cycles (SWP=1) */
#define SIM_SYPCR_SWRI		0x40		/* soft watchdog resets CPU */
#define SIM_SYPCR_SWE		0x80		/* soft watchdog enable */

/* SIM Periodic Interrupt Control Register definitions */

#define SIM_PICR_PIV		0x00ff		/* PIT int vector */
#define SIM_PICR_PIRQL		0x0700		/* PIT int request level */

/* SIM Periodic Interrupt Timer Register definitions */

#define SIM_PITR_PITR_CNT	0x00ff		/* PIT counter register */
#define SIM_PITR_PTP		0x0100		/* PIT prescale bit */
#define SIM_PITR_SWP		0x0200		/* soft watchdog prescale bit */

/* SIM Software Watchdog Service Register definitions */

#define SIM_SWSR_ACK1		0x55		/* software watchdog ack. 1 */
#define SIM_SWSR_ACK2		0xaa		/* software watchdog ack. 2 */

/* EBI - External Bus Interface */

/* EBI Port E Pin Assignment Register definitions */

#define EBI_PEPAR_IACK5		0x0001		/* select IACK5* output func */
#define EBI_PEPAR_IACK7		0x0002		/* select IACK7* output func */
#define EBI_PEPAR_IACK1_2	0x0004		/* select IACK1,2 output func */
#define EBI_PEPAR_IACK3_6	0x0010		/* select IACK3,6 output func */
#define EBI_PEPAR_PWW		0x0020		/* PEPAR was written */
#define EBI_PEPAR_AMUX		0x0040		/* select AMUX output func */
#define EBI_PEPAR_WE		0x0080		/* select WE* output function */
#define EBI_PEPAR_RAS1DD	0x0100		/* select RAS1DD* output func */
#define EBI_PEPAR_CF1MODE	0x0600		/* CONFIG1/BCLRO*/RAS2DD* */
#define EBI_PEPAR_SINTOUT	0x7000		/* slave interrupt out mode */

/* MEMC - Memory Controller */

/* MEMC Global Memory Register definitions */

#define MEMC_GMR_GMAX		0x00000020	/* global address mux enable */
#define MEMC_GMR_DW40		0x00000040	/* delay write for 68EC040 */
#define MEMC_GMR_DWQ		0x00000080	/* delay write for QUICC */
#define MEMC_GMR_NCS		0x00000100	/* suppress CS/RAS on CPU sp. */
#define MEMC_GMR_TSS40		0x00000200	/* TS* sample for 68EC040 */
#define MEMC_GMR_PBEE		0x00000400	/* parity bus error enable */
#define MEMC_GMR_OPAR		0x00000800	/* odd/even parity */
#define MEMC_GMR_EMWS		0x00001000	/* external master wait state */
#define MEMC_GMR_SYNC		0x00002000	/* synch external accesses */
#define MEMC_GMR_WBTQ		0x00004000	/* wait between QUICC trans */
#define MEMC_GMR_WBT40		0x00008000	/* wait between 68EC040 trans */
#define MEMC_GMR_DPS_32		0x00000000	/* DRAM port size is 32 bits */
#define MEMC_GMR_DPS_16		0x00010000	/* DRAM port size is 16 bits */
#define MEMC_GMR_DPS_EX		0x00030000	/* external DSACK* support */
#define MEMC_GMR_PGS_128K	0x00000000	/* page size is 128Kbytes */
#define MEMC_GMR_PGS_256K	0x00040000	/* page size is 256Kbytes */
#define MEMC_GMR_PGS_512K	0x00080000	/* page size is 512Kbytes */
#define MEMC_GMR_PGS_1M		0x000c0000	/* page size is 1Mbytes */
#define MEMC_GMR_PGS_2M		0x00100000	/* page size is 2Mbytes */
#define MEMC_GMR_PGS_4M		0x00140000	/* page size is 4Mbytes */
#define MEMC_GMR_PGS_8M		0x00180000	/* page size is 8Mbytes */
#define MEMC_GMR_PGS_16M	0x001c0000	/* page size is 16Mbytes */
#define MEMC_GMR_RCYC_4		0x00000000	/* refresh cycle 4 clocks */
#define MEMC_GMR_RCYC_6		0x00200000	/* refresh cycle 6 clocks */
#define MEMC_GMR_RCYC_7		0x00400000	/* refresh cycle 7 clocks */
#define MEMC_GMR_RCYC_8		0x00600000	/* refresh cycle 8 clocks */
#define MEMC_GMR_RFEN		0x00800000	/* refresh enable */
#define MEMC_GMR_RCNT		0xff000000	/* refresh counter period */

/* MEMC Status Register definitions */

#define MEMC_MSTAT_PER1		0x0001		/* write protect err - bank 1 */
#define MEMC_MSTAT_PER2		0x0002		/* write protect err - bank 2 */
#define MEMC_MSTAT_PER3		0x0004		/* write protect err - bank 3 */
#define MEMC_MSTAT_PER4		0x0008		/* write protect err - bank 4 */
#define MEMC_MSTAT_PER5		0x0010		/* write protect err - bank 5 */
#define MEMC_MSTAT_PER6		0x0020		/* write protect err - bank 6 */
#define MEMC_MSTAT_PER7		0x0040		/* write protect err - bank 7 */
#define MEMC_MSTAT_PER8		0x0080		/* write protect err - bank 8 */
#define MEMC_MSTAT_WPER		0x0100		/* write protect error */

/* MEMC Base Register definitions */

#define MEMC_BR_V		0x00000001	/* DRAM/SRAM bank is valid */
#define MEMC_BR_WP		0x00000002	/* write protect */
#define MEMC_BR_PAREN		0x00000004	/* parity checking enable */
#define MEMC_BR_CSNTQ		0x00000008	/* CS negate timing - QUICC */
#define MEMC_BR_CSNT40		0x00000010	/* CS negate timing - 68EC040 */
#define MEMC_BR_BACK40		0x00000020	/* burst acknowledge 68EC040 */
#define MEMC_BR_TRLXQ		0x00000040	/* timing relax */
#define MEMC_BR_FC		0x00000780	/* function code spec */
#define MEMC_BR_BA		0xfffff800	/* base address spec */

/* MEMC Option Register definitions */

#define MEMC_OR_DSSEL		0x00000001	/* DRAM/SRAM select */
#define MEMC_OR_SPS_32		0x00000000	/* SRAM port size is 32 bits */
#define MEMC_OR_SPS_16		0x00000002	/* SRAM port size is 16 bits */
#define MEMC_OR_SPS_8		0x00000004	/* SRAM port size is 8 bits */
#define MEMC_OR_SPS_EX		0x00000006	/* external DSACK* support */
#define MEMC_OR_PGME		0x00000008	/* page mode enable (DRAM) */
#define MEMC_OR_BCYC_1		0x00000000	/* burst cycle 1 clock */
#define MEMC_OR_BCYC_2		0x00000020	/* burst cycle 2 clock */
#define MEMC_OR_BCYC_3		0x00000040	/* burst cycle 3 clock */
#define MEMC_OR_BCYC_4		0x00000060	/* burst cycle 4 clock */
#define MEMC_OR_FC		0x00000780	/* function code mask */
#define MEMC_OR_AM		0x0ffff800	/* addresss mask */
#define MEMC_OR_TCYC		0xf0000000	/* bus cycle length in clocks */

/*** CPM - register definitions for the Communication Processor Module ***/

/* CPM - Communication Processor Module */

/* CPM Configuration Register definitions */

#define CPM_CR_FLG		0x0001		/* flag - command executing */
#define CPM_CR_CHANNEL_SCC1	0x0000		/* SCC1 channel */
#define CPM_CR_CHANNEL_SCC2	0x0040		/* SCC2 channel */
#define CPM_CR_CHANNEL_SPI	0x0050		/* SPI channel */
#define CPM_CR_CHANNEL_RTMR	0x0050		/* RISC timer channel */
#define CPM_CR_CHANNEL_SCC3	0x0080		/* SCC3 channel */
#define CPM_CR_CHANNEL_SMC1	0x0090		/* SMC1 channel */
#define CPM_CR_CHANNEL_IDMA1	0x0090		/* IDMA1 channel */
#define CPM_CR_CHANNEL_SCC4	0x00c0		/* SCC4 channel */
#define CPM_CR_CHANNEL_SMC2	0x00d0		/* SMC2 channel */
#define CPM_CR_CHANNEL_IDMA2	0x00d0		/* IDMA2 channel */
#define CPM_CR_OPCODE		0x0f00		/* command opcode */

#define CPM_CR_SCC_INIT_RT	0x0000		/* initialize SCC rx and tx*/
#define CPM_CR_SCC_INIT_R	0x0100		/* initialize SCC rx only */
#define CPM_CR_SCC_INIT_T	0x0200		/* initialize SCC tx only */
#define CPM_CR_SCC_HUNT		0x0300		/* enter rx frame hunt mode */
#define CPM_CR_SCC_STOP		0x0400		/* stop SCC tx */
#define CPM_CR_SCC_GRSTOP	0x0500		/* gracefully stop SCC tx */
#define CPM_CR_SCC_RESTART	0x0600		/* restart SCC tx */
#define CPM_CR_SCC_CLOSE	0x0700		/* close SCC rx buffer */
#define CPM_CR_SCC_SET_GROUP	0x0800		/* set SCC group address */
#define CPM_CR_SCC_RESET_BCS	0x0a00		/* reset bisync seq calc */

#define CPM_CR_RST		0x8000		/* software reset command */

/* CPIC - CPM Interrupt Controller */

/* CPM Interrupt Configuration Register definitions */

#define CPIC_CICR_SPS		0x00000001	/* spread SCC priority scheme */
#define CPIC_CICR_VBA		0x000000e0	/* vector base address */
#define CPIC_CICR_HP		0x00001f00	/* highest priority source */
#define CPIC_CICR_IRL		0x0000e000	/* interrupt request level */
#define CPIC_CICR_SCaP_1	0x00000000	/* SCCa will be used by SCC1 */
#define CPIC_CICR_SCaP_2	0x00010000	/* SCCa will be used by SCC2 */
#define CPIC_CICR_SCaP_3	0x00020000	/* SCCa will be used by SCC3 */
#define CPIC_CICR_SCaP_4	0x00030000	/* SCCa will be used by SCC4 */
#define CPIC_CICR_SCbP_1	0x00000000	/* SCCb will be used by SCC1 */
#define CPIC_CICR_SCbP_2	0x00040000	/* SCCb will be used by SCC2 */
#define CPIC_CICR_SCbP_3	0x00080000	/* SCCb will be used by SCC3 */