m68360.h

IXP425的BSP代码

/* m68360.h - Motorola MC68360 CPU control registers */

/* Copyright 1994-1996 Wind River Systems, Inc. */

/*
modification history
--------------------
01e,05dec96,db	 fixed macro M360_DPR_TMR per SPR #7575.
01d,28may96,dat  fixed SPR #5616, new macros for SMC in GCI mode
01c,24jan94,dzb  fixed size of M360_CPM_GSMR_L3, M360_CPM_PSMR3, M360_CPM_PCINT.
01b,05oct93,dzb  added ethernet macros.  broke out CPM interrupt vectors.
		 added SCC_DEV abstraction.  added CPM command macros.
01a,04aug93,dzb  written.
*/

/*
This file contains I/O addresses and related constants for the MC68360.
*/

#ifndef __INCm68360h
#define __INCm68360h

#ifdef __cplusplus
extern "C" {
#endif

#ifndef	_ASMLANGUAGE

#ifndef	INCLUDE_TY_CO_DRV_50
#include "tyLib.h"
#endif	/* INCLUDE_TY_CO_DRV_50 */

/* MC68360 Module Base Address Register fixed locations */

#define M360_SIM_MBAR		0x0003ff00  /* master base address register */
#define M360_SIM_MBAR_SLAVE	0x0003ff04  /* slave base address register */
#define M360_SIM_MBARE		0x0003ff08  /* slave MBAR enable address */

/* MC68360 Dual Ported Ram addresses */

#define M360_DPR_SCC1(base)	((UINT32 *) (base + 0xc00))
#define M360_DPR_MISC(base)	((UINT32 *) (base + 0xcb0))
#define M360_DPR_SCC2(base)	((UINT32 *) (base + 0xd00))
#define M360_DPR_TMR(base)	((UINT32 *) (base + 0xdb0))
#define M360_DPR_SPI(base)	((UINT32 *) (base + 0xd80))
#define M360_DPR_SCC3(base)	((UINT32 *) (base + 0xe00))
#define M360_DPR_IDMA1(base)	((UINT32 *) (base + 0xe70))
#define M360_DPR_SMC1(base)	((UINT32 *) (base + 0xe80))
#define M360_DPR_SCC4(base)	((UINT32 *) (base + 0xf00))
#define M360_DPR_IDMA2(base)	((UINT32 *) (base + 0xf70))
#define M360_DPR_SMC2(base)	((UINT32 *) (base + 0xf80))

/* GCI MODE Buffer Descriptors */

#define	M360_SMC1_M_RXBD(base)	((UINT16 *) (base + 0x0E80))
#define	M360_SMC1_M_TXBD(base)	((UINT16 *) (base + 0x0E82))
#define	M360_SMC1_CI_RXBD(base) ((UINT16 *) (base + 0x0E84))
#define	M360_SMC1_CI_TXBD(base) ((UINT16 *) (base + 0x0E86))

#define	M360_SMC2_M_RXBD(base)	((UINT16 *) (base + 0x0F80))
#define	M360_SMC2_M_TXBD(base)	((UINT16 *) (base + 0x0F82))
#define	M360_SMC2_CI_RXBD(base) ((UINT16 *) (base + 0x0F84))
#define	M360_SMC2_CI_TXBD(base) ((UINT16 *) (base + 0x0F86))

/* MC68360 register addresses in parameter ram */

#define M360_REGB_OFFSET	0x1000	/* offset to internal registers */

/* System Integration Module register addresses */

#define M360_SIM_MCR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x000))
#define M360_SIM_AVR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x008))
#define M360_SIM_RSR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x009))
#define M360_SIM_CLKOCR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x00c))
#define M360_SIM_PLLCR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x010))
#define M360_SIM_CDVCR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x014))
#define M360_SIM_PEPAR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x016))
#define M360_SIM_SYPCR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x022))
#define M360_SIM_SWIV(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x023))
#define M360_SIM_PICR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x026))
#define M360_SIM_PITR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x02a))
#define M360_SIM_SWSR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x02f))
#define M360_SIM_BKAR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x030))
#define M360_SIM_BKCR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x034))
#define M360_SIM_GMR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x040))
#define M360_SIM_MSTAT(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x044))
#define M360_SIM_BR0(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x050))
#define M360_SIM_OR0(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x054))
#define M360_SIM_BR1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x060))
#define M360_SIM_OR1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x064))
#define M360_SIM_BR2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x070))
#define M360_SIM_OR2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x074))
#define M360_SIM_BR3(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x080))
#define M360_SIM_OR3(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x084))
#define M360_SIM_BR4(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x090))
#define M360_SIM_OR4(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x094))
#define M360_SIM_BR5(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x0a0))
#define M360_SIM_OR5(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x0a4))
#define M360_SIM_BR6(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x0b0))
#define M360_SIM_OR6(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x0b4))
#define M360_SIM_BR7(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x0c0))
#define M360_SIM_OR7(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x0c4))

/* Communication Processor Module register addresses */

#define M360_CPM_ICCR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x500))
#define M360_CPM_CMR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x504))
#define M360_CPM_SAPR1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x508))
#define M360_CPM_DAPR1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x50c))
#define M360_CPM_BCR1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x510))
#define M360_CPM_FCR1(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x514))
#define M360_CPM_CMAR1(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x516))
#define M360_CPM_CSR1(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x518))
#define M360_CPM_SDSR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x51c))
#define M360_CPM_SDCR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x51e))
#define M360_CPM_SDAR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x520))
#define M360_CPM_CMR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x526))
#define M360_CPM_SAPR2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x528))
#define M360_CPM_DAPR2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x52c))
#define M360_CPM_BCR2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x530))
#define M360_CPM_FCR2(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x534))
#define M360_CPM_CMAR2(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x536))
#define M360_CPM_CSR2(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x538))
#define M360_CPM_CICR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x540))
#define M360_CPM_CIPR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x544))
#define M360_CPM_CIMR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x548))
#define M360_CPM_CISR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x54c))
#define M360_CPM_PADIR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x550))
#define M360_CPM_PAPAR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x552))
#define M360_CPM_PAODR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x554))
#define M360_CPM_PADAT(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x556))
#define M360_CPM_PCDIR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x560))
#define M360_CPM_PCPAR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x562))
#define M360_CPM_PCSO(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x564))
#define M360_CPM_PCDAT(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x566))
#define M360_CPM_PCINT(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x568))
#define M360_CPM_TGCR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x580))
#define M360_CPM_TMR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x590))
#define M360_CPM_TMR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x592))
#define M360_CPM_TRR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x594))
#define M360_CPM_TRR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x596))
#define M360_CPM_TCR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x598))
#define M360_CPM_TCR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x59a))
#define M360_CPM_TCN1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x59c))
#define M360_CPM_TCN2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x59e))
#define M360_CPM_TMR3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5a0))
#define M360_CPM_TMR4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5a2))
#define M360_CPM_TRR3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5a4))
#define M360_CPM_TRR4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5a6))
#define M360_CPM_TCR3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5a8))
#define M360_CPM_TCR4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5aa))
#define M360_CPM_TCN3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5ac))
#define M360_CPM_TCN4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5ae))
#define M360_CPM_TER1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5b0))
#define M360_CPM_TER2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5b2))
#define M360_CPM_TER3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5b4))
#define M360_CPM_TER4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5b6))
#define M360_CPM_CR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5c0))
#define M360_CPM_RCCR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5c4))
#define M360_CPM_RTER(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5d6))
#define M360_CPM_RTMR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x5da))
#define M360_CPM_BRGC1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x5f0))
#define M360_CPM_BRGC2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x5f4))
#define M360_CPM_BRGC3(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x5f8))
#define M360_CPM_BRGC4(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x5fc))
#define M360_CPM_GSMR_L1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x600))
#define M360_CPM_GSMR_H1(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x604))
#define M360_CPM_PSMR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x608))
#define M360_CPM_TODR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x60c))
#define M360_CPM_DSR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x60e))
#define M360_CPM_SCCE1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x610))
#define M360_CPM_SCCM1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x614))
#define M360_CPM_SCCS1(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x617))
#define M360_CPM_GSMR_L2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x620))
#define M360_CPM_GSMR_H2(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x624))
#define M360_CPM_PSMR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x628))
#define M360_CPM_TODR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x62c))
#define M360_CPM_DSR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x62e))
#define M360_CPM_SCCE2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x630))
#define M360_CPM_SCCM2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x634))
#define M360_CPM_SCCS2(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x637))
#define M360_CPM_GSMR_L3(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x640))
#define M360_CPM_GSMR_H3(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x644))
#define M360_CPM_PSMR3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x648))
#define M360_CPM_TODR3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x64c))
#define M360_CPM_DSR3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x64e))
#define M360_CPM_SCCE3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x650))
#define M360_CPM_SCCM3(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x654))
#define M360_CPM_SCCS3(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x657))
#define M360_CPM_GSMR_L4(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x660))
#define M360_CPM_GSMR_H4(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x664))
#define M360_CPM_PSMR4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x668))
#define M360_CPM_TODR4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x66c))
#define M360_CPM_DSR4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x66e))
#define M360_CPM_SCCE4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x670))
#define M360_CPM_SCCM4(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x674))
#define M360_CPM_SCCS4(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x677))
#define M360_CPM_SMCMR1(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x682))
#define M360_CPM_SMCE1(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x686))
#define M360_CPM_SMCM1(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x68a))
#define M360_CPM_SMCMR2(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x692))
#define M360_CPM_SMCE2(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x696))
#define M360_CPM_SMCM2(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x69a))
#define M360_CPM_SPMODE(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x6a0))
#define M360_CPM_SPIE(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x6a6))
#define M360_CPM_SPIM(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x6aa))
#define M360_CPM_SPCOM(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x6ad))
#define M360_CPM_PIPC(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x6b2))
#define M360_CPM_PTPR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x6b6))
#define M360_CPM_PBDIR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x6b8))
#define M360_CPM_PBPAR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x6bc))
#define M360_CPM_PBODR(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x6c2))
#define M360_CPM_PBDAT(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x6c4))
#define M360_CPM_SIMODE(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x6e0))
#define M360_CPM_SIGMR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x6e4))
#define M360_CPM_SISTR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x6e6))
#define M360_CPM_SICMR(base)	((UINT8  *) (base + M360_REGB_OFFSET + 0x6e7))
#define M360_CPM_SICR(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x6ec))
#define M360_CPM_SIRP(base)	((UINT32 *) (base + M360_REGB_OFFSET + 0x6f2))
#define M360_CPM_SIRAM(base)	((UINT16 *) (base + M360_REGB_OFFSET + 0x700))

/* SMC GCI Monitor Channel Receive Buffer Descriptor */

#define	SMC_GCI_MON_RXBD_E	0x8000
#define	SMC_GCI_MON_RXBD_L	0x4000
#define	SMC_GCI_MON_RXBD_ER	0x2000
#define	SMC_GCI_MON_RXBD_MS	0x1000
#define	SMC_GCI_MON_RXBD_AB	0x0200
#define	SMC_GCI_MON_RXBD_EB	0x0100

/* SMC GCI  Monitor Channel Transmit Buffer Descriptor */

#define	SMC_GCI_MON_TXBD_R	0x8000
#define	SMC_GCI_MON_TXBD_L	0x4000
#define	SMC_GCI_MON_TXBD_AR	0x2000
#define	SMC_GCI_MON_TXBD_MS	0x1000
#define	SMC_GCI_MON_TXBD_AB	0x0200
#define	SMC_GCI_MON_TXBD_EB	0x0100

/* SMC GCI C/I Channel Receive Buffer Descriptor */

#define	SMC_GCI_CI_RXBD_E	0x8000
#define SMC_GCI_CI_DATA_MASK	0x003F

/* SMC GCI  C/I Channel Transmit Buffer Descriptor */

#define	SMC_GCI_CI_TXBD_R	0x8000

/* SMC GCI Event and Mask Register definitions */

#define	SMC_GCI_SMCX_CTXB	0x08
#define	SMC_GCI_SMCX_CRXB	0x04
#define	SMC_GCI_SMCX_MTXB	0x02
#define	SMC_GCI_SMCX_MRXB	0x01

/* SMC MODE Register fields in GCI MODE */

#define	SMC_SMCMR_CLEN_1	0x0000
#define	SMC_SMCMR_CLEN_2	0x0800
#define	SMC_SMCMR_CLEN_3	0x1000
#define	SMC_SMCMR_CLEN_4	0x1800
#define	SMC_SMCMR_CLEN_5	0x2000
#define	SMC_SMCMR_CLEN_6	0x2800
#define	SMC_SMCMR_CLEN_7	0x3000
#define	SMC_SMCMR_CLEN_8	0x3800
#define	SMC_SMCMR_CLEN_9	0x4000
#define	SMC_SMCMR_CLEN_10	0x4800
#define	SMC_SMCMR_CLEN_11	0x5000
#define	SMC_SMCMR_CLEN_12	0x5800
#define	SMC_SMCMR_CLEN_13	0x6000
#define	SMC_SMCMR_CLEN_14	0x6800
#define	SMC_SMCMR_CLEN_15	0x7000
#define	SMC_SMCMR_CLEN_16	0x7800

#define SMC_SMCMR_ME		0x0400
#define SMC_SMCMR_MP		0x0200
#define SMC_SMCMR_CN		0x0100
#define SMC_SMCMR_CHAN1		0x0000
#define SMC_SMCMR_CHAN2		0x0100

#define	SMC_SMCMR_SM_GCI	0x0000
#define	SMC_SMCMR_SM_UART	0x0020
#define	SMC_SMCMR_SM_TRANSPARENT 0x0030

#define	SMC_SMCMR_DM_NORMAL	0x0000
#define	SMC_SMCMR_DM_LCLOOP	0x0004
#define	SMC_SMCMR_DM_ECHO	0x0008

#define	SMC_SMCMR_TEN		0x0002
#define	SMC_SMCMR_REN		0x0001
#define SMC_SMCMR_CRX_ENABLE	0x0004


/* SI GLOBAL MODE register */

#define	SI_SIGMR_ENB		0x08
#define	SI_SIGMR_ENA		0x04
#define	SI_SIGMR_RDM_1CHN_64E	0x00
#define SI_SIGMR_RDM_1CHN_32E	0x01
#define SI_SIGMR_RDM_2CHN_32E	0x02
#define SI_SIGMR_RDM_2CHN_16E	0x03