mpc107.h

IXP425的BSP代码

#define MPC107_ODC_DRV_MEM_CLK_13_3  0x00000002 /* mem clock drive: 13.3-ohms */
#define MPC107_ODC_DRV_MEM_CLK_8     0x00000003 /* mem clock drive: 8-ohms */

/* MPC107 - clock driver control Register */

#define MPC107_CDC_PCI_CLK_0        0x00004000  /* PCI_CLK(0) disable */
#define MPC107_CDC_PCI_CLK_1        0x00002000  /* PCI_CLK(1) disable */
#define MPC107_CDC_PCI_CLK_2        0x00001000  /* PCI_CLK(2) disable */
#define MPC107_CDC_PCI_CLK_3        0x00000800  /* PCI_CLK(3) disable */
#define MPC107_CDC_PCI_CLK_4        0x00000400  /* PCI_CLK(4) disable */
#define MPC107_CDC_SDRAM_CLK_0      0x00000040  /* SDRAM_CLK(0) disable */
#define MPC107_CDC_SDRAM_CLK_1      0x00000020  /* SDRAM_CLK(1) disable */
#define MPC107_CDC_SDRAM_CLK_2      0x00000010  /* SDRAM_CLK(2) disable */
#define MPC107_CDC_SDRAM_CLK_3      0x00000008  /* SDRAM_CLK(3) disable */

/* MPC107 - processor interface configuration #1 Register */

#define MPC107_PIC1_CF_BREAD_WS_MASK  0x00c00000 /* wait states mask */
#define MPC107_PIC1_CF_BREAD_WS_SHIFT 22         /* wait states shift */
#define MPC107_PIC1_RCS0              0x00100000 /* ROM location */
#define MPC107_PIC1_PROC_TYPE_MASK    0x00060000 /* processor type mask */
#define MPC107_PIC1_PROC_TYPE_SHIFT   17         /* processor type shift */
#define MPC107_PIC1_ADDRESS_MAP       0x00010000 /* address map */
#define MPC107_PIC1_FLASH_WR_EN       0x00001000 /* FLASH write enable */
#define MPC107_PIC1_MCP_EN            0x00000800 /* machine check enable */
#define MPC107_PIC1_CF_DPARK          0x00000200 /* processor data bus park */
#define MPC107_PIC1_STORE_GATHER      0x00000040 /* store gathering enable */
#define MPC107_PIC1_ENDIAN_MODE       0x00000020 /* endian mode */
#define MPC107_PIC1_CF_LOOP_SNOOP     0x00000010 /* PCI-to-mem snoop loop en */
#define MPC107_PIC1_CF_APARK          0x00000008 /* processor addr bus park */
#define MPC107_PIC1_SPECULATIVE       0x00000004 /* speculative PCI from */
                                           	 /* memory read enable */

/* MPC107 - processor interface configuration #2 Register */

#define MPC107_PIC2_NO_SER_ON_CFG  0x20000000 /* disable PCI serialization */
#define MPC107_PIC2_NO_SNOOP_EN    0x08000000 /* disable PCI snoop */
#define MPC107_PIC2_CF_FF0_LOCAL   0x04000000 /* ROM PCI address map */
#define MPC107_PIC2_FLSH_WR_LCK_EN 0x02000000 /* disable FLASH writes */
#define MPC107_PIC2_CF_SNOOP_WS_M  0x00c00000 /* snoop addr phase wait state*/
#define MPC107_PIC2_CF_SNOOP_WS_S  18         /* snoop addr wait shift */
#define MPC107_PIC2_CF_APHASE_WS_M 0x0000000c /* proc addr phase wait states*/
#define MPC107_PIC2_CF_APHASE_WS_S 2          /* proc addr phase wait shift */

/* MPC107 - emulation support */

#define MPC107_ES_CPU_FD_ALIAS_EN  0x00000080 /* forward FDxxxxxx to PCI */
#define MPC107_ES_PCI_FD_ALIAS_EN  0x00000040 /* forward FDxxxxxx to CPU */
#define MPC107_ES_DLL_RESET	   0x00000020 /* reset the DLL */
#define MPC107_ES_PCI_COMPAT_HOLE  0x00000008 /* PCI compatibil hole enable */
#define MPC107_ES_PROC_COMPAT_HOLE 0x00000004 /* proc compatibility hole en */

/* MPC107 - error enable #1 Register */

#define MPC107_EE1_PCI_TARG_ABORT   0x00000080  /* PCI target abort */
#define MPC107_EE1_PCI_PERR_SLAVE   0x00000040  /* PCI slace PERR */
#define MPC107_EE1_MEM_SELECT       0x00000020  /* memory select */
#define MPC107_EE1_MEM_REFRESH      0x00000010  /* memory refresh overflow */
#define MPC107_EE1_PCI_PERR_MSTR    0x00000008  /* PCI master PERR */
#define MPC107_EE1_MEM_READ_PARITY  0x00000004  /* memory read parity */
#define MPC107_EE1_PCI_MSTR_ABORT   0x00000002  /* PCI master abort */
#define MPC107_EE1_LOCAL_BUS_ERROR  0x00000001  /* local bus error */

/* MPC107 - error detection #1 Register */

#define MPC107_ED1_SERR            0x00000080 /* SERR_ received */
#define MPC107_ED1_PCI_PERR_SLAVE  0x00000040 /* PCI slace PERR */
#define MPC107_ED1_MEM_SELECT      0x00000020 /* memory select */
#define MPC107_ED1_MEM_REFRESH     0x00000010 /* memory refresh overflow */
#define MPC107_ED1_CYCLE_SPACE     0x00000008 /* cycle type: 0=local, 1=PCI */
#define MPC107_ED1_MEM_READ_PARITY 0x00000004 /* memory read parity */
#define MPC107_ED1_ULBC_MASK       0x00000003 /* unsupported local bus */
					      /* cycle mask */
#define MPC107_ED1_ULBC_NO_ERROR   0x00000000 /* no error detected */
#define MPC107_ED1_ULBC_UTA        0x00000001 /* unsupported transfer */
					      /* attributes */

/* MPC107 - CPU Bus Error Status Register */

#define MPC107_CPU_BUS_ERR_TT_MASK    0x000000f8
#define MPC107_CPU_BUS_ERR_TSIZ_MASK  0x00000007

/* MPC107 - error enable #2 */

#define MPC107_EE2_PCI_ADRS_PARITY  0x00000080 /* PCI address parity error */
#define MPC107_EE2_ECC_MULTIBIT     0x00000008 /* ECC multi-bit error */
#define MPC107_EE2_60X_MEM_WRITE_P  0x00000004 /* 60X mem write parity error */
#define MPC107_EE2_FLASH_ROM_WRITE  0x00000001 /* Flash ROM write error */

/* MPC107 - error detection #2 Register */

#define MPC107_ED2_IEA              0x00000080 /* invalid error address */
#define MPC107_ED2_ECC_MULTIBIT     0x00000008 /* ECC multi-bit error */
#define MPC107_ED2_60X_MEM_WRITE_P  0x00000004 /* 60X mem write parity error */
#define MPC107_ED2_FLASH_ROM_WRITE  0x00000001 /* Flash ROM write error */

/* MCP107 - PCI Bus Error Status Register */

#define MPC107_CPU_BUS_TARGET	     0x00000010	/* 1=bus target,0=bus master */
#define MPC107_CPU_BUS_ERR_C_BE_MASK 0x0000000f /* Bus Error Status mask */


/* Address MAP B Options register */

#define MPC107_ADMBO_PROC_HOLE   0x00000004 /* Processor compatability hole */
#define MPC107_ADMBO_PCI_HOLE  	0x00000008 /* PCI compatabilty hole */
#define MPC107_ADMBO_PCI_ALIAS   0x00000040 /* PCI alias */
#define MPC107_ADMBO_CPU_ALIAS   0x00000080 /* CPU alias */

#define MPC107_ADMBO_DEFAULT  0x0


/* Default Settings & values  for MPC107 Registers */

#define MPC107_PCICMD_DEFAULT	0x00000006  /* PCI COMMAND Default value */
#define MPC107_PICR1_DEFAULT   	0xff041a18  /* PICR1  setting Flash */
                                            /* writing Enabled */
#define MPC107_PICR2_DEFAULT    0x04040000  /* PICR2  setting with Write */
                                            /* Operations to Flash Enabled */
#define MPC107_FLASH_WRITE_BIT	(0x1 << 12) /* Flash Write Enable Bit */

/* PPC Decrementer - used as vxWorks system clock */

#define MPC107_DELTA(a,b)              (abs((int)a - (int)b))

/* High and low words of bit-mask of read-only bits in PICR1 */

#define MPC107_PICR1_ROBITS_16    0x0011    /* Mask of Readonly bits */
#define MPC107_PICR1_ROBITS_00    0x0000    /* Mask of Readonly bits */
#define MPC107_EUMBBAR_VAL	0x80500000  /* Base address of EUMBBAR Reg */

#define MPC107_PCSRBAR_VAL	0x80500000  /* Base addr of PCRBARVAL Reg */

#define MPC107_ODCR_DATA 	0xff        /* default ODCR data */

#define MPC107_DEFAULT_BUS_CLOCK	33000000    /* 33 Mhz */
#define MPC107_DEFAULT_TIMER_CLOCK	33000000/8  /* 33Mhz /8 */

#ifndef SYNC
# define SYNC  		WRS_ASM ("sync") 
#endif  /* SYNC */


/* Swap of four bytes : ABCD becomes DCBA */

#define MPC107LONGSWAP(x) LONGSWAP(x)

/* Swap of two bytes : AB becomes BA */

#define MPC107WORDSWAP(x) WORDSWAP(x)

/* Macro to read Data from a register in EUMBBAR space */

#define MPC107EUMBBARREAD(regNum)    MPC107LONGSWAP(*(ULONG *) \
                                          (MPC107_EUMBBAR_VAL + regNum))

/* Macro to write Data to a register in EUMBBAR space */

#define MPC107EUMBBARWRITE(regNum,regVal) \
             *(ULONG *)(MPC107_EUMBBAR_VAL + regNum) = MPC107LONGSWAP(regVal)

/* Macro to read Data from a register in PCSRBAR space */

#define  MPC107EUMBBARREAD(regNum)    MPC107LONGSWAP(*(ULONG *) \
                                                 (MPC107_EUMBBAR_VAL + regNum))

/* Macro to write Data to a register in PCSRBAR space */

#define MPC107PCSRBARWRITE(regNum,regVal)  \
             *(ULONG *) (PCSRBAR_VAL + regNum) = MPC107LONGSWAP(regVal)

#ifdef __cplusplus
}
#endif

#endif	/* __INCmpc107h */