📄 nvr4121.h

📁 IXP425的BSP代码
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/* nvr4121.h - NEC NVR4121 header file *//* Copyright 1984-1997 Wind River Systems, Inc. *//*modification history--------------------01c,14oct99,jmw  fix RTC reg VR4121_ECMPHREG address01b,07oct99,jmw  add vr4102 RTC and new BCU registers01a,23aug99,jmw  created from nvr4102.h for vr4121 bsp*//*This file contains constants for the NEC V4R4101.  Register addressdefinitions for the various subsystems are provided, and some (butnot all) register field definitions are provided.*/#ifndef __INCnvr4121h#define __INCnvr4121h#include "vxWorks.h"#ifdef __cplusplusextern "C" {#endif#define VR4121_ICACHE_SIZE	16384#define VR4121_DCACHE_SIZE	8192#define VR4121_ISA_IO_BASE_ADRS PHYS_TO_K1(0x15000000)   /* vr4121 SDB    *//* interrupt bits in the status register */#define VR4121_SR_ICU_INTERVAL_TIMER  (1 << 11)#define VR4121_SR_ICU_OTHER	      (1 << 10)/* VR4121 register definitions. */#define VR4121_REG_BASE   (0x0b000000 | K1BASE)#ifdef	_ASMLANGUAGE#define VR4121_ADRS(reg)   (VR4121_REG_BASE + (reg))#else#define VR4121_ADRS(reg)   ((volatile UINT16 *)(VR4121_REG_BASE + (reg)))#endif	/* _ASMLANGUAGE *//* BCU registers */#define VR4121_BCUCNTREG1	VR4121_ADRS(0x00)#define VR4121_BCUCNTREG2	VR4121_ADRS(0x02)#define VR4121_ROMSIZEREG	VR4121_ADRS(0x04)  /* new */#define VR4121_RAMSIZEREG	VR4121_ADRS(0x06)  /* new */#define VR4121_BCUSPEEDREG	VR4121_ADRS(0x0a)#define VR4121_BCUERRSTREG	VR4121_ADRS(0x0c)#define VR4121_BCURFCNTREG	VR4121_ADRS(0x0e)#define VR4121_REVIDREG		VR4121_ADRS(0x10)#define VR4121_BCURCOUNTRE	VR4121_ADRS(0x12)#define VR4121_CLKSPEEDREG	VR4121_ADRS(0x14)#define VR4121_BCUCNTREG3	VR4121_ADRS(0x16)  /* new */#define VR4121_SDRAMMODEREG	VR4121_ADRS(0x1a)  /* new */#define VR4121_SROMMODEREG	VR4121_ADRS(0x1c)  /* new */#define VR4121_SDRAMCNTREG	VR4121_ADRS(0x1e)  /* new *//* BCUCNTREG1 bit definitions */#define VR4121_ROM64		(1 << 15)#define VR4121_DRAM64		(1 << 14)#define VR4121_ISAM_LCD		(1 << 13)	/* XXX set this? */#define VR4121_PAGE128		(1 << 12)#define VR4121_PAGEROM2		(1 << 10)#define VR4121_PAGEROM0		(1 << 8)#define VR4121_ROMWEN2		(1 << 6)#define VR4121_ROMWEN0		(1 << 4)#define VR4121_BUSHERREN	(1 << 2)#define VR4121_RSTOUT		(1 << 0)/* BCUCNTREG2 bit definitions */#define VR4121_GMODE		(1 << 0)/* DMAAU registers */#define VR4121_AIUBALREG	VR4121_ADRS(0x20)#define VR4121_AIUBAHREG	VR4121_ADRS(0x22)#define VR4121_AIUALREG		VR4121_ADRS(0x24)#define VR4121_AIUAHREG		VR4121_ADRS(0x26)#define VR4121_AIUOBALREG	VR4121_ADRS(0x28)#define VR4121_AIUOBAHREG	VR4121_ADRS(0x2a)#define VR4121_AIUOALREG	VR4121_ADRS(0x2c)#define VR4121_AIUOAHREG	VR4121_ADRS(0x2e)#define VR4121_FIRBALREG	VR4121_ADRS(0x30)#define VR4121_FIRBAHREG	VR4121_ADRS(0x32)#define VR4121_FIRALREG		VR4121_ADRS(0x34)#define VR4121_FIRAHREG		VR4121_ADRS(0x36)/* DCU registers */#define VR4121_DMARSTREG	VR4121_ADRS(0x40)#define VR4121_DMAIDLEREG	VR4121_ADRS(0x42)#define VR4121_DMASENREG	VR4121_ADRS(0x44)#define VR4121_DMAMSKREG	VR4121_ADRS(0x46)#define VR4121_DMAREQREG	VR4121_ADRS(0x48)#define VR4121_TDREG		VR4121_ADRS(0x4a)/* DMA mask bit definitions */#define  VR4121_DMAMSKAIN	(1 << 3)#define  VR4121_DMAMSKAOUT	(1 << 2)#define  VR4121_DMAMSKFOUT	(1 << 0)/* CMU register */#define VR4121_CMUCLKMSK	VR4121_ADRS(0x60)#define  VR4121_MSKFFIR		(1 << 10)#define  VR4121_MSKSHSP		(1 << 9)#define  VR4121_MSKSSIU		(1 << 8)  /* XXX set this */#define  VR4121_MSKDSIU		(1 << 5)  /* XXX set this */#define  VR4121_MSKFIR		(1 << 4)#define  VR4121_MSKKIU		(1 << 3)#define  VR4121_MSKADU		(1 << 2)#define  VR4121_MSKSIU		(1 << 1)  /* XXX set this */#define  VR4121_MSKPIU		(1 << 0)/* ICU system and system mask registers */#define VR4121_ICU_SYSINT1REG  	VR4121_ADRS(0x80)#define VR4121_ICU_MSYSINT1REG	VR4121_ADRS(0x8c)#define  VR4121_DOZEPIUINTR	(1 << 13)#define  VR4121_SOFTINTR	(1 << 11)#define  VR4121_WRBERRINTR	(1 << 10)#define  VR4121_SIUINTR		(1 << 9)#define  VR4121_GIUINTR		(1 << 8)#define  VR4121_KIUINTR		(1 << 7)#define  VR4121_AIUINTR		(1 << 6)#define  VR4121_PIUINTR		(1 << 5)#define  VR4121_ETIMERINTR	(1 << 3)#define  VR4121_RTCL1INTR	(1 << 2)#define  VR4121_POWERINTR	(1 << 1)#define  VR4121_BATINTR		(1 << 0)#define  VR4121_ZEROINTR	 0#define VR4121_ICU_SYSINT2REG  	VR4121_ADRS(0x200)#define VR4121_ICU_MSYSINT2REG	VR4121_ADRS(0x206)#define  VR4121_DSIUINTR	(1 << 5)#define  VR4121_FIRINTR		(1 << 4)#define  VR4121_TCLKINTR	(1 << 3)#define  VR4121_HSPINTR		(1 << 2)#define  VR4121_LEDINTR		(1 << 1)#define  VR4121_RTCL2INTR	(1 << 0)/* ICU subsystem status and mask registers */#define VR4121_ICU_PIUINTREG	VR4121_ADRS(0x82)#define VR4121_ICU_ADUINTREG	VR4121_ADRS(0x84)#define VR4121_ICU_KIUINTREG	VR4121_ADRS(0x86)#define VR4121_ICU_GIUINTLREG	VR4121_ADRS(0x88)#define VR4121_ICU_DSIUINTREG	VR4121_ADRS(0x8a)#define VR4121_ICU_MPIUINTREG	VR4121_ADRS(0x8e)#define VR4121_ICU_MAIUINTREG	VR4121_ADRS(0x90)#define VR4121_ICU_MKIUINTREG	VR4121_ADRS(0x92)#define VR4121_ICU_MGIUINTLREG	VR4121_ADRS(0x94)#define VR4121_ICU_MDSIUINTREG	VR4121_ADRS(0x96)#define VR4121_ICU_NMIREG	VR4121_ADRS(0x98)#define VR4121_ICU_SOFTINTREG	VR4121_ADRS(0x9a)#define VR4121_ICU_GIUINTHREG   VR4121_ADRS(0x202)#define VR4121_ICU_FIRINTHREG   VR4121_ADRS(0x204)#define VR4121_ICU_MGIUINTHREG  VR4121_ADRS(0x208)#define VR4121_ICU_MFIRINTHREG  VR4121_ADRS(0x20a)/* ICU MDSIUINTREG bit definitions */#define  VR4121_ICU_DSIU_INTSR0	   (1 << 9)#define  VR4121_ICU_DSIU_INTST0	   (1 << 8)/* PMU registers */#define VR4121_PMUINTREG	VR4121_ADRS(0xa0)  /* verify this adr XXX */#define VR4121_PMUCNTREG	VR4121_ADRS(0xa2)  /* verify this adr XXX */#define VR4121_HALTIMERRST	(1 << 2)/* RTC registers */#define VR4121_ETIMELREG	VR4121_ADRS(0xc0)#define VR4121_ETIMEMREG	VR4121_ADRS(0xc2)#define VR4121_ETIMEHREG	VR4121_ADRS(0xc4)#define VR4121_ECMPLREG		VR4121_ADRS(0xc8)#define VR4121_ECMPMREG		VR4121_ADRS(0xca)#define VR4121_ECMPHREG		VR4121_ADRS(0xcc)  /* modified XXX was 0xce */#define VR4121_RTCL1LREG	VR4121_ADRS(0xd0)#define VR4121_RTCL1HREG	VR4121_ADRS(0xd2)#define VR4121_RTCL1CNTLREG	VR4121_ADRS(0xd4)#define VR4121_RTCL1CNTHREG	VR4121_ADRS(0xd6)#define VR4121_RTCL2LREG	VR4121_ADRS(0xd8)#define VR4121_RTCL2HREG	VR4121_ADRS(0xda)#define VR4121_RTCL2CNTLREG	VR4121_ADRS(0xdc)#define VR4121_RTCL2CNTHREG	VR4121_ADRS(0xde)#define VR4121_TCLKLREG		VR4121_ADRS(0x1c0)#define VR4121_TCLKHREG		VR4121_ADRS(0x1c2)#define VR4121_TCLKCNTLREG	VR4121_ADRS(0x1c4)#define VR4121_TCLKCNTHREG	VR4121_ADRS(0x1c6)#define VR4121_RTCINTREG	VR4121_ADRS(0x1de)#define  VR4121_RTC_RTCINTR0	(1 << 0)#define  VR4121_RTC_RTCINTR1	(1 << 1)#define  VR4121_RTC_RTCINTR2	(1 << 2)#define  VR4121_RTC_RTCINTR3	(1 << 3)/* define VR4102 RTC registers to use nvr4102RTCTimer.c */#define VR4102_ETIMELREG	VR4121_ETIMELREG#define VR4102_ETIMEMRE		VR4121_ETIMEMRE#define VR4102_ETIMEHREG	VR4121_ETIMEHREG#define VR4102_ECMPLREG 	VR4121_ECMPLREG#define VR4102_ECMPMREG 	VR4121_ECMPMREG#define VR4102_ECMPHREG 	VR4121_ECMPHREG#define VR4102_RTCL1LREG	VR4121_RTCL1LREG#define VR4102_RTCL1HREG	VR4121_RTCL1HREG#define VR4102_RTCL1CNTLREG	VR4121_RTCL1CNTLREG#define VR4102_RTCL1CNTHREG	VR4121_RTCL1CNTHREG#define VR4102_RTCL2LREG	VR4121_RTCL2LREG
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