ppc555siu.h

IXP425的BSP代码

/* ppc555Siu.h - PowerPC 555 Unified System Interface Unit header file */

/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,26aug99,cmc  Added new definitions
01b,15apr99.cmc	 Fixed PISCR_PIRQ values
01a,17mar99,zl 	 created.
*/

/*
This file contains constants of the System Interface Unit (SIU) for the
Motorola MPC555 PowerPC microcontroller
*/

#ifndef __INCppc555Siuh
#define __INCppc555Siuh

#ifdef __cplusplus
extern "C" {
#endif

#ifdef	_ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;   /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8;   /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif	/* _ASMLANGUAGE */


/* 
 * MPC555 SIU internal register/memory map 
 */

/* General SIU registers */

#define SIUMCR(base)	(CAST(VUINT32 *) (base + 0x2FC000)) /* SIU Module Config*/
#define	SYPCR(base)	(CAST(VUINT32 *) (base + 0x2FC004)) /* Protection Ctrl */
#define	SWSR(base)	(CAST(VUINT16 *) (base + 0x2FC00E)) /* SW Service Reg */
#define	SIPEND(base)	(CAST(VUINT32 *) (base + 0x2FC010)) /* Intr Pending reg */
#define	SIMASK(base)	(CAST(VUINT32 *) (base + 0x2FC014)) /* Intr Mask reg */
#define	SIEL(base)	(CAST(VUINT32 *) (base + 0x2FC018)) /* Intr Edge Lvl */
#define	SIVEC(base)	(CAST(VUINT32 *) (base + 0x2FC01C)) /* Intr Vector reg */
#define	TESR(base)	(CAST(VUINT32 *) (base + 0x2FC020)) /* Tx Error Status */
#define	SGPIODT1(base)	(CAST(VUINT32 *) (base + 0x2FC024)) /* GP I/O Data reg */
#define	SGPIODT2(base)	(CAST(VUINT32 *) (base + 0x2FC028)) /* GP I/O Data reg 2 */
#define	SGPIOCR(base)	(CAST(VUINT32 *) (base + 0x2FC02C)) /* GP I/O Control reg */
#define	EMCR(base)	(CAST(VUINT32 *) (base + 0x2FC030)) /* Ext Mstr Mode Ctrl */
#define	PDMCR(base)	(CAST(VUINT16 *) (base + 0x2FC03C)) /* Pads Module Ctrl */

/* MEMC registers */

#define BR0(base)	(CAST(VUINT32 *) (base + 0x2FC100)) /* Base Reg bank 0 */
#define OR0(base)	(CAST(VUINT32 *) (base + 0x2FC104)) /* Option Reg bank 0*/
#define BR1(base)	(CAST(VUINT32 *) (base + 0x2FC108)) /* Base Reg bank 1 */
#define OR1(base)	(CAST(VUINT32 *) (base + 0x2FC10C)) /* Option Reg bank 1*/
#define BR2(base)	(CAST(VUINT32 *) (base + 0x2FC110)) /* Base Reg bank 2 */
#define OR2(base)	(CAST(VUINT32 *) (base + 0x2FC114)) /* Option Reg bank 2*/
#define BR3(base)	(CAST(VUINT32 *) (base + 0x2FC118)) /* Base Reg bank 3 */
#define OR3(base)	(CAST(VUINT32 *) (base + 0x2FC11C)) /* Option Reg bank 3*/

#define DMBR(base)	(CAST(VUINT32 *) (base + 0x2FC140)) /* Dual-Mapping Base reg*/
#define DMOR(base)	(CAST(VUINT32 *) (base + 0x2FC144)) /* Dual-Mapping Opt reg*/
#define MSTAT(base)	(CAST(VUINT16 *) (base + 0x2FC178)) /* Memory Status */

/* System Integration Timers */

#define TBSCR(base)	(CAST(VUINT16 *) (base + 0x2FC200)) /* T.B. Status Ctrl */
#define TBREFF0(base)	(CAST(VUINT32 *) (base + 0x2FC204)) /* Time Base Ref 0 */
#define TBREFF1(base)	(CAST(VUINT32 *) (base + 0x2FC208)) /* Time Base Ref 1 */

#define RTCSC(base)	(CAST(VUINT16 *) (base + 0x2FC220)) /* Clock Status Ctrl*/
#define RTC(base)	(CAST(VUINT32 *) (base + 0x2FC224)) /* RT Clock */
#define RTSEC(base)	(CAST(VUINT32 *) (base + 0x2FC228)) /* RT Alarm Seconds */
#define RTCAL(base)	(CAST(VUINT32 *) (base + 0x2FC22C)) /* Real Time Alarm */

#define PISCR(base)	(CAST(VUINT16 *) (base + 0x2FC240)) /* PIT Status Ctrl */
#define PITC(base)	(CAST(VUINT32 *) (base + 0x2FC244)) /* PIT Count */
#define PITR(base)	(CAST(VUINT32 *) (base + 0x2FC248)) /* PIT */

/* Clock and Reset */

#define SCCR(base)	(CAST(VUINT32 *) (base + 0x2FC280)) /* System Clock Ctrl*/
#define PLPRCR(base)	(CAST(VUINT32 *) (base + 0x2FC284)) /* PLL, LPower Reset*/
#define RSR(base)	(CAST(VUINT16 *) (base + 0x2FC288)) /* Reset Status Reg */
#define COLIR(base)	(CAST(VUINT16 *) (base + 0x2FC28C)) /* Chg of Lock Int reg*/
#define VSRMCR(base)	(CAST(VUINT16 *) (base + 0x2FC290)) /* VDDSRM Ctrl reg*/

/* System Integration Timers Keys */

#define TBSCRK(base)	(CAST(VUINT32 *) (base + 0x2FC300)) /* TB Stat Ctrl key */
#define TBREFF0K(base)	(CAST(VUINT32 *) (base + 0x2FC304)) /* TB Ref 0 Key */
#define TBREFF1K(base)	(CAST(VUINT32 *) (base + 0x2FC308)) /* TB Ref 1 Key */
#define TBK(base)	(CAST(VUINT32 *) (base + 0x2FC30C)) /* TB & Dec Key */

#define RTCSCK(base)	(CAST(VUINT32 *) (base + 0x2FC320)) /* RT Stat Ctrl Key */
#define RTCK(base)	(CAST(VUINT32 *) (base + 0x2FC324)) /* RT Clock Key */
#define RTSECK(base)	(CAST(VUINT32 *) (base + 0x2FC328)) /* RT Alarm Second */
#define RTCALK(base)	(CAST(VUINT32 *) (base + 0x2FC32C)) /* R T Alarm Key */

#define PISCRK(base)	(CAST(VUINT32 *) (base + 0x2FC340)) /* PIT Stat Ctrl Key*/
#define PITCK(base)	(CAST(VUINT32 *) (base + 0x2FC344)) /* PIT Count Key */

/* Clock and Reset Keys */

#define SCCRK(base)	(CAST(VUINT32 *) (base + 0x2FC380)) /* System Clk Ctrl */
#define PLPRCRK(base)	(CAST(VUINT32 *) (base + 0x2FC384)) /* Pll, LP&R Ctrl */
#define RSRK(base)	(CAST(VUINT32 *) (base + 0x2FC388)) /* Reset Status Key */
#define  UMCR(base)     (CAST(VUINT32 *) (base + 0x307F80)) /* IMB Module Config */

/*
 * SIU register bit definitions 
 */

/* SIU Module Configuration register bit definition (SIUMCR - 0x00) */

#define SIUMCR_EARB	0x80000000	/* External Abritation */
#define SIUMCR_EARP	0x70000000	/* Extern Abri. Req. prior.*/
#define SIUMCR_DSHW	0x00800000	/* Data Showcycles */
#define SIUMCR_DBGC	0x00600000	/* Debug pins conf */
#define SIUMCR_DBPC	0x00100000	/* Debug Port pins conf */
#define SIUMCR_ATWC	0x00080000	/* Addr wrt type enable conf */
#define SIUMCR_GPC	0x00060000	/* General pins conf */
#define SIUMCR_DLK	0x00010000	/* Debug Register Lock */
#define SIUMCR_SC	0x00006000	/* Single-chip select*/
#define SIUMCR_RCTX	0x00001000	/* Reset conf/timer exp.*/
#define SIUMCR_MLRC	0x00000C00	/* Multi-level reserv. ctrl*/
#define SIUMCR_MTSC	0x00000010	/* Memory transfer start ctrl*/

/* System Portection Control register bit definition (SYPCR - 0x04) */

#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count */
#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing */
#define SYPCR_BME	0x00000080	/* Bus Monitor Enable */
#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze */
#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable */
#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Sel */
#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale */

/* System Interrupt PENDing register bit definition (SIPEND - 0x10) */

#define SIPEND_IRQ0	0x80000000	/* Interrupt IRQ0 pending */
#define SIPEND_LVL0	0x40000000	/* Interrupt LEVEL 0 pending */
#define SIPEND_IRQ1	0x20000000	/* Interrupt IRQ1 pending */
#define SIPEND_LVL1	0x10000000	/* Interrupt LEVEL 1 pending */
#define SIPEND_IRQ2	0x08000000	/* Interrupt IRQ2 pending */
#define SIPEND_LVL2	0x04000000	/* Interrupt LEVEL 2 pending */
#define SIPEND_IRQ3	0x02000000	/* Interrupt IRQ3 pending */
#define SIPEND_LVL3	0x01000000	/* Interrupt LEVEL 3 pending */
#define SIPEND_IRQ4	0x00800000	/* Interrupt IRQ4 pending */
#define SIPEND_LVL4	0x00400000	/* Interrupt LEVEL 4 pending */
#define SIPEND_IRQ5	0x00200000	/* Interrupt IRQ5 pending */
#define SIPEND_LVL5	0x00100000	/* Interrupt LEVEL 5 pending */
#define SIPEND_IRQ6	0x00080000	/* Interrupt IRQ6 pending */
#define SIPEND_LVL6	0x00040000	/* Interrupt LEVEL 6 pending */
#define SIPEND_IRQ7	0x00020000	/* Interrupt IRQ7 pending */
#define SIPEND_LVL7	0x00010000	/* Interrupt LEVEL 7 pending */

/* System Interrupt MASK register bit definition (SIMASK - 0x14) */

#define SIMASK_IRM0	0x80000000	/* Interrupt IRQ0 mask */
#define SIMASK_LVM0	0x40000000	/* Interrupt LEVEL 0 mask */
#define SIMASK_IRM1	0x20000000	/* Interrupt IRQ1 mask */
#define SIMASK_LVM1	0x10000000	/* Interrupt LEVEL 1 mask */
#define SIMASK_IRM2	0x08000000	/* Interrupt IRQ2 mask */
#define SIMASK_LVM2	0x04000000	/* Interrupt LEVEL 2 mask */
#define SIMASK_IRM3	0x02000000	/* Interrupt IRQ3 mask */
#define SIMASK_LVM3	0x01000000	/* Interrupt LEVEL 3 mask */
#define SIMASK_IRM4	0x00800000	/* Interrupt IRQ4 mask */
#define SIMASK_LVM4	0x00400000	/* Interrupt LEVEL 4 mask */
#define SIMASK_IRM5	0x00200000	/* Interrupt IRQ5 mask */
#define SIMASK_LVM5	0x00100000	/* Interrupt LEVEL 5 mask */
#define SIMASK_IRM6	0x00080000	/* Interrupt IRQ6 mask */
#define SIMASK_LVM6	0x00040000	/* Interrupt LEVEL 6 mask */
#define SIMASK_IRM7	0x00020000	/* Interrupt IRQ7 mask */
#define SIMASK_LVM7	0x00010000	/* Interrupt LEVEL 7 mask */
#define SIMASK_ALL	0xffff0000	/* All interrupt mask */

/* System Interrupt Edge Level mask register bit definition (SIEL - 0x1C) */

#define SIEL_ED0	0x80000000	/* Interrupt IRQ0 on falling Edge */