nvr4122.h

IXP425的BSP代码

#define VR4102_TCLKLREG		VR4122_TCLKLREG
#define VR4102_TCLKHREG		VR4122_TCLKHREG
#define VR4102_TCLKCNTLREG	VR4122_TCLKCNTLREG
#define VR4102_TCLKCNTHREG	VR4122_TCLKCNTHREG
#define VR4102_RTCINTREG  	VR4122_RTCINTREG
#define VR4102_RTC_RTCINTR0	VR4122_RTCINTR0
#define VR4102_RTC_RTCINTR1	VR4122_RTCINTR1
#define VR4102_RTC_RTCINTR2	VR4122_RTCINTR2
#define VR4102_RTC_RTCINTR3	VR4122_RTCINTR3

#define VR4102_RTCL1INTR	VR4122_RTCL1INTR
#define VR4102_RTCL2INTR	VR4122_RTCL2INTR

#define VR4102_ICU_MSYSINT1REG	VR4122_MSYSINT1REG

/* GIU registers */

#define VR4122_GIUIOSELL	VR4122_REG16(0x140)
#define VR4122_GIUIOSELH	VR4122_REG16(0x142)
#define VR4122_GIUPIODL		VR4122_REG16(0x144)
#define VR4122_GIUPIODH		VR4122_REG16(0x146)
#define VR4122_GIUINTSTATL	VR4122_REG16(0x148)
#define VR4122_GIUINTSTATH	VR4122_REG16(0x14a)
#define VR4122_GIUINTENL	VR4122_REG16(0x14c)
#define VR4122_GIUINTENH	VR4122_REG16(0x14e)
#define VR4122_GIUINTTYPL	VR4122_REG16(0x150)
#define VR4122_GIUINTTYPH	VR4122_REG16(0x152)
#define VR4122_GIUINTALSELL	VR4122_REG16(0x154)
#define VR4122_GIUINTALSELH	VR4122_REG16(0x156)
#define VR4122_GIUINTHTSELL	VR4122_REG16(0x158)
#define VR4122_GIUINTHTSELH	VR4122_REG16(0x15a)
#define VR4122_GIUPODATEN	VR4122_REG16(0x15c)
#define VR4122_GIUPODATL	VR4122_REG16(0x15e)

/* 
 * The general-purpose I/O pins (GPIO) are enabled and controlled via
 * identically placed bits in the GIU registers and some of the ICU
 * registers. This set of pin masks can be used with whichever registers
 * contain GPIO pin configuration. 
 */

#define  VR4122_GPIO_PIN_31	0x8000
#define  VR4122_GPIO_PIN_30	0x4000
#define  VR4122_GPIO_PIN_29	0x2000
#define  VR4122_GPIO_PIN_28	0x1000
#define  VR4122_GPIO_PIN_27	0x0800
#define  VR4122_GPIO_PIN_26	0x0400
#define  VR4122_GPIO_PIN_25	0x0200
#define  VR4122_GPIO_PIN_24	0x0100
#define  VR4122_GPIO_PIN_23	0x0080
#define  VR4122_GPIO_PIN_22	0x0040
#define  VR4122_GPIO_PIN_21	0x0020
#define  VR4122_GPIO_PIN_20	0x0010
#define  VR4122_GPIO_PIN_19	0x0008
#define  VR4122_GPIO_PIN_18	0x0004
#define  VR4122_GPIO_PIN_17	0x0002
#define  VR4122_GPIO_PIN_16	0x0001
#define  VR4122_GPIO_PIN_15	0x8000
#define  VR4122_GPIO_PIN_14	0x4000
#define  VR4122_GPIO_PIN_13	0x2000
#define  VR4122_GPIO_PIN_12	0x1000
#define  VR4122_GPIO_PIN_11	0x0800
#define  VR4122_GPIO_PIN_10	0x0400
#define  VR4122_GPIO_PIN_9	0x0200
#define  VR4122_GPIO_PIN_8	0x0100
#define  VR4122_GPIO_PIN_7	0x0080
#define  VR4122_GPIO_PIN_6	0x0040
#define  VR4122_GPIO_PIN_5	0x0020
#define  VR4122_GPIO_PIN_4	0x0010
#define  VR4122_GPIO_PIN_3	0x0008
#define  VR4122_GPIO_PIN_2	0x0004
#define  VR4122_GPIO_PIN_1	0x0002
#define  VR4122_GPIO_PIN_0	0x0001

/* SCI registers */

#define VR4122_TIMOUTCNTREG	VR4122_REG16(0x1000)
#define VR4122_TIMOUTCOUNTREG	VR4122_REG16(0x1002)
#define VR4122_ERRLADDRESSREG	VR4122_REG16(0x1004)
#define VR4122_ERRHADDRESSREG	VR4122_REG16(0x1006)
#define VR4122_SCUINTRREG	VR4122_REG16(0x1008)

/* SDRAMU registers */

#define VR4122_SDRAMMODEREG	VR4122_REG16(0x400)
#define VR4122_SDRAMCNTREG	VR4122_REG16(0x402)
#define VR4122_BCURFCNTREG	VR4122_REG16(0x404)
#define VR4122_BCURFCOUNTREG	VR4122_REG16(0x406)
#define VR4122_RAMSIZEREG	VR4122_REG16(0x408)

/* PCIU registers */

#define VR4122_PCIMMAW1REG	VR4122_REG32(0xc00)
#define VR4122_PCIMMAW2REG	VR4122_REG32(0xc04)
#define VR4122_PCITAW1REG	VR4122_REG32(0xc08)
#define VR4122_PCITAW2REG	VR4122_REG32(0xc0c)
#define VR4122_PCIMIOAWREG	VR4122_REG32(0xc10)
#define VR4122_PCICONFDREG	VR4122_REG32(0xc14)
#define VR4122_PCICONFAREG	VR4122_REG32(0xc18)
#define VR4122_PCIMAILREG	VR4122_REG32(0xc1c)
#define VR4122_BUSERRADREG	VR4122_REG32(0xc24)
#define VR4122_INTCNTSTAREG	VR4122_REG32(0xc28)
#define VR4122_PCIEXACCREG	VR4122_REG32(0xc2c)
#define VR4122_PCIRECONTREG	VR4122_REG32(0xc30)
#define VR4122_PCIENREG		VR4122_REG32(0xc34)
#define VR4122_PCICLKSELREG	VR4122_REG32(0xc38)
#define VR4122_PCITRDYVREG	VR4122_REG32(0xc3c)
#define VR4122_PCICLKRUNREG	VR4122_REG16(0xc60)

#define VR4122_PCICLKSEL_DIV_1  0x2
#define VR4122_PCICLKSEL_DIV_2  0x0
#define VR4122_PCICLKSEL_DIV_4  0x1

#define VR4122_PCICONFIGDONE	0x00000004	/* PCIENREG */
#define VR4122_PCICLKRUN	0x0001		/* PCICLKRUNREG */
#define VR4122_PCISTOPEN	0x8000		/* PCICLKRUNREG */
#define VR4122_PCIIBA		0xFF000000	/* PCIM*AW*REG */
#define VR4122_PCIMSK		0x000FE000	/* PCIM*AW*REG, PCITAWnREG */
#define VR4122_PCIWINEN		0x00001000	/* PCIM*AW*REG, PCITAWnREG */
#define VR4122_PCIPCIA		0x000000FF	/* PCIM*AW*REG */
#define VR4122_PCIITA		0x000007FF	/* PCITAWnREG */

/* PCI Config Registers */

#define VR4122_PCICONF_IDENT	VR4122_REG32(0xd00)
#define VR4122_PCICONF_CMDSR	VR4122_REG32(0xd04)
#define VR4122_PCICONF_REVCLASS	VR4122_REG32(0xd08)
#define VR4122_PCICONF_CACHELAT	VR4122_REG32(0xd0c)
#define VR4122_PCICONF_MAILBA	VR4122_REG32(0xd10)
#define VR4122_PCICONF_PCIMBA1	VR4122_REG32(0xd14)
#define VR4122_PCICONF_PCIMBA2	VR4122_REG32(0xd18)
#define VR4122_PCICONF_PCIINT	VR4122_REG32(0xd3c)
#define VR4122_PCICONF_RETVAL	VR4122_REG32(0xd40)

/* DSIU registers */

#define VR4122_DSIURB		VR4122_REG8(0x820)	/* SUILC7 = 0, read */
#define VR4122_DSIUTH		VR4122_REG8(0x820)	/* SUILC7 = 0, write */
#define VR4122_DSIUDLL		VR4122_REG8(0x820)	/* SUILC7 = 1 */
#define VR4122_DSIUIE		VR4122_REG8(0x821)	/* SUILC7 = 0 */
#define VR4122_DSIUDLM		VR4122_REG8(0x821)	/* SUILC7 = 1 */
#define VR4122_DSIUIID		VR4122_REG8(0x822)	/* read */
#define VR4122_DSIUFC		VR4122_REG8(0x822)	/* write */
#define VR4122_DSIULC		VR4122_REG8(0x823)
#define VR4122_DSIUMC		VR4122_REG8(0x824)
#define VR4122_DSIULS		VR4122_REG8(0x825)
#define VR4122_DSIUMS		VR4122_REG8(0x826)
#define VR4122_DSIUSC		VR4122_REG8(0x827)
#define VR4122_DSIURESET	VR4122_SIURESET		/* Common with SIU */

#define VR4122_DSIU_BASE	VR4122_DSIURB
#define VR4122_DSIU_DELTA	1
#define VR4122_DSIU_XTAL	18432000	/* crystal input to 16550 */

#define VR4122_DSIURST		0x0002		/* in SIURESET register */

/* LED registers */

#define VR4122_LEDHTSREG	VR4122_REG16(0x180)
#define VR4122_LEDLTSREG	VR4122_REG16(0x182)
#define VR4122_LEDCNTREG	VR4122_REG16(0x188)
#define VR4122_LEDASTCREG	VR4122_REG16(0x18a)
#define VR4122_LEDINTREG	VR4122_REG16(0x18c)

/* SIU registers */

#define VR4122_SIURB		VR4122_REG8(0x800)	/* SUILC7 = 0, read */
#define VR4122_SIUTH		VR4122_REG8(0x800)	/* SUILC7 = 0, write */
#define VR4122_SIUDLL		VR4122_REG8(0x800)	/* SUILC7 = 1 */
#define VR4122_SIUIE		VR4122_REG8(0x801)	/* SUILC7 = 0 */
#define VR4122_SIUDLM		VR4122_REG8(0x801)	/* SUILC7 = 1 */
#define VR4122_SIUIID		VR4122_REG8(0x802)	/* read */
#define VR4122_SIUFC		VR4122_REG8(0x802)	/* write */
#define VR4122_SIULC		VR4122_REG8(0x803)
#define VR4122_SIUMC		VR4122_REG8(0x804)
#define VR4122_SIULS		VR4122_REG8(0x805)
#define VR4122_SIUMS		VR4122_REG8(0x806)
#define VR4122_SIUSC		VR4122_REG8(0x807)
#define VR4122_SIUIRSEL		VR4122_REG8(0x808)
#define VR4122_SIURESET		VR4122_REG8(0x809)	/* common with DSIU */
#define VR4122_SIUCSEL		VR4122_REG8(0x80a)

#define VR4122_SIU_BASE		VR4122_SIURB
#define VR4122_SIU_DELTA	1
#define VR4122_SIU_XTAL		18432000	/* crystal input to 16550 */

#define VR4122_SIURST		0x0001		/* in SIURESET register */

/* CSI registers */

#define VR4122_CSI_MODEREG	VR4122_REG16(0x1a0)
#define VR4122_CSI_CLKSELREG	VR4122_REG16(0x1a1)
#define VR4122_CSI_SIRBREG	VR4122_REG16(0x1a2)
#define VR4122_CSI_SOTBREG	VR4122_REG16(0x1a4)
#define VR4122_CSI_SIRBEREG	VR4122_REG16(0x1a6)
#define VR4122_CSI_SOTBFREG	VR4122_REG16(0x1a8)
#define VR4122_CSI_SIOREG	VR4122_REG16(0x1aa)
#define VR4122_CSI_CNTREG	VR4122_REG16(0x1b0)
#define VR4122_CSI_INTREG	VR4122_REG16(0x1b2)
#define VR4122_CSI_IFIFOVREG	VR4122_REG16(0x1b4)
#define VR4122_CSI_OFIFOVREG	VR4122_REG16(0x1b6)
#define VR4122_CSI_IFIFOREG	VR4122_REG16(0x1b8)
#define VR4122_CSI_OFIFOREG	VR4122_REG16(0x1ba)
#define VR4122_CSI_FIFOTRGREG	VR4122_REG16(0x1bc)

/* FIR registers - not included */

/* Clock rate values for different settings of CLKSEL[2:0] pins/jumpers. */

#define CPU_PCLOCK_RATE_111	200700000
#define CPU_PCLOCK_RATE_110	180600000
#define CPU_PCLOCK_RATE_101	164200000
#define CPU_PCLOCK_RATE_100	150500000
#define CPU_PCLOCK_RATE_011	129000000
#define CPU_PCLOCK_RATE_010	100400000
#define CPU_PCLOCK_RATE_001	 90300000
#define CPU_PCLOCK_RATE_000	 78500000

/* Miscellaneous */

#define NUM_4122_TTY		2	/* SIU + DSIU */

#ifdef __cplusplus
}
#endif

#endif /* __INCnvr4122h */