📄 nvr4122.h
字号:
/* nvr4122.h - NEC NVR4122 header file *//* Copyright 1984-2001 Wind River Systems, Inc. *//*modification history--------------------01c,17apr01,sru update after code review01b,09apr01,sru cleanup after code review01a,05jan01,sru fix cache sizes01a,03jan01,sru created.*//*DESCRIPTIONThis file contains constants for the NEC VR4122. Register addressdefinitions for the various subsystems are provided, and some (butnot all) register field definitions are provided.*/#ifndef __INCnvr4122h#define __INCnvr4122h#include "vxWorks.h"#ifdef __cplusplusextern "C" {#endif#define VR4122_ICACHE_SIZE 32768#define VR4122_DCACHE_SIZE 16384/* VR4122 register definitions. */#define VR4122_REG_BASE (0x0f000000+K1BASE)#ifdef _ASMLANGUAGE#define VR4122_REG32(reg) (VR4122_REG_BASE + (reg))#define VR4122_REG16(reg) (VR4122_REG_BASE + (reg))#define VR4122_REG8(reg) (VR4122_REG_BASE + (reg))#else#define VR4122_REG32(reg) ((volatile UINT32 *)(VR4122_REG_BASE + (reg)))#define VR4122_REG16(reg) ((volatile UINT16 *)(VR4122_REG_BASE + (reg)))#define VR4122_REG8(reg) ((volatile UINT8 *)(VR4122_REG_BASE + (reg)))#endif /* _ASMLANGUAGE *//* BCU registers */#define VR4122_BCUCNTREG1 VR4122_REG16(0x00)#define VR4122_ROMSIZEREG VR4122_REG16(0x04)#define VR4122_ROMSPEEDREG VR4122_REG16(0x06)#define VR4122_IO0SPEEDREG VR4122_REG16(0x08)#define VR4122_IO1SPEEDREG VR4122_REG16(0x0a)#define VR4122_REVIDREG VR4122_REG16(0x10)#define VR4122_CLKSPEEDREG VR4122_REG16(0x14)#define VR4122_BCUCNTREG3 VR4122_REG16(0x16)#define VR4122_BCUCACHECNTREG VR4122_REG16(0x18)/* BCUCNTREG1 bit definitions */#define VR4122_PAGESIZE 0x3000#define VR4122_PAGEROM2 0x0400#define VR4122_PAGEROM0 0x0100#define VR4122_ROMWEN2 0x0040#define VR4122_ROMWEN0 0x0010/* DMAAU registers */#define VR4122_CSIIBALREG VR4122_REG16(0x20)#define VR4122_CSIIBAHREG VR4122_REG16(0x22)#define VR4122_CSIIALREG VR4122_REG16(0x24)#define VR4122_CSIIAHREG VR4122_REG16(0x26)#define VR4122_CSIOBALREG VR4122_REG16(0x28)#define VR4122_CSIOBAHREG VR4122_REG16(0x2a)#define VR4122_CSIOALREG VR4122_REG16(0x2c)#define VR4122_CSIOAHREG VR4122_REG16(0x2e)#define VR4122_FIRBALREG VR4122_REG16(0x30)#define VR4122_FIRBAHREG VR4122_REG16(0x32)#define VR4122_FIRALREG VR4122_REG16(0x34)#define VR4122_FIRAHREG VR4122_REG16(0x36)#define VR4122_RAMBALREG VR4122_REG16(0x1e0)#define VR4122_RAMBAHREG VR4122_REG16(0x1e2)#define VR4122_RAMALREG VR4122_REG16(0x1e4)#define VR4122_RAMAHREG VR4122_REG16(0x1e6)#define VR4122_IOBALREG VR4122_REG16(0x1e8)#define VR4122_IOBAHREG VR4122_REG16(0x1ea)#define VR4122_IOALREG VR4122_REG16(0x1ec)#define VR4122_IOAHREG VR4122_REG16(0x1ee)/* DCU registers */#define VR4122_DMARSTREG VR4122_REG16(0x40)#define VR4122_DMAIDLEREG VR4122_REG16(0x42)#define VR4122_DMASENREG VR4122_REG16(0x44)#define VR4122_DMAMSKREG VR4122_REG16(0x46)#define VR4122_DMAREQREG VR4122_REG16(0x48)#define VR4122_TDREG VR4122_REG16(0x4a)#define VR4122_DMAABITREG VR4122_REG16(0x4c)#define VR4122_CONTROLREG VR4122_REG16(0x4e)#define VR4122_BASSCNTLREG VR4122_REG16(0x50)#define VR4122_BASSCNTHREG VR4122_REG16(0x52)#define VR4122_CURRENTCNTLREG VR4122_REG16(0x54)#define VR4122_CURRENTCNTHREG VR4122_REG16(0x56)#define VR4122_TCINTR VR4122_REG16(0x58)/* DMA mask bit definitions */#define VR4122_DMAMSKAIOR 0x0008#define VR4122_DMAMSKCOUT 0x0004#define VR4122_DMAMSKCIN 0x0002#define VR4122_DMAMSKFOUT 0x0001/* CMU register */#define VR4122_CMUCLKMSK VR4122_REG16(0x60)#define VR4122_MSKPCIU 0x2000#define VR4122_MSKSCSI 0x1000#define VR4122_MSKDSIU 0x0800#define VR4122_MSKFFIR 0x0400#define VR4122_MSKSSIU 0x0100#define VR4122_MSKCSI 0x0040#define VR4122_MSKFIR 0x0010#define VR4122_MSKSIU 0x0002/* ICU system and system mask registers */#define VR4122_SYSINT1REG VR4122_REG16(0x80)#define VR4122_GIUINTLREG VR4122_REG16(0x88)#define VR4122_DSIUINTREG VR4122_REG16(0x8a)#define VR4122_MSYSINT1REG VR4122_REG16(0x8c)#define VR4122_MGIUINTLREG VR4122_REG16(0x94)#define VR4122_MDSIUINTREG VR4122_REG16(0x96)#define VR4122_NMIREG VR4122_REG16(0x98)#define VR4122_SOFTINTREG VR4122_REG16(0x9a)#define VR4122_SYSINT2REG VR4122_REG16(0xa0)#define VR4122_GIUINTHREG VR4122_REG16(0xa2)#define VR4122_FIRINTREG VR4122_REG16(0xa4)#define VR4122_MSYSINT2REG VR4122_REG16(0xa6)#define VR4122_MGIUINTHREG VR4122_REG16(0xa8)#define VR4122_MFIRINTREG VR4122_REG16(0xaa)#define VR4122_PCIINTREG VR4122_REG16(0xac)#define VR4122_SCUINTREG VR4122_REG16(0xae)#define VR4122_CSIINTREG VR4122_REG16(0xb0)#define VR4122_MPCIINTREG VR4122_REG16(0xb2)#define VR4122_MSCUINTREG VR4122_REG16(0xb4)#define VR4122_MCSIINTREG VR4122_REG16(0xb6)#define VR4122_BCUINTREG VR4122_REG16(0xb8)#define VR4122_MBCUINTREG VR4122_REG16(0xba)#define VR4122_CLKRUNINTR 0x1000#define VR4122_SOFTINTR 0x0800#define VR4122_SIUINTR 0x0200#define VR4122_GIUINTR 0x0100#define VR4122_ETIMERINTR 0x0008#define VR4122_RTCL1INTR 0x0004#define VR4122_POWERINTR 0x0002#define VR4122_BATINTR 0x0001#define VR4122_BCUINTR 0x0200#define VR4122_CSIINTR 0x0100#define VR4122_SCUINTR 0x0080#define VR4122_PCIINTR 0x0040#define VR4122_DSIUINTR 0x0020#define VR4122_FIRINTR 0x0010#define VR4122_TCLKINTR 0x0008#define VR4122_LEDINTR 0x0002#define VR4122_RTCL2INTR 0x0001/* PMU registers */#define VR4122_PMUINTREG VR4122_REG16(0xc0)#define VR4122_PMUCNTREG VR4122_REG16(0xc2)#define VR4122_PMUINT2REG VR4122_REG16(0xc4)#define VR4122_PMUCNT2REG VR4122_REG16(0xc6)#define VR4122_PMUWAITREG VR4122_REG16(0xc8)#define VR4122_PMUTCLKDIVREG VR4122_REG16(0xcc)#define VR4122_PMUINTRCLKDIVREG VR4122_REG16(0xce)#define VR4122_HALTIMERRST 0x0004/* RTC registers */#define VR4122_ETIMELREG VR4122_REG16(0x100)#define VR4122_ETIMEMREG VR4122_REG16(0x102)#define VR4122_ETIMEHREG VR4122_REG16(0x104)#define VR4122_ECMPLREG VR4122_REG16(0x108)#define VR4122_ECMPMREG VR4122_REG16(0x10a)#define VR4122_ECMPHREG VR4122_REG16(0x10c)#define VR4122_RTCL1LREG VR4122_REG16(0x110)#define VR4122_RTCL1HREG VR4122_REG16(0x112)#define VR4122_RTCL1CNTLREG VR4122_REG16(0x114)#define VR4122_RTCL1CNTHREG VR4122_REG16(0x116)#define VR4122_RTCL2LREG VR4122_REG16(0x118)#define VR4122_RTCL2HREG VR4122_REG16(0x11a)#define VR4122_RTCL2CNTLREG VR4122_REG16(0x11c)#define VR4122_RTCL2CNTHREG VR4122_REG16(0x11e)#define VR4122_TCLKLREG VR4122_REG16(0x120)#define VR4122_TCLKHREG VR4122_REG16(0x122)#define VR4122_TCLKCNTLREG VR4122_REG16(0x124)#define VR4122_TCLKCNTHREG VR4122_REG16(0x126)#define VR4122_RTCINTREG VR4122_REG16(0x13e)#define VR4122_RTCINTR0 0x0001#define VR4122_RTCINTR1 0x0002#define VR4122_RTCINTR2 0x0004#define VR4122_RTCINTR3 0x0008/* * The VR4122 RTC module has identical functionality to the VR4102 * RTC module. In order to use the nvr4102RTCTimer.c driver, we must * define the VR4102_... constants in terms of the VR4122 values. */#define VR4102_ETIMELREG VR4122_ETIMELREG#define VR4102_ETIMEMRE VR4122_ETIMEMRE#define VR4102_ETIMEHREG VR4122_ETIMEHREG#define VR4102_ECMPLREG VR4122_ECMPLREG#define VR4102_ECMPMREG VR4122_ECMPMREG#define VR4102_ECMPHREG VR4122_ECMPHREG#define VR4102_RTCL1LREG VR4122_RTCL1LREG#define VR4102_RTCL1HREG VR4122_RTCL1HREG#define VR4102_RTCL1CNTLREG VR4122_RTCL1CNTLREG#define VR4102_RTCL1CNTHREG VR4122_RTCL1CNTHREG#define VR4102_RTCL2LREG VR4122_RTCL2LREG#define VR4102_RTCL2HREG VR4122_RTCL2HREG#define VR4102_RTCL2CNTLREG VR4122_RTCL2CNTLREG#define VR4102_RTCL2CNTHREG VR4122_RTCL2CNTHREG⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -