bcm1250lib.h

IXP425的BSP代码

#define A_SCD_WDOG_CNT_1            0x0010020158
#define A_SCD_WDOG_CFG_1            0x0010020160

/*
 * Generic timers
 */

#define A_SCD_TIMER_0		    0x0010020070
#define A_SCD_TIMER_1               0x0010020078
#define A_SCD_TIMER_2		    0x0010020170
#define A_SCD_TIMER_3               0x0010020178
#define SCD_NUM_TIMERS		    4
#define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
#define A_SCD_TIMER_REGISTER(w,r)   (A_SCD_TIMER_BASE(w) + (r))

#define R_SCD_TIMER_INIT	    0x0000000000
#define R_SCD_TIMER_CNT		    0x0000000010
#define R_SCD_TIMER_CFG		    0x0000000020

#define A_SCD_TIMER_INIT_0          0x0010020070
#define A_SCD_TIMER_CNT_0           0x0010020080
#define A_SCD_TIMER_CFG_0           0x0010020090

#define A_SCD_TIMER_INIT_1          0x0010020078
#define A_SCD_TIMER_CNT_1           0x0010020088
#define A_SCD_TIMER_CFG_1           0x0010020098

#define A_SCD_TIMER_INIT_2          0x0010020170
#define A_SCD_TIMER_CNT_2           0x0010020180
#define A_SCD_TIMER_CFG_2           0x0010020190

#define A_SCD_TIMER_INIT_3          0x0010020178
#define A_SCD_TIMER_CNT_3           0x0010020188
#define A_SCD_TIMER_CFG_3           0x0010020198

/*  ********************************************************************* 
    * System Control Registers
    ********************************************************************* */

#define A_SCD_SYSTEM_REVISION       0x0010020000
#define A_SCD_SYSTEM_CFG            0x0010020008

#define A_SCD_SCRATCH		    0x0010020C10	/* PASS2 */

/*  ********************************************************************* 
    * System Address Trap Registers
    ********************************************************************* */

#define A_ADDR_TRAP_INDEX           0x00100200B0
#define A_ADDR_TRAP_REG             0x00100200B8
#define A_ADDR_TRAP_UP_0            0x0010020400
#define A_ADDR_TRAP_UP_1            0x0010020408
#define A_ADDR_TRAP_UP_2            0x0010020410
#define A_ADDR_TRAP_UP_3            0x0010020418
#define A_ADDR_TRAP_DOWN_0          0x0010020420
#define A_ADDR_TRAP_DOWN_1          0x0010020428
#define A_ADDR_TRAP_DOWN_2          0x0010020430
#define A_ADDR_TRAP_DOWN_3          0x0010020438
#define A_ADDR_TRAP_CFG_0           0x0010020440
#define A_ADDR_TRAP_CFG_1           0x0010020448
#define A_ADDR_TRAP_CFG_2           0x0010020450
#define A_ADDR_TRAP_CFG_3           0x0010020458


/*  ********************************************************************* 
    * System Interrupt Mapper Registers
    ********************************************************************* */

#define A_IMR_CPU0_BASE                 0x0010020000
#define A_IMR_CPU1_BASE                 0x0010022000
#define IMR_REGISTER_SPACING            0x2000

#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))

#define R_IMR_INTERRUPT_DIAG            0x0010
#define R_IMR_INTERRUPT_MASK            0x0028
#define R_IMR_INTERRUPT_TRACE           0x0038
#define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
#define R_IMR_LDT_INTERRUPT_SET         0x0048
#define R_IMR_LDT_INTERRUPT             0x0018
#define R_IMR_LDT_INTERRUPT_CLR         0x0020
#define R_IMR_MAILBOX_CPU               0x00c0
#define R_IMR_ALIAS_MAILBOX_CPU         0x1000
#define R_IMR_MAILBOX_SET_CPU           0x00C8
#define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
#define R_IMR_MAILBOX_CLR_CPU           0x00D0
#define R_IMR_INTERRUPT_STATUS_BASE     0x0100
#define R_IMR_INTERRUPT_STATUS_COUNT    7
#define R_IMR_INTERRUPT_MAP_BASE        0x0200
#define R_IMR_INTERRUPT_MAP_COUNT       64

/*  ********************************************************************* 
    * System Performance Counter Registers
    ********************************************************************* */

#define A_SCD_PERF_CNT_CFG          0x00100204C0
#define A_SCD_PERF_CNT_0            0x00100204D0
#define A_SCD_PERF_CNT_1            0x00100204D8
#define A_SCD_PERF_CNT_2            0x00100204E0
#define A_SCD_PERF_CNT_3            0x00100204E8

/*  ********************************************************************* 
    * System Bus Watcher Registers
    ********************************************************************* */

#define A_SCD_BUS_ERR_STATUS        0x0010020880
#define A_BUS_ERR_DATA_0            0x00100208A0
#define A_BUS_ERR_DATA_1            0x00100208A8
#define A_BUS_ERR_DATA_2            0x00100208B0
#define A_BUS_ERR_DATA_3            0x00100208B8
#define A_BUS_L2_ERRORS             0x00100208C0
#define A_BUS_MEM_IO_ERRORS         0x00100208C8

/*  ********************************************************************* 
    * System Debug Controller Registers
    ********************************************************************* */

#define A_SCD_JTAG_BASE             0x0010000000

/*  ********************************************************************* 
    * System Trace Buffer Registers
    ********************************************************************* */

#define A_SCD_TRACE_CFG             0x0010020A00
#define A_SCD_TRACE_READ            0x0010020A08
#define A_SCD_TRACE_EVENT_0         0x0010020A20
#define A_SCD_TRACE_EVENT_1         0x0010020A28
#define A_SCD_TRACE_EVENT_2         0x0010020A30
#define A_SCD_TRACE_EVENT_3         0x0010020A38
#define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
#define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
#define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
#define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
#define A_SCD_TRACE_EVENT_4         0x0010020A60
#define A_SCD_TRACE_EVENT_5         0x0010020A68
#define A_SCD_TRACE_EVENT_6         0x0010020A70
#define A_SCD_TRACE_EVENT_7         0x0010020A78
#define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
#define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
#define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
#define A_SCD_TRACE_SEQUENCE_7      0x0010020A98

/*  ********************************************************************* 
    * System Generic DMA Registers
    ********************************************************************* */

#define A_DM_0		  	    0x0010020B00
#define A_DM_1		  	    0x0010020B20
#define A_DM_2			    0x0010020B40
#define A_DM_3			    0x0010020B60
#define DM_REGISTER_SPACING	    0x20
#define DM_NUM_CHANNELS		    4
#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg))

#define R_DM_DSCR_BASE		    0x0000000000
#define R_DM_DSCR_COUNT		    0x0000000008
#define R_DM_CUR_DSCR_ADDR	    0x0000000010
#define R_DM_DSCR_BASE_DEBUG	    0x0000000018


/*  *********************************************************************
    *  Physical Address Map
    ********************************************************************* */

#define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
#define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
#define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
#define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
#define A_PHYS_GENBUS			_SB_MAKE64(0x0010090000)
#define A_PHYS_GENBUS_END		_SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
#define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
#define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
#define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
#define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
#define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
#define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
#define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
#define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
#define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
#define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
#define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)

#define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
#define PHYS_L2CACHE_NUM_WAYS           4
#define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
#define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
#define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
#define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
#define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)


/*  *********************************************************************
    *
    *  The remainder are field definitions within the SOC registers
    *
    *  The information in this file is based on the BCM1250 SOC
    *  manual version 0.2, July 2000.
    ********************************************************************* */

/*  *********************************************************************
    *  System control/debug register constants
    ********************************************************************* */

/*
 * System Revision Register (Table 4-1)
 */

#define M_SYS_RESERVED		    _SB_MAKEMASK(8,0)

#define S_SYS_REVISION              _SB_MAKE64(8)
#define M_SYS_REVISION              _SB_MAKEMASK(8,S_SYS_REVISION)
#define V_SYS_REVISION(x)           _SB_MAKEVALUE(x,S_SYS_REVISION)
#define G_SYS_REVISION(x)           _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)

#define K_SYS_REVISION_PASS1	    1
#define K_SYS_REVISION_PASS2	    3
#define K_SYS_REVISION_PASS3	    4 /* XXX Unknown */

#define S_SYS_PART                  _SB_MAKE64(16)
#define M_SYS_PART                  _SB_MAKEMASK(16,S_SYS_PART)
#define V_SYS_PART(x)               _SB_MAKEVALUE(x,S_SYS_PART)
#define G_SYS_PART(x)               _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)

#define K_SYS_PART_BCM1250           0x1250
#define K_SYS_PART_SB1125           0x1125 

#define S_SYS_WID                   _SB_MAKE64(32)
#define M_SYS_WID                   _SB_MAKEMASK(32,S_SYS_WID)
#define V_SYS_WID(x)                _SB_MAKEVALUE(x,S_SYS_WID)
#define G_SYS_WID(x)                _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)

/*
 * System Config Register (Table 4-2)
 * Register: SCD_SYSTEM_CFG
 */

#define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
#define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
#define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
#define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)

#define S_SYS_PLL_DIV               _SB_MAKE64(7)
#define M_SYS_PLL_DIV               _SB_MAKEMASK(5,S_SYS_PLL_DIV)
#define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
#define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)

#define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
#define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
#define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
#define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
#define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)

#define S_SYS_BOOT_MODE             _SB_MAKE64(17)
#define M_SYS_BOOT_MODE             _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
#define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
#define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
#define K_SYS_BOOT_MODE_ROM32       0
#define K_SYS_BOOT_MODE_ROM8        1
#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
#define K_SYS_BOOT_MODE_SMBUS_BIG   3

#define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
#define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
#define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
#define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
#define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
#define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
#define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)

#define S_SYS_CONFIG                26
#define M_SYS_CONFIG                _SB_MAKEMASK(6,S_SYS_CONFIG)
#define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x,S_SYS_CONFIG)
#define G_SYS_CONFIG(x)             _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)

/* The following bits are writeable by JTAG only. */

#define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
#define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)

#define S_SYS_CLKCOUNT              34
#define M_SYS_CLKCOUNT              _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
#define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
#define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)

#define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)

#define S_SYS_PLL_IREF		    43
#define M_SYS_PLL_IREF		    _SB_MAKEMASK(2,S_SYS_PLL_IREF)

#define S_SYS_PLL_VCO		    45
#define M_SYS_PLL_VCO		    _SB_MAKEMASK(2,S_SYS_PLL_VCO)

#define S_SYS_PLL_VREG		    47
#define M_SYS_PLL_VREG		    _SB_MAKEMASK(2,S_SYS_PLL_VREG)

#define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
#define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
#define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
#define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
#define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)

/* End of bits writable by JTAG only. */

#define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
#define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)

#define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
#define M_SYS_UNICPU1               _SB_MAKEMASK1(57)