bcm1250lib.h

IXP425的BSP代码

/* bcm1250Lib.h - BCM1250 systems-on-chip header file */

/* Copyright 2002 Wind River Systems, Inc. */

/*********************************************************************
*
*  Copyright 2000,2001
*  Broadcom Corporation. All rights reserved.
*
*  This software is furnished under license to Wind River Systems, Inc.
*  and may be used only in accordance with the terms and conditions
*  of this license.  No title or ownership is transferred hereby.
********************************************************************* */

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
01d,31may02,pgh  Fix the address definitions for R_MAC_CHLO0_BASE and
                 R_MAC_CHUP0_BASE.
01c,10may02,tlc  Add C++ header protection.
01b,17dec01,agf  Replace __ASSEMBLER__ with _ASMLANGUAGE
01a,05dec01,agf  created
*/

/*
DESCRIPTION
This file contains constants for the BCM 1250.  Register address
definitions for the various subsystems are provided, and most (but
not all) register field definitions are provided.

Naming schemes for the BCM 1250 constants are:

  M_xxx           MASK constant (identifies bits in a register). 
                  For multi-bit fields, all bits in the field will
                  be set.

  K_xxx           "Code" constant (value for data in a multi-bit
                  field).  The value is right justified.

  V_xxx           "Value" constant.  This is the same as the 
                  corresponding "K_xxx" constant, except it is
                  shifted to the correct position in the register.

  S_xxx           SHIFT constant.  This is the number of bits that
                  a field value (code) needs to be shifted 
                  (towards the left) to put the value in the right
                  position for the register.

  A_xxx           ADDRESS constant.  This will be a physical 
                  address.  Use the PHYS_TO_K1 macro to generate
                  a K1SEG address.

  R_xxx           RELATIVE offset constant.  This is an offset from
                  an A_xxx constant (usually the first register in
                  a group).
  
  G_xxx(X)        GET value.  This macro obtains a multi-bit field
                  from a register, masks it, and shifts it to
                  the bottom of the register (retrieving a K_xxx
                  value, for example).

  V_xxx(X)        VALUE.  This macro computes the value of a
                  K_xxx constant shifted to the correct position
                  in the register.
*/

#ifndef __INCbcm1250Libh
#define __INCbcm1250Libh

#ifdef __cplusplus
extern "C" {
#endif

#include "vxWorks.h"

         /* macros */

/*
 * Cast to 64-bit number.  Presumably the syntax is different in 
 * assembly language.
 *
 */

#if !defined(_ASMLANGUAGE)
#define _SB_MAKE64(x) ((UINT64)(x))
#define _SB_MAKE32(x) ((UINT32)(x))
#else
#define _SB_MAKE64(x) (x)
#define _SB_MAKE32(x) (x)
#endif


/*
 * Make a mask for 1 bit at position 'n'
 */

#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))

/*
 * Make a mask for 'v' bits at position 'n'
 */

#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))

/*
 * Make a value at 'v' at bit position 'n'
 */

#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))

#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))

/*
 * Macros to read/write on-chip registers
 */

#if !defined(_ASMLANGUAGE)
#define SBWRITECSR(csr,val) *((volatile UINT64 *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile UINT64 *) PHYS_TO_K1(csr)))
#endif /* _ASMLANGUAGE*/


         /* defines */

/*  *********************************************************************
    *  Some general notes:
    *  
    *  For the most part, when there is more than one peripheral
    *  of the same type on the SOC, the constants below will be
    *  offsets from the base of each peripheral.  For example,
    *  the MAC registers are described as offsets from the first
    *  MAC register, and there will be a MAC_REGISTER() macro
    *  to calculate the base address of a given MAC.  
    *  
    *  The information in this file is based on the BCM1250 SOC
    *  manual version 0.2, July 2000.
    ********************************************************************* */


/*  ********************************************************************* 
    * Memory Controller Registers
    ********************************************************************* */

#define A_MC_BASE_0                 0x0010051000
#define A_MC_BASE_1                 0x0010052000
#define MC_REGISTER_SPACING         0x1000

#define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
#define A_MC_REGISTER(ctlid,reg)    (A_MC_BASE(ctlid)+(reg))

#define R_MC_CONFIG                 0x0000000100
#define R_MC_DRAMCMD                0x0000000120
#define R_MC_DRAMMODE               0x0000000140
#define R_MC_TIMING1                0x0000000160
#define R_MC_TIMING2                0x0000000180
#define R_MC_CS_START               0x00000001A0
#define R_MC_CS_END                 0x00000001C0
#define R_MC_CS_INTERLEAVE          0x00000001E0
#define S_MC_CS_STARTEND            16

#define R_MC_CSX_BASE               0x0000000200
#define R_MC_CSX_ROW                0x0000000000	/* relative to CSX_BASE, above */
#define R_MC_CSX_COL                0x0000000020	/* relative to CSX_BASE, above */
#define R_MC_CSX_BA                 0x0000000040	/* relative to CSX_BASE, above */
#define MC_CSX_SPACING              0x0000000060	/* relative to CSX_BASE, above */

#define R_MC_CS0_ROW                0x0000000200
#define R_MC_CS0_COL                0x0000000220
#define R_MC_CS0_BA                 0x0000000240
#define R_MC_CS1_ROW                0x0000000260
#define R_MC_CS1_COL                0x0000000280
#define R_MC_CS1_BA                 0x00000002A0
#define R_MC_CS2_ROW                0x00000002C0
#define R_MC_CS2_COL                0x00000002E0
#define R_MC_CS2_BA                 0x0000000300
#define R_MC_CS3_ROW                0x0000000320
#define R_MC_CS3_COL                0x0000000340
#define R_MC_CS3_BA                 0x0000000360
#define R_MC_CS_ATTR                0x0000000380
#define R_MC_TEST_DATA              0x0000000400
#define R_MC_TEST_ECC               0x0000000420
#define R_MC_MCLK_CFG               0x0000000500

/*  ********************************************************************* 
    * L2 Cache Control Registers
    ********************************************************************* */

#define A_L2_READ_ADDRESS           0x0010040018
#define A_L2_EEC_ADDRESS            0x0010040038
#define A_L2_WAY_DISABLE            0x0010041000
#define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE          0x00D0000000

/*  ********************************************************************* 
    * PCI Interface Registers
    ********************************************************************* */

#define A_PCI_TYPE00_HEADER         0x00DE000000
#define A_PCI_TYPE01_HEADER         0x00DE000800


/*  ********************************************************************* 
    * Ethernet DMA and MACs
    ********************************************************************* */

#define A_MAC_BASE_0                0x0010064000
#define A_MAC_BASE_1                0x0010065000
#define A_MAC_BASE_2                0x0010066000

#define MAC_SPACING                 0x1000
#define MAC_DMA_TXRX_SPACING        0x0400
#define MAC_DMA_CHANNEL_SPACING     0x0100
#define DMA_RX                      0
#define DMA_TX                      1
#define MAC_NUM_DMACHAN		    2		    /* channels per direction */

#define MAC_NUM_PORTS               3

#define A_MAC_CHANNEL_BASE(macnum)                  \
            (A_MAC_BASE_0 +                         \
             MAC_SPACING*(macnum))

#define A_MAC_REGISTER(macnum,reg)                  \
            (A_MAC_BASE_0 +                         \
             MAC_SPACING*(macnum) + (reg))


#define R_MAC_DMA_CHANNELS		0x800 /* Relative to A_MAC_CHANNEL_BASE */

#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan)    \
             ((A_MAC_CHANNEL_BASE(macnum)) +        \
             R_MAC_DMA_CHANNELS +                   \
             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
             (MAC_DMA_CHANNEL_SPACING*(chan)))

#define R_MAC_DMA_CHANNEL_BASE(txrx,chan)    \
             (R_MAC_DMA_CHANNELS +                   \
             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
             (MAC_DMA_CHANNEL_SPACING*(chan)))

#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg)           \
            (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) +    \
            (reg))

#define R_MAC_DMA_REGISTER(txrx,chan,reg)           \
            (R_MAC_DMA_CHANNEL_BASE(txrx,chan) +    \
            (reg))

/* 
 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
 */

#define R_MAC_DMA_CONFIG0               0x00000000
#define R_MAC_DMA_CONFIG1               0x00000008
#define R_MAC_DMA_DSCR_BASE             0x00000010
#define R_MAC_DMA_DSCR_CNT              0x00000018
#define R_MAC_DMA_CUR_DSCRA             0x00000020
#define R_MAC_DMA_CUR_DSCRB             0x00000028
#define R_MAC_DMA_CUR_DSCRADDR          0x00000030

/*
 * RMON Counters
 */

#define R_MAC_RMON_TX_BYTES             0x00000000
#define R_MAC_RMON_COLLISIONS           0x00000008
#define R_MAC_RMON_LATE_COL             0x00000010
#define R_MAC_RMON_EX_COL               0x00000018
#define R_MAC_RMON_FCS_ERROR            0x00000020
#define R_MAC_RMON_TX_ABORT             0x00000028
/* Counter #6 (0x30) now reserved */
#define R_MAC_RMON_TX_BAD               0x00000038
#define R_MAC_RMON_TX_GOOD              0x00000040
#define R_MAC_RMON_TX_RUNT              0x00000048
#define R_MAC_RMON_TX_OVERSIZE          0x00000050
#define R_MAC_RMON_RX_BYTES             0x00000080
#define R_MAC_RMON_RX_MCAST             0x00000088
#define R_MAC_RMON_RX_BCAST             0x00000090
#define R_MAC_RMON_RX_BAD               0x00000098
#define R_MAC_RMON_RX_GOOD              0x000000A0
#define R_MAC_RMON_RX_RUNT              0x000000A8
#define R_MAC_RMON_RX_OVERSIZE          0x000000B0
#define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
#define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
#define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
#define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0

/* Updated to spec 0.2 */
#define R_MAC_CFG                       0x00000100
#define R_MAC_THRSH_CFG                 0x00000108
#define R_MAC_VLANTAG                   0x00000110
#define R_MAC_FRAMECFG                  0x00000118
#define R_MAC_EOPCNT                    0x00000120
#define R_MAC_FIFO_PTRS                 0x00000130
#define R_MAC_ADFILTER_CFG              0x00000200
#define R_MAC_ETHERNET_ADDR             0x00000208
#define R_MAC_PKT_TYPE                  0x00000210
#define R_MAC_HASH_BASE                 0x00000240
#define R_MAC_ADDR_BASE                 0x00000280
#define R_MAC_CHUP0_BASE                0x00000300
#define R_MAC_CHLO0_BASE                0x00000320
#define R_MAC_ENABLE                    0x00000400
#define R_MAC_STATUS                    0x00000408
#define R_MAC_INT_MASK                  0x00000410
#define R_MAC_TXD_CTL                   0x00000420
#define R_MAC_MDIO                      0x00000428
#define R_MAC_DEBUG_STATUS              0x00000448