📄 nvr4131.h
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/* nvr4131.h - NEC NVR4131 header file *//* Copyright 2002 Wind River Systems, Inc. *//*modification history--------------------01c,20jun02,sru Added constants for cache control (SPR 78924).01b,12mar02,sru added VR4131_PCICLKSEL_DIV_3 and VR4131_PCIDMACTRLREG.01a,10oct01,sru created, based upon nvr4122.h*//*DESCRIPTIONThis file contains constants for the NEC Vr4131. Register addressdefinitions for the various subsystems are provided, and some (butnot all) register field definitions are provided.*/#ifndef __INCnvr4131h#define __INCnvr4131h#include "vxWorks.h"#ifdef __cplusplusextern "C" {#endif/* VR4131 cache sizes */#define VR4131_ICACHE_SIZE 16384#define VR4131_DCACHE_SIZE 16384/* VR4131 cache line configuration (config bits in C0_CONFIG) */#define VR4131_ICACHE_LINE_32_MASK (1 << 5)#define VR4131_DCACHE_LINE_32_MASK (1 << 4)#define VR4131_CACHE_LINE_SIZE_16 16#define VR4131_CACHE_LINE_SIZE_32 32/* VR4131 register definitions. */#define VR4131_REG_BASE (0x0f000000+K1BASE)#ifdef _ASMLANGUAGE#define VR4131_REG32(reg) (VR4131_REG_BASE + (reg))#define VR4131_REG16(reg) (VR4131_REG_BASE + (reg))#define VR4131_REG8(reg) (VR4131_REG_BASE + (reg))#else#define VR4131_REG32(reg) ((volatile UINT32 *)(VR4131_REG_BASE + (reg)))#define VR4131_REG16(reg) ((volatile UINT16 *)(VR4131_REG_BASE + (reg)))#define VR4131_REG8(reg) ((volatile UINT8 *)(VR4131_REG_BASE + (reg)))#endif /* _ASMLANGUAGE *//* BCU registers */#define VR4131_BCUCNTREG1 VR4131_REG16(0x00)#define VR4131_ROMSIZEREG VR4131_REG16(0x04)#define VR4131_ROMSPEEDREG VR4131_REG16(0x06)#define VR4131_IO0SPEEDREG VR4131_REG16(0x08)#define VR4131_IO1SPEEDREG VR4131_REG16(0x0a)#define VR4131_REVIDREG VR4131_REG16(0x10)#define VR4131_CLKSPEEDREG VR4131_REG16(0x14)#define VR4131_BCUCNTREG3 VR4131_REG16(0x16)#define VR4131_BCUCACHECNTREG VR4131_REG16(0x18)/* BCUCNTREG1 bit definitions */#define VR4131_PAGESIZE 0x3000#define VR4131_PAGEROM2 0x0400#define VR4131_PAGEROM0 0x0100#define VR4131_ROMWEN2 0x0040#define VR4131_ROMWEN0 0x0010/* DMAAU registers */#define VR4131_CSIIBALREG VR4131_REG16(0x20)#define VR4131_CSIIBAHREG VR4131_REG16(0x22)#define VR4131_CSIIALREG VR4131_REG16(0x24)#define VR4131_CSIIAHREG VR4131_REG16(0x26)#define VR4131_CSIOBALREG VR4131_REG16(0x28)#define VR4131_CSIOBAHREG VR4131_REG16(0x2a)#define VR4131_CSIOALREG VR4131_REG16(0x2c)#define VR4131_CSIOAHREG VR4131_REG16(0x2e)#define VR4131_FIRBALREG VR4131_REG16(0x30)#define VR4131_FIRBAHREG VR4131_REG16(0x32)#define VR4131_FIRALREG VR4131_REG16(0x34)#define VR4131_FIRAHREG VR4131_REG16(0x36)#define VR4131_RAMBALREG VR4131_REG16(0x1e0)#define VR4131_RAMBAHREG VR4131_REG16(0x1e2)#define VR4131_RAMALREG VR4131_REG16(0x1e4)#define VR4131_RAMAHREG VR4131_REG16(0x1e6)#define VR4131_IOBALREG VR4131_REG16(0x1e8)#define VR4131_IOBAHREG VR4131_REG16(0x1ea)#define VR4131_IOALREG VR4131_REG16(0x1ec)#define VR4131_IOAHREG VR4131_REG16(0x1ee)/* DCU registers */#define VR4131_DMARSTREG VR4131_REG16(0x40)#define VR4131_DMAIDLEREG VR4131_REG16(0x42)#define VR4131_DMASENREG VR4131_REG16(0x44)#define VR4131_DMAMSKREG VR4131_REG16(0x46)#define VR4131_DMAREQREG VR4131_REG16(0x48)#define VR4131_TDREG VR4131_REG16(0x4a)#define VR4131_DMAABITREG VR4131_REG16(0x4c)#define VR4131_CONTROLREG VR4131_REG16(0x4e)#define VR4131_BASSCNTLREG VR4131_REG16(0x50)#define VR4131_BASSCNTHREG VR4131_REG16(0x52)#define VR4131_CURRENTCNTLREG VR4131_REG16(0x54)#define VR4131_CURRENTCNTHREG VR4131_REG16(0x56)#define VR4131_TCINTR VR4131_REG16(0x58)/* DMA mask bit definitions */#define VR4131_DMAMSKAIOR 0x0008#define VR4131_DMAMSKCOUT 0x0004#define VR4131_DMAMSKCIN 0x0002#define VR4131_DMAMSKFOUT 0x0001/* CMU register */#define VR4131_CMUCLKMSK VR4131_REG16(0x60)#define VR4131_MSKPCIU 0x2080#define VR4131_MSKSCSI 0x1000#define VR4131_MSKDSIU 0x0800#define VR4131_MSKFFIR 0x0400#define VR4131_MSKSSIU 0x0100#define VR4131_MSKCSI 0x0040#define VR4131_MSKFIR 0x0010#define VR4131_MSKSIU 0x0002/* ICU system and system mask registers */#define VR4131_SYSINT1REG VR4131_REG16(0x80)#define VR4131_GIUINTLREG VR4131_REG16(0x88)#define VR4131_DSIUINTREG VR4131_REG16(0x8a)#define VR4131_MSYSINT1REG VR4131_REG16(0x8c)#define VR4131_MGIUINTLREG VR4131_REG16(0x94)#define VR4131_MDSIUINTREG VR4131_REG16(0x96)#define VR4131_NMIREG VR4131_REG16(0x98)#define VR4131_SOFTINTREG VR4131_REG16(0x9a)#define VR4131_SYSINT2REG VR4131_REG16(0xa0)#define VR4131_GIUINTHREG VR4131_REG16(0xa2)#define VR4131_FIRINTREG VR4131_REG16(0xa4)#define VR4131_MSYSINT2REG VR4131_REG16(0xa6)#define VR4131_MGIUINTHREG VR4131_REG16(0xa8)#define VR4131_MFIRINTREG VR4131_REG16(0xaa)#define VR4131_PCIINTREG VR4131_REG16(0xac)#define VR4131_SCUINTREG VR4131_REG16(0xae)#define VR4131_CSIINTREG VR4131_REG16(0xb0)#define VR4131_MPCIINTREG VR4131_REG16(0xb2)#define VR4131_MSCUINTREG VR4131_REG16(0xb4)#define VR4131_MCSIINTREG VR4131_REG16(0xb6)#define VR4131_BCUINTREG VR4131_REG16(0xb8)#define VR4131_MBCUINTREG VR4131_REG16(0xba)#define VR4131_CLKRUNINTR 0x1000#define VR4131_SOFTINTR 0x0800#define VR4131_SIUINTR 0x0200#define VR4131_GIUINTR 0x0100#define VR4131_ETIMERINTR 0x0008#define VR4131_RTCL1INTR 0x0004#define VR4131_POWERINTR 0x0002#define VR4131_BATINTR 0x0001#define VR4131_BCUINTR 0x0200#define VR4131_CSIINTR 0x0100#define VR4131_SCUINTR 0x0080#define VR4131_PCIINTR 0x0040#define VR4131_DSIUINTR 0x0020#define VR4131_FIRINTR 0x0010#define VR4131_TCLKINTR 0x0008#define VR4131_LEDINTR 0x0002#define VR4131_RTCL2INTR 0x0001/* PMU registers */#define VR4131_PMUINTREG VR4131_REG16(0xc0)#define VR4131_PMUCNTREG VR4131_REG16(0xc2)#define VR4131_PMUINT2REG VR4131_REG16(0xc4)#define VR4131_PMUCNT2REG VR4131_REG16(0xc6)#define VR4131_PMUWAITREG VR4131_REG16(0xc8)#define VR4131_PMUTCLKDIVREG VR4131_REG16(0xcc)#define VR4131_PMUINTRCLKDIVREG VR4131_REG16(0xce)#define VR4131_HALTIMERRST 0x0004/* RTC registers */#define VR4131_ETIMELREG VR4131_REG16(0x100)#define VR4131_ETIMEMREG VR4131_REG16(0x102)#define VR4131_ETIMEHREG VR4131_REG16(0x104)#define VR4131_ECMPLREG VR4131_REG16(0x108)#define VR4131_ECMPMREG VR4131_REG16(0x10a)#define VR4131_ECMPHREG VR4131_REG16(0x10c)#define VR4131_RTCL1LREG VR4131_REG16(0x110)#define VR4131_RTCL1HREG VR4131_REG16(0x112)#define VR4131_RTCL1CNTLREG VR4131_REG16(0x114)#define VR4131_RTCL1CNTHREG VR4131_REG16(0x116)#define VR4131_RTCL2LREG VR4131_REG16(0x118)#define VR4131_RTCL2HREG VR4131_REG16(0x11a)#define VR4131_RTCL2CNTLREG VR4131_REG16(0x11c)#define VR4131_RTCL2CNTHREG VR4131_REG16(0x11e)#define VR4131_TCLKLREG VR4131_REG16(0x120)#define VR4131_TCLKHREG VR4131_REG16(0x122)#define VR4131_TCLKCNTLREG VR4131_REG16(0x124)#define VR4131_TCLKCNTHREG VR4131_REG16(0x126)#define VR4131_RTCINTREG VR4131_REG16(0x13e)#define VR4131_RTCINTR0 0x0001#define VR4131_RTCINTR1 0x0002#define VR4131_RTCINTR2 0x0004#define VR4131_RTCINTR3 0x0008/* * The VR4131 RTC module has identical functionality to the VR4102 * RTC module. In order to use the nvr4102RTCTimer.c driver, we must * define the VR4102_... constants in terms of the VR4131 values. */#define VR4102_ETIMELREG VR4131_ETIMELREG#define VR4102_ETIMEMRE VR4131_ETIMEMRE#define VR4102_ETIMEHREG VR4131_ETIMEHREG#define VR4102_ECMPLREG VR4131_ECMPLREG#define VR4102_ECMPMREG VR4131_ECMPMREG#define VR4102_ECMPHREG VR4131_ECMPHREG#define VR4102_RTCL1LREG VR4131_RTCL1LREG#define VR4102_RTCL1HREG VR4131_RTCL1HREG#define VR4102_RTCL1CNTLREG VR4131_RTCL1CNTLREG#define VR4102_RTCL1CNTHREG VR4131_RTCL1CNTHREG#define VR4102_RTCL2LREG VR4131_RTCL2LREG⌨️ 快捷键说明
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