m68332.h

IXP425的BSP代码

#define QSM_SCSR_TC		0x0080	/* transmit complete */
#define QSM_SCSR_TDRE		0x0100	/* transmit date register empty flag */

/* QSM_QPDR/QSM_QDDR - Port Data and Data Direction Register */

#define QSM_QPDR_MISO		0x01	/* MISO pin */
#define QSM_QPDR_MOSI		0x02	/* MOSI pin */
#define QSM_QPDR_SCK		0x04	/* SCK pin */
#define QSM_QPDR_PCS0		0x08	/* PCS0 pin */
#define QSM_QPDR_PCS1		0x10	/* PCS1 pin */
#define QSM_QPDR_PCS2		0x20	/* PCS2 pin */
#define QSM_QPDR_PCS3		0x40	/* PCS3 pin */
#define QSM_QPDR_TXD		0x80	/* TXD pin */

/* QSM_QPAR - Pin Assignment Register */

#define QSM_QPAR_MISO		0x0001	/* MISO pin */
#define QSM_QPAR_MOSI		0x0002	/* MOSI pin */
#define QSM_QPAR_PCS0		0x0008	/* PCS0 pin */
#define QSM_QPAR_PCS1		0x0010	/* PCS1 pin */
#define QSM_QPAR_PCS2		0x0020	/* PCS2 pin */
#define QSM_QPAR_PCS3		0x0040	/* PCS3 pin */

/* QSM_SPCR0 - Serial Peripheral Control Register 0 */

#define QSM_SPCR0_CPHA_CAP	0x0000	/* capture data on leading edge */
#define QSM_SPCR0_CPHA_CHG	0x0100	/* change data on leading edge */
#define QSM_SPCR0_CPOL_LOW	0x0000 	/* clock polarity; SCK inactive low */
#define QSM_SPCR0_CPOL_HIGH	0x0200 	/* clock polarity; SCK inactive high */
#define QSM_SPCR0_WOMQ		0x4000	/* wired or mode */
#define QSM_SPCR0_MASTER	0x8000	/* device as QSM master */
#define QSM_SPCR0_SLAVE		0x0000	/* device as QSM slave */

/* QSM_SPCR1 - Serial Peripheral Control Register 1 */

#define QSM_SPCR1_SPE		0x8000	/* QSPI is enabled */

/* QSM_SPCR2 - Serial Peripheral Control Register 2 */

#define QSM_SPCR2_WRTO		0x2000	/* wrap to NEWQP (0 otherwise) */
#define QSM_SPCR2_WREN		0x4000	/* wrap enabled */
#define QSM_SPCR2_SPIFIE	0x8000	/* finished interrupt enabled */

/* QSM_SPCR3 - Serial Peripheral Control Register 3 */

#define QSM_SPCR3_HALT		0x01	/* halt after current transfer */
#define QSM_SPCR3_HMIE		0x02	/* HALTA or MODF interrupt enable */
#define QSM_SPCR3_LOOPQ		0x04	/* loop back mode */

/* QSM_SPSR - Serial Peripheral Status Register */

#define QSM_SPSR_HALTA		0x20	/* QSPI halted */
#define QSM_SPSR_MODF		0x40	/* mode fault (multiple masters) */
#define QSM_SPSR_SPIF		0x80	/* QSPI executed last command */

/* QSM_SPCCB - Serial Peripheral Command Control Byte */

#define QSM_SPCCB_DSCK		0x10	/* SPCR1 contains PCS setup time */
#define QSM_SPCCB_DT		0x20	/* SPCR1 contains inter-trans delay */
#define QSM_SPCCB_BITSE		0x40	/* SPCR0 contains number of bits */
#define QSM_SPCCB_CONT		0x80	/* continue to assert PCS after trans */


/* TPU - Time Processing Unit */

/* Channel control options */

#define CHN_PSC_PAC		0x0000	/* force pin to PAC latches */
#define CHN_PSC_HIGH		0x0001	/* force pin high */
#define CHN_PSC_LOW		0x0002	/* force pin low */
#define CHN_PSC_NC		0x0003	/* do not force any state */
#define CHN_PAC_NCM		0x0000	/* no change on match */
#define CHN_PAC_NO_DETECT	0x0000	/* do not detect transition */
#define CHN_PAC_HIGH		0x0004	/* high on match */
#define CHN_PAC_RISING		0x0004	/* detect rising edge */
#define CHN_PAC_LOW		0x0008	/* low on match */
#define CHN_PAC_FALLING		0x0008	/* detect falling edge */
#define CHN_PAC_TOGGLE		0x000c	/* toggle on match */
#define CHN_PAC_EITHER		0x000c	/* detect either edge transition */
#define CHN_PAC_NC		0x0010	/* don not change PAC */
#define CHN_TBS_INP_C1_M1	0x0000	/* input - capture TCR1, match TCR1 */
#define CHN_TBS_INP_C1_M2	0x0020	/* input - capture TCR1, match TCR2 */
#define CHN_TBS_INP_C2_M1	0x0040	/* input - capture TCR2, match TCR1 */
#define CHN_TBS_INP_C2_M2	0x0060	/* input - capture TCR2, match TCR2 */
#define CHN_TBS_OUT_C1_M1	0x0080	/* output - capture TCR1, match TCR1 */
#define CHN_TBS_OUT_C1_M2	0x00a0	/* output - capture TCR1, match TCR2 */
#define CHN_TBS_OUT_C2_M1	0x00c0	/* output - capture TCR2, match TCR1 */
#define CHN_TBS_OUT_C2_M2	0x00e0	/* output - capture TCR2, match TCR2 */
#define CHN_TBS_NC		0x0100	/* do not change TBS */

typedef struct		/* TPU_DIO */
    {
    UINT16	chnCont;
    UINT16	pinLvl;
    UINT16	matchRate;
    } TPU_DIO;

/* DIO_HSQR - Host Sequence Register */

#define DIO_HSQR_TRANS		0x0	/* record pin on transition */
#define DIO_HSQR_MATCH		0x1	/* record pin at matchRate */
#define DIO_HSQR_RECORD		0x2	/* record pin on HSRR = 0x3 */

/* DIO_HSRR - Host Service Register */

#define DIO_HSRR_NONE		0x0	/* none */
#define DIO_HSRR_HIGH		0x1	/* force output high */
#define DIO_HSRR_LOW		0x2	/* force output low */
#define DIO_HSRR_INIT		0x3	/* initialization */

typedef struct		/* TPU_ITC */
    {
    UINT16	chnCont;
    UINT16	linkBankAdrs;
    UINT16	maxCount;
    UINT16	transCount;
    UINT16	finalTransTime;
    UINT16	lastTransTime;
    } TPU_ITC;

/* ITC_HSQR - Host Sequence Register */

#define ITC_HSQR_SNGL		0x0	/* no link, single mode */
#define ITC_HSQR_CONT		0x1	/* no link, continuous mode */
#define ITC_HSQR_LINK_SNGL	0x2	/* link, single mode */
#define ITC_HSQR_LINK_CONT	0x3	/* link, continuous mode */

/* ITC_HSRR - Host Service Register */

#define ITC_HSRR_NONE		0x0	/* none */
#define ITC_HSRR_INIT		0x1	/* initialization */

typedef struct		/* TPU_OC */
    {
    UINT16	chnCont;
    UINT16	offset;
    UINT16	ratioRefAddr1;
    UINT16	refAddr2Addr3;
    UINT16	refTime;
    UINT16	matchTime;
    } TPU_OC;

/* OC_HSQR - Host Sequence Register */

#define OC_HSQR_ALL		0x0	/* all pulse mode code executed */
#define OC_HSQR_RESTRICT	0x2	/* pulse mode code 0xec,0xee executed */

/* OC_HSRR - Host Service Register */

#define OC_HSRR_NONE		0x0	/* none */
#define OC_HSRR_HIPM		0x1	/* host initiated pulse mode */
#define OC_HSRR_INIT		0x3	/* initialization */

typedef struct		/* TPU_PWM */
    {
    UINT16	chnCont;
    UINT16	oldris;
    UINT16	pwmhi;
    UINT16	pwmper;
    UINT16	pwmris;
    } TPU_PWM;

/* PWM_HSRR - Host Service Register */

#define PWM_HSRR_NONE		0x0	/* none */
#define PWM_HSRR_UPDATE		0x1	/* immediate update request */
#define PWM_HSRR_INIT		0x2	/* initialization */

typedef struct		/* TPU_SPWM_M0 */
    {
    UINT16	chnCont;
    UINT16	nextRise;
    UINT16	highTime;
    UINT16	period;
    UINT16	refAddr1;
    UINT16 	delay;
    } TPU_SPWM_M0;

typedef struct		/* TPU_SPWM_M1 */
    {
    UINT16	chnCont;
    UINT16	nextRise;
    UINT16	highTime;
    UINT16	delay;
    UINT16	refAddr1Addr2;
    UINT16	refValue;
    } TPU_SPWM_M1;

typedef struct		/* TPU_SPWM_M2 */
    {
    UINT16	chnCont;
    UINT16	nextRise;
    UINT16	highTime;
    UINT16	period;
    UINT16	linkRefAddr1;
    UINT16 	delay;
    } TPU_SPWM_M2;

/* SPWM_HSQR - Host Sequence Register */

#define SPWM_HSQR_MODE0		0x0	/* mode 0 */
#define SPWM_HSQR_MODE1		0x1	/* mode 1 */
#define SPWM_HSQR_MODE2		0x2	/* mode 2 */

/* SPWM_HSRR - Host Service Register */

#define SPWM_HSRR_NONE		0x0	/* none */
#define SPWM_HSRR_INIT		0x2	/* initialization */
#define SPWM_HSRR_UPDATE	0x3	/* immediate update request */

typedef struct		/* TPU_PMA */
    {
    UINT16	chnCont;
    UINT16	maxAddNumTeeth;
    UINT16	addRollCnt;
    UINT16	ratioTcrMax;
    UINT16	periodHigh;
    UINT16	periodLow;
    } TPU_PMA;

/* PMA_HSQR - Host Sequence Register */

#define PMA_HSQR_BANK		0x0	/* bank mode */
#define PMA_HSQR_COUNT		0x1	/* count mode */

/* PMA_HSRR - Host Service Register */

#define PMA_HSRR_NONE		0x0	/* none */
#define PMA_HSRR_INIT		0x1	/* initialization */

typedef struct		/* TPU_PMM */
    {
    UINT16	chnCont;
    UINT16	maxMissNumTeeth;
    UINT16	missRollCnt;
    UINT16	ratioTcrMax;
    UINT16	periodHigh;
    UINT16	periodLow;
    } TPU_PMM;

/* PMM_HSQR - Host Sequence Register */

#define PMM_HSQR_BANK		0x2	/* bank mode */
#define PMM_HSQR_COUNT		0x3	/* count mode */

/* PMM_HSRR - Host Service Register */

#define PMM_HSRR_NONE		0x0	/* none */
#define PMM_HSRR_INIT		0x1	/* initialization */

typedef struct		/* TPU_PSP */
    {
    UINT16	chnCont;
    UINT16	r2A2Tmp;
    UINT16	angleTime;
    UINT16	ratioTmp;
    UINT16	ratioAngle1;
    UINT16	ratioAngle2;
    } TPU_PSP;

/* PSP_HSQR - Host Sequence Register */

#define PSP_HSQR_ANGLE		0x0	/* angle-angle mode */
#define PSP_HSQR_TIME		0x1	/* angle-time mode */

/* PSP_HSRR - Host Service Register */

#define PSP_HSRR_NONE		0x0	/* none */
#define PSP_HSRR_UPDATE		0x1	/* immediate update request */
#define PSP_HSRR_INIT		0x2	/* initialization */
#define PSP_HSRR_FORCE		0x3	/* force mode */

typedef struct		/* TPU_SM_PRI */
    {
    UINT16	chnCont;
    UINT16	pinCont;
    UINT16	currentPos;
    UINT16	desiredPos;
    UINT16	modCntNextStep;
    UINT16	stepCntLastChn;
    } TPU_SM_PRI;

typedef struct		/* TPU_SM_SEC */
    {
    UINT16	chnCont;
    UINT16	pinCont;
    UINT16	stepCntl0;
    UINT16	stepCntl1;
    } TPU_SM_SEC;

/* SM_HSRR - Host Service Register */

#define SM_HSRR_NONE		0x0	/* none */
#define SM_HSRR_INIT		0x2	/* initialization */
#define SM_HSRR_STEP		0x3	/* step request */

typedef struct		/* TPU_PPWA */
    {
    UINT16	chnCont;
    UINT16	maxPeriodCnt;
    UINT16	lastAccum;
    UINT16	accum;
    UINT16	accumRatePpwaUb;
    UINT16	ppwaLw;
    } TPU_PPWA;

/* PPWA_HSQR - Host Sequence Register */

#define PPWA_HSQR_ACC_24	0x0	/* accumulate 24 bit periods */
#define PPWA_HSQR_ACC_16	0x1	/* accumulate 16 bit periods */

/* PPWA_HSRR - Host Service Register */

#define PPWA_HSRR_NONE		0x0	/* none */
#define PPWA_HSRR_INIT		0x2	/* initialization */

typedef struct		/* TPU_CHN */
    {
    union
	{
	TPU_DIO		dio;		/* discrete input/output */
	TPU_ITC		itc;		/* input transition counter */
	TPU_OC		oc;		/* output compare */
	TPU_PWM		pwm;		/* pulse width modulation */
	TPU_SPWM_M0	spwmM0;		/* synchronized pulse width modulation*/
	TPU_SPWM_M1	spwmM1;		/* synchronized pulse width modulation*/
	TPU_SPWM_M2	spwmM2;		/* synchronized pulse width modulation*/
	TPU_PMA		pma;		/* period measure w/additional trans */
	TPU_PMM		pmm;		/* period measure w/missing trans */
	TPU_PSP		psp;		/* position-sync. pulse generator */
	TPU_SM_PRI	smPri;		/* stepper motor primary channel */
	TPU_SM_SEC	smSec;		/* stepper motor secondary channel */
	TPU_PPWA	ppwa;		/* period/pulse width accumulator */
	UINT16		pad[8];		/* each channel has 8 parameters */
	} tf;
    } TPU_CHN;

/* TPU_TMCR - TPU Module Configuration Register */

#define TPU_TMCR_PSCK_32X	0x0000	/* clock/32 is TCR1 prescaler input */
#define TPU_TMCR_PSCK_4X	0x0040	/* clock/4 is TCR1 prescaler input */
#define TPU_TMCR_SUPV		0x0080	/* supervisor access only */
#define TPU_TMCR_STF		0x0100	/* TPU is stopped */
#define TPU_TMCR_T2CG		0x0200	/* TCR2 pin is gate of DIV8 clock */
#define TPU_TMCR_EMU		0x0400	/* TPU and RAM in emulation mode */
#define TPU_TMCR_TCR2_1X	0x0000	/* TCR2 divide by 1 prescaler */
#define TPU_TMCR_TCR2_2X	0x0800	/* TCR2 divide by 2 prescaler */
#define TPU_TMCR_TCR2_4X	0x1000	/* TCR2 divide by 4 prescaler */
#define TPU_TMCR_TCR2_8X	0x1800	/* TCR2 divide by 8 prescaler */
#define TPU_TMCR_TCR1_1X	0x0000	/* TCR1 divide by 1 prescaler */
#define TPU_TMCR_TCR1_2X	0x2000	/* TCR1 divide by 2 prescaler */
#define TPU_TMCR_TCR1_4X	0x4000	/* TCR1 divide by 4 prescaler */
#define TPU_TMCR_TCR1_8X	0x6000	/* TCR1 divide by 8 prescaler */
#define TPU_TMCR_STOP		0x8000	/* stop the clocks and microengine */

/* TPU_CFSR - Channel Function Select Register */

#define TPU_CFSR_DIO		0x8 	/* discrete input/output */
#define TPU_CFSR_ITC		0xa	/* input transition counter */
#define TPU_CFSR_OC		0xe	/* output compare */
#define TPU_CFSR_PWM		0x9	/* pulse width modulation */
#define TPU_CFSR_SPWM		0x7	/* synchronized pulse width modulation*/
#define TPU_CFSR_PMA		0xb	/* period measure w/additional trans */
#define TPU_CFSR_PMM		0xb	/* period measure w/missing trans */
#define TPU_CFSR_PSP		0xc	/* position-sync. pulse generator */
#define TPU_CFSR_SM		0xd	/* stepper motor */
#define TPU_CFSR_PPWA		0xf	/* period/pulse width accumulator */

/* TPU_CPR - Channel Priority Register */

#define TPU_CPR_DISABLE		0x0	/* channel disabled */
#define TPU_CPR_LOW		0x1	/* low priority */
#define TPU_CPR_MEDIUM		0x2	/* medium priority */
#define TPU_CPR_HIGH		0x3	/* high priority */

/* function declarations */

#ifndef INCLUDE_TY_CO_DRV_50
#if defined(__STDC__) || defined(__cplusplus)

IMPORT  void    tyCoInt (void);

#else   /* __STDC__ */

IMPORT  void    tyCoInt ();

#endif  /* __STDC__ */
#endif  /* INCLUDE_TY_CO_DRV_50 */

#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCm68332h */