m68332.h

IXP425的BSP代码

/* m68332.h - Motorola MC68332 CPU control registers */

/* Copyright 1984-1992 Wind River Systems, Inc. */
/*
modification history
--------------------
01m,20dec96,dat  fixed SPR 4225, M332_RAM_RAMBAR was incorrect
01l,24oct92,jcf  fixed TPU defines.
01k,22sep92,rrr  added support for c++
01j,02jul92,caf  added TY_CO_DEV and function declarations for 5.1 upgrade.
		 for 5.0.x compatibility, define INCLUDE_TY_CO_DRV_50 when
		 including this header.
01e,26may92,rrr  the tree shuffle
01d,22jan92,caf  fixed M332_QSM_CMD_BASE, QSM_QILR_SPI_MASK and SIM_CSOR_IPL.
01c,04oct91,rrr  passed through the ansification filter
		  -fixed #else and #endif
		  -changed ASMLANGUAGE to _ASMLANGUAGE
		  -changed copyright notice
01b,30sep91,caf  added _ASMLANGUAGE conditional.
01a,13feb91,jcf	 based on Tektronix original.
*/

/*
This file contains I/O address and related constants for the MC68332.
*/

#ifndef __INCm68332h
#define __INCm68332h

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "tyLib.h"

#ifndef  INCLUDE_TY_CO_DRV_50

typedef struct		/* TY_CO_DEV */
    {
    TY_DEV	tyDev;
    BOOL	created;	/* true if this device has been created */
    int		baudFreq;	/* system clock frequency */
    } TY_CO_DEV;

#endif	/* INCLUDE_TY_CO_DRV_50 */

/* MC68332 parameter register addresses */

#define M332_SIM_MCR		((UINT16 *) 0xfffa00)
#define M332_SIM_SIMTR		((UINT16 *) 0xfffa02)
#define M332_SIM_SYNCR		((UINT16 *) 0xfffa04)
#define M332_SIM_RSR		((UINT8  *) 0xfffa07)
#define M332_SIM_SIMTRE		((UINT16 *) 0xfffa08)
#define M332_SIM_PORTE		((UINT8  *) 0xfffa11)
#define M332_SIM_DDRE		((UINT8  *) 0xfffa15)
#define M332_SIM_PEPAR		((UINT8  *) 0xfffa17)
#define M332_SIM_PORTF		((UINT8  *) 0xfffa19)
#define M332_SIM_DDRF		((UINT8  *) 0xfffa1d)
#define M332_SIM_PFPAR		((UINT8  *) 0xfffa1f)
#define M332_SIM_SYPCR		((UINT8  *) 0xfffa21)
#define M332_SIM_PICR		((UINT16 *) 0xfffa22)
#define M332_SIM_PITR		((UINT16 *) 0xfffa24)
#define M332_SIM_SWSR		((UINT8  *) 0xfffa27)
#define M332_SIM_TSTMSRA	((UINT16 *) 0xfffa30)
#define M332_SIM_TSTMSRB	((UINT16 *) 0xfffa32)
#define M332_SIM_TSTSC		((UINT16 *) 0xfffa34)
#define M332_SIM_TSTRC		((UINT16 *) 0xfffa36)
#define M332_SIM_CREG		((UINT16 *) 0xfffa38)
#define M332_SIM_DREG		((UINT16 *) 0xfffa3a)
#define M332_SIM_PORTC		((UINT8  *) 0xfffa41)
#define M332_SIM_CSPAR0		((UINT16 *) 0xfffa44)
#define M332_SIM_CSPAR1		((UINT16 *) 0xfffa46)
#define M332_SIM_CSBOOT		((SIM_CS *) 0xfffa48)
#define M332_SIM_CS0		((SIM_CS *) 0xfffa4c)
#define M332_SIM_CS1		((SIM_CS *) 0xfffa50)
#define M332_SIM_CS2		((SIM_CS *) 0xfffa54)
#define M332_SIM_CS3		((SIM_CS *) 0xfffa58)
#define M332_SIM_CS4		((SIM_CS *) 0xfffa5c)
#define M332_SIM_CS5		((SIM_CS *) 0xfffa60)
#define M332_SIM_CS6		((SIM_CS *) 0xfffa64)
#define M332_SIM_CS7		((SIM_CS *) 0xfffa68)
#define M332_SIM_CS8		((SIM_CS *) 0xfffa6c)
#define M332_SIM_CS9		((SIM_CS *) 0xfffa70)
#define M332_SIM_CS10		((SIM_CS *) 0xfffa74)
#define M332_RAM_RAMMCR		((UINT16 *) 0xfffb00)
#define M332_RAM_RAMTST		((UINT16 *) 0xfffb02)
#define M332_RAM_RAMBAR		((UINT16 *) 0xfffb04)
#define M332_QSM_QMCR		((UINT16 *) 0xfffc00)
#define M332_QSM_QTEST		((UINT16 *) 0xfffc02)
#define M332_QSM_QILR		((UINT8  *) 0xfffc04)
#define M332_QSM_QIVR		((UINT8  *) 0xfffc05)
#define M332_QSM_SCCR0		((UINT16 *) 0xfffc08)
#define M332_QSM_SCCR1		((UINT16 *) 0xfffc0a)
#define M332_QSM_SCSR		((UINT16 *) 0xfffc0c)
#define M332_QSM_SCDR		((UINT16 *) 0xfffc0e)
#define M332_QSM_QPDR		((UINT8  *) 0xfffc15)
#define M332_QSM_QPAR		((UINT8  *) 0xfffc16)
#define M332_QSM_QDDR		((UINT8  *) 0xfffc17)
#define M332_QSM_SPCR0		((UINT16 *) 0xfffc18)
#define M332_QSM_SPCR1		((UINT16 *) 0xfffc1a)
#define M332_QSM_SPCR2		((UINT16 *) 0xfffc1c)
#define M332_QSM_SPCR3		((UINT8  *) 0xfffc1e)
#define M332_QSM_SPSR		((UINT8  *) 0xfffc1f)
#define M332_QSM_RX_BASE	((UINT16 *) 0xfffd00)
#define M332_QSM_TX_BASE	((UINT16 *) 0xfffd20)
#define M332_QSM_CMD_BASE	((UINT8  *) 0xfffd40)
#define M332_TPU_TMCR		((UINT16 *) 0xfffe00)
#define M332_TPU_TTCR		((UINT16 *) 0xfffe02)
#define M332_TPU_DSCR		((UINT16 *) 0xfffe04)
#define M332_TPU_DSSR		((UINT16 *) 0xfffe06)
#define M332_TPU_TICR		((UINT16 *) 0xfffe08)
#define M332_TPU_CIER		((UINT16 *) 0xfffe0a)
#define M332_TPU_CFSR0		((UINT16 *) 0xfffe0c)
#define M332_TPU_CFSR1		((UINT16 *) 0xfffe0e)
#define M332_TPU_CFSR2		((UINT16 *) 0xfffe10)
#define M332_TPU_CFSR3		((UINT16 *) 0xfffe12)
#define M332_TPU_HSQR0		((UINT16 *) 0xfffe14)
#define M332_TPU_HSQR1		((UINT16 *) 0xfffe16)
#define M332_TPU_HSRR0		((UINT16 *) 0xfffe18)
#define M332_TPU_HSRR1		((UINT16 *) 0xfffe1a)
#define M332_TPU_CPR0		((UINT16 *) 0xfffe1c)
#define M332_TPU_CPR1		((UINT16 *) 0xfffe1e)
#define M332_TPU_CISR		((UINT16 *) 0xfffe20)
#define M332_TPU_CHN		((TPU_CHN *) 0xffff00)


/* SIM - Register definitions for the System Integration Module */

typedef struct		/* SIM_CS */
    {
    UINT16 csBar;		/* chip select base address register */
    UINT16 csOr;		/* chip select options register */
    } SIM_CS;

/* SIM_MCR - Module Configuration Register (Write Once Only) */

#define SIM_MCR_MM		0x0040	/* module mapping */
#define SIM_MCR_SUPV		0x0080	/* supervisor/unrestricted data space */
#define SIM_MCR_X		0x0000	/* no show cycle, ext. arbitration */
#define SIM_MCR_SH		0x0100	/* show cycle enabled, no ext. arb. */
#define SIM_MCR_SH_X		0x0200	/* show cycle enabled, ext. arb. */
#define SIM_MCR_SH_X_BG		0x0300	/* show cycle/ext arb; int halt w/ BG */
#define SIM_MCR_SLVEN		0x0800	/* slave mode enable */
#define SIM_MCR_FRZBM		0x2000	/* freeze bus monitor enable */
#define SIM_MCR_FRZSW		0x4000	/* freeze software enable */
#define SIM_MCR_EXOFF		0x8000	/* external clock off */

/* SIM_SIMTR - Module Test Register */

#define SIM_SIMTR_REV_MASK	0xfc00	/* revision number for this part */

/* SIM_SYNCR - Clock Synthesis Control Register */

#define SIM_SYNCR_STEXT		0x0001	/* stop mode external clock */
#define SIM_SYNCR_STSIM		0x0002	/* stop mode system integration clock */
#define SIM_SYNCR_RSTEN		0x0004	/* reset enable */
#define SIM_SYNCR_SLOCK		0x0008	/* synthesizer lock */
#define SIM_SYNCR_SLIMP		0x0010	/* limp mode */
#define SIM_SYNCR_EDIV 		0x0080	/* E clock divide rate */
#define SIM_SYNCR_Y_MASK 	0x3f00	/* Y - frequency control bits */
#define SIM_SYNCR_X    		0x4000	/* X - frequency control bit */
#define SIM_SYNCR_W    		0x8000	/* W - frequency control bit */

/* SIM_RSR - Reset Status Register */

#define SIM_RSR_TST		0x01	/* test submodule reset	*/
#define SIM_RSR_SYS		0x02	/* system reset (CPU reset) */
#define SIM_RSR_LOC		0x04	/* loss of clock reset */
#define SIM_RSR_HLT		0x10	/* halt monitor reset */
#define SIM_RSR_SW		0x20	/* software watchdog reset */
#define SIM_RSR_POW		0x40	/* power up reset */
#define SIM_RSR_EXT		0x80	/* external reset */

/* SIM_PEPAR - Port E Pin Assignment Register */

#define SIM_PEPAR_DSACK0	0x01	/* select bus control pin assignment */
#define SIM_PEPAR_DSACK1	0x02	/* select bus control pin assignment */
#define SIM_PEPAR_AVEC		0x04	/* select bus control pin assignment */
#define SIM_PEPAR_RMC		0x08	/* select bus control pin assignment */
#define SIM_PEPAR_DS		0x10	/* select bus control pin assignment */
#define SIM_PEPAR_AS		0x20	/* select bus control pin assignment */
#define SIM_PEPAR_SIZ0		0x40	/* select bus control pin assignment */
#define SIM_PEPAR_SIZ1		0x80	/* select bus control pin assignment */

/* SIM_PFPAR - Port F Pin Assignment Register */

#define SIM_PFPAR_MODCK		0x01	/* select bus control pin assignment */
#define SIM_PFPAR_IRQ1		0x02	/* select bus control pin assignment */
#define SIM_PFPAR_IRQ2		0x04	/* select bus control pin assignment */
#define SIM_PFPAR_IRQ3		0x08	/* select bus control pin assignment */
#define SIM_PFPAR_IRQ4		0x10	/* select bus control pin assignment */
#define SIM_PFPAR_IRQ5		0x20	/* select bus control pin assignment */
#define SIM_PFPAR_IRQ6		0x40	/* select bus control pin assignment */
#define SIM_PFPAR_IRQ7		0x80	/* select bus control pin assignment */

/* SIM_SYPCR - System Protection Control (Write Once Only) */

#define SIM_SYPCR_BMT_64	0x00	/* 64 clk cycle bus monitor timeout */
#define SIM_SYPCR_BMT_32	0x01	/* 32 clk cycle bus monitor timeout */
#define SIM_SYPCR_BMT_16	0x02	/* 16 clk cycle bus monitor timeout */
#define SIM_SYPCR_BMT_8		0x03	/* 8 clk cycle bus monitor timeout */
#define SIM_SYPCR_BME		0x04	/* bus monitor enable */
#define SIM_SYPCR_HME		0x08	/* halt monitor enable */
#define SIM_SYPCR_SWT_9		0x00	/* 2^9 extal cycle software timeout */
#define SIM_SYPCR_SWT_11	0x10	/* 2^11 extal cycle software timeout */
#define SIM_SYPCR_SWT_13	0x20	/* 2^13 extal cycle software timeout */
#define SIM_SYPCR_SWT_15	0x30	/* 2^15 extal cycle software timeout */
#define SIM_SYPCR_SWT_18	0x40	/* 2^18 extal cycle software timeout */
#define SIM_SYPCR_SWT_20	0x50	/* 2^20 extal cycle software timeout */
#define SIM_SYPCR_SWT_22	0x60	/* 2^22 extal cycle software timeout */
#define SIM_SYPCR_SWT_24	0x70	/* 2^24 extal cycle software timeout */
#define SIM_SYPCR_SWE		0x80	/* software watchdog enable */

/* SIM_PICR - Periodic Interrupt Control Register */

#define SIM_PICR_PIV_MASK	0x00ff	/* periodic interrupt vector */
#define SIM_PICR_PIRQL_MASK	0x0700	/* periodic interrupt request level */

/* SIM_PITR - Periodic Interrupt Timer */

#define SIM_PITR_PITR_MASK	0x00ff	/* periodic interrupt timing register */
#define SIM_PITR_PTP		0x0100	/* periodic timer prescale bit */

/* SIM_SWSR - Software Service Register */

#define SIM_SWSR_ACK1		0x55	/* software watchdog ack. part 1 */
#define SIM_SWSR_ACK2		0xaa	/* software watchdog ack. part 2 */

/* SIM_CSPAR0 - Chip Select Pin Assignement Register 0 */

#define SIM_CSPAR0_CSBOOT_DIS	0x0000	/* discrete output */
#define SIM_CSPAR0_CSBOOT_DEF	0x0001	/* default pin function */
#define SIM_CSPAR0_CSBOOT_8BIT	0x0002	/* chip select with 8 bit port */
#define SIM_CSPAR0_CSBOOT_16BIT	0x0003	/* chip select with 16 bit port */
#define SIM_CSPAR0_CS0_DIS	0x0000	/* discrete output */
#define SIM_CSPAR0_CS0_BR	0x0004	/* default pin function */
#define SIM_CSPAR0_CS0_8BIT	0x0008	/* chip select with 8 bit port */
#define SIM_CSPAR0_CS0_16BIT	0x000c	/* chip select with 16 bit port */
#define SIM_CSPAR0_CS1_DIS	0x0000	/* discrete output */
#define SIM_CSPAR0_CS1_BG	0x0010	/* default pin function */
#define SIM_CSPAR0_CS1_8BIT	0x0020	/* chip select with 8 bit port */
#define SIM_CSPAR0_CS1_16BIT	0x0030	/* chip select with 16 bit port */
#define SIM_CSPAR0_CS2_DIS	0x0000	/* discrete output */
#define SIM_CSPAR0_CS2_BGACK	0x0040	/* default pin function */
#define SIM_CSPAR0_CS2_8BIT	0x0080	/* chip select with 8 bit port */
#define SIM_CSPAR0_CS2_16BIT	0x00c0	/* chip select with 16 bit port */
#define SIM_CSPAR0_CS3_DIS	0x0000	/* discrete output */
#define SIM_CSPAR0_CS3_FC0	0x0100	/* default pin function */
#define SIM_CSPAR0_CS3_8BIT	0x0200	/* chip select with 8 bit port */
#define SIM_CSPAR0_CS3_16BIT	0x0300	/* chip select with 16 bit port */
#define SIM_CSPAR0_CS4_DIS	0x0000	/* discrete output */
#define SIM_CSPAR0_CS4_FC1	0x0400	/* default pin function */
#define SIM_CSPAR0_CS4_8BIT	0x0800	/* chip select with 8 bit port */
#define SIM_CSPAR0_CS4_16BIT	0x0c00	/* chip select with 16 bit port */
#define SIM_CSPAR0_CS5_DIS	0x0000	/* discrete output */
#define SIM_CSPAR0_CS5_FC2	0x1000	/* default pin function */
#define SIM_CSPAR0_CS5_8BIT	0x2000	/* chip select with 8 bit port */
#define SIM_CSPAR0_CS5_16BIT	0x3000	/* chip select with 16 bit port */

/* SIM_CSPAR1 - Chip Select Pin Assignement Register 1 */

#define SIM_CSPAR1_CS6_DIS	0x0000	/* discrete output */
#define SIM_CSPAR1_CS6_A19	0x0001	/* default pin function */
#define SIM_CSPAR1_CS6_8BIT	0x0002	/* chip select with 8 bit port */
#define SIM_CSPAR1_CS6_16BIT	0x0003	/* chip select with 16 bit port */
#define SIM_CSPAR1_CS7_DIS	0x0000	/* discrete output */
#define SIM_CSPAR1_CS7_A20	0x0004	/* default pin function */
#define SIM_CSPAR1_CS7_8BIT	0x0008	/* chip select with 8 bit port */
#define SIM_CSPAR1_CS7_16BIT	0x000c	/* chip select with 16 bit port */
#define SIM_CSPAR1_CS8_DIS	0x0000	/* discrete output */
#define SIM_CSPAR1_CS8_A21	0x0010	/* default pin function */
#define SIM_CSPAR1_CS8_8BIT	0x0020	/* chip select with 8 bit port */
#define SIM_CSPAR1_CS8_16BIT	0x0030	/* chip select with 16 bit port */
#define SIM_CSPAR1_CS9_DIS	0x0000	/* discrete output */
#define SIM_CSPAR1_CS9_A22	0x0040	/* default pin function */
#define SIM_CSPAR1_CS9_8BIT	0x0080	/* chip select with 8 bit port */
#define SIM_CSPAR1_CS9_16BIT	0x00c0	/* chip select with 16 bit port */
#define SIM_CSPAR1_CS10_E_CLK	0x0000	/* E clock output */
#define SIM_CSPAR1_CS10_A23	0x0100	/* default pin function */
#define SIM_CSPAR1_CS10_8BIT	0x0200	/* chip select with 8 bit port */
#define SIM_CSPAR1_CS10_16BIT	0x0300	/* chip select with 16 bit port */

/* SIM_CSBAR - Chip Select Base Address Register */

#define SIM_CSBAR_2K		0x0000	/* 2k block size */
#define SIM_CSBAR_8K		0x0001	/* 8k block size */
#define SIM_CSBAR_16K		0x0002	/* 16k block size */
#define SIM_CSBAR_64K		0x0003	/* 64k block size */
#define SIM_CSBAR_128K		0x0004	/* 128k block size */
#define SIM_CSBAR_256K		0x0005	/* 256k block size */
#define SIM_CSBAR_512K		0x0006	/* 512k block size */
#define SIM_CSBAR_1024K		0x0007	/* 1024k block size */

/* SIM_CSOR - Chip Select Option Register */

#define SIM_CSOR_AVEC		0x0001	/* autovector */
#define SIM_CSOR_IPL_ALL	0x0000	/* assert chip select for any level */
#define SIM_CSOR_IPL_1		0x0002	/* assert chip select for level 1 */
#define SIM_CSOR_IPL_2		0x0004	/* assert chip select for level 2 */
#define SIM_CSOR_IPL_3		0x0006	/* assert chip select for level 3 */
#define SIM_CSOR_IPL_4		0x0008	/* assert chip select for level 4 */
#define SIM_CSOR_IPL_5		0x000a	/* assert chip select for level 5 */
#define SIM_CSOR_IPL_6		0x000c	/* assert chip select for level 6 */
#define SIM_CSOR_IPL_7		0x000e	/* assert chip select for level 7 */
#define SIM_CSOR_SP_CPU		0x0000	/* CPU space */
#define SIM_CSOR_SP_USER	0x0010	/* user space */
#define SIM_CSOR_SP_SUPV	0x0020	/* supervisor space */
#define SIM_CSOR_SP_SU		0x0030	/* either supervisor or user space */
#define SIM_CSOR_WAIT0		0x0000	/* dsack with 0 wait states */
#define SIM_CSOR_WAIT1		0x0040	/* dsack with 1 wait states */
#define SIM_CSOR_WAIT2		0x0080	/* dsack with 2 wait states */
#define SIM_CSOR_WAIT3		0x00c0	/* dsack with 3 wait states */
#define SIM_CSOR_WAIT4		0x0100	/* dsack with 4 wait states */
#define SIM_CSOR_WAIT5		0x0140	/* dsack with 5 wait states */
#define SIM_CSOR_WAIT6		0x0180	/* dsack with 6 wait states */
#define SIM_CSOR_WAIT7		0x01c0	/* dsack with 7 wait states */
#define SIM_CSOR_WAIT8		0x0200	/* dsack with 8 wait states */
#define SIM_CSOR_WAIT9		0x0240	/* dsack with 9 wait states */
#define SIM_CSOR_WAIT10		0x0280	/* dsack with 10 wait states */
#define SIM_CSOR_WAIT11		0x02c0	/* dsack with 11 wait states */
#define SIM_CSOR_WAIT12		0x0300	/* dsack with 12 wait states */
#define SIM_CSOR_WAIT13		0x0340	/* dsack with 13 wait states */
#define SIM_CSOR_WAIT_FAST	0x0380	/* fast termination */
#define SIM_CSOR_WAIT_EXT	0x03c0	/* external dsack generation */
#define SIM_CSOR_AS	 	0x0000	/* strobe with AS* */
#define SIM_CSOR_DS		0x0400	/* strobe with DS* */
#define SIM_CSOR_READ		0x0800	/* read only */
#define SIM_CSOR_WRITE		0x1000	/* write only */
#define SIM_CSOR_RW		0x1800	/* read/write */
#define SIM_CSOR_BYTE_OFF	0x0000	/* off */
#define SIM_CSOR_BYTE_LOWER	0x2000	/* lower byte access */
#define SIM_CSOR_BYTE_UPPER	0x4000	/* upper byte access */
#define SIM_CSOR_BYTE_BOTH	0x6000	/* either upper or lower access */
#define SIM_CSOR_ASYNC		0x0000	/* asynchronous */
#define SIM_CSOR_SYNC		0x8000	/* synchronous */


/* RAM - Register definitions for the RAM Control Registers */

/* RAM_RAMMCR - RAM Module Configuration Register */

#define RAM_RAMMCR_SUPV		0x0100	/* supv. access to on chip RAM only */
#define RAM_RAMMCR_STOP		0x8000	/* low power stop mode */

/* RAM_RAMTST - RAM Test Register */

#define RAM_RAMTST_RTBA		0x0100	/* RAMBAR may be written as desired */

/* RAM_RAMBAR - RAM Base Address Register */

#define RAM_RAMBAR_DISABLE	0x0001	/* RAM array is disabled */
#define RAM_RAMBAR_ENABLE	0x0000	/* RAM array is enabled */


/* QSM - Register definitions for the Queued Serial Module (QSM) */

/* QSM_MCR - Module Configuration Register */

#define QSM_MCR_SUPV		0x0080	/* supervisor/unrestricted access */
#define QSM_MCR_FRZ0		0x2000	/* reserved */
#define QSM_MCR_FRZ1		0x4000	/* halt QSM on transfer bndry */
#define QSM_MCR_STOP		0x8000	/* stop enable */

/* QSM_QILR -  QSM Interrupt Level Register */

#define QSM_QILR_SCI_MASK	0x07	/* SCI interrupt level (0 = disabled) */
#define QSM_QILR_SPI_MASK	0x38	/* SCI interrupt level (0 = disabled) */

/* QSM_SCCR1 - Control Register 1 */

#define QSM_SCCR1_SBK		0x0001	/* send break */
#define QSM_SCCR1_RWU		0x0002	/* receiver wakeup enable */
#define QSM_SCCR1_RE		0x0004	/* receiver enable */
#define QSM_SCCR1_TE		0x0008	/* transmitter enable */
#define QSM_SCCR1_ILIE		0x0010	/* idle-line interrupt enable */
#define QSM_SCCR1_RIE		0x0020	/* receiver interrupt enable */
#define QSM_SCCR1_TCIE		0x0040	/* transmit complete interrupt enable */
#define QSM_SCCR1_TIE		0x0080	/* transmit interrupt enable */
#define QSM_SCCR1_WAKE		0x0100	/* wakeup by address mark */
#define QSM_SCCR1_M		0x0200	/* mode select: 0= 8 data bits, 1 = 9 */
#define QSM_SCCR1_PE		0x0400	/* parity enable */
#define QSM_SCCR1_PT		0x0800	/* parity type: 1=Odd, 0=Even */
#define QSM_SCCR1_ILT		0x1000	/* idle line detect type */
#define QSM_SCCR1_WOMS		0x2000	/* wired or mode for SCI Pins */
#define QSM_SCCR1_LOOPS		0x4000	/* test SCI operation */

/* QSM_SCSR - Status Register */

#define QSM_SCSR_PF		0x0001	/* parity error flag */
#define QSM_SCSR_FE		0x0002	/* framing error flag */
#define QSM_SCSR_NF		0x0004	/* noise error flag */
#define QSM_SCSR_OR		0x0008	/* overrun error flag */
#define QSM_SCSR_IDLE		0x0010	/* idle-line detected flag */
#define QSM_SCSR_RAF		0x0020	/* receiver active flag */
#define QSM_SCSR_RDRF		0x0040	/* receive data register full flag */