📄 aulib.h
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#define AU_CLOCK_FREQUENCY_CONTROL_FS0 (1<<0)#define AU_CLOCK_FREQUENCY_CONTROL_FE0 (1<<1)#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV0 MSK(9,2)#define AU_CLOCK_FREQUENCY_CONTROL_FS1 (1<<10) #define AU_CLOCK_FREQUENCY_CONTROL_FE1 (1<<11)#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV1 MSK(19,12) #define AU_CLOCK_FREQUENCY_CONTROL_FS2 (1<<20)#define AU_CLOCK_FREQUENCY_CONTROL_FE2 (1<<21)#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV2 MSK(29,22) #define AU_CLOCK_FREQUENCY_CONTROL_FRDIV0_SH 2#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV1_SH 12#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV2_SH 22 /* for use with AU_CLOCK_FREQUENCY_CONTROL1 register */#define AU_CLOCK_FREQUENCY_CONTROL_FS3 (1<<0)#define AU_CLOCK_FREQUENCY_CONTROL_FE3 (1<<1)#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV3 MSK(9,2) #define AU_CLOCK_FREQUENCY_CONTROL_FS4 (1<<10)#define AU_CLOCK_FREQUENCY_CONTROL_FE4 (1<<11)#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV4 MSK(19,12) #define AU_CLOCK_FREQUENCY_CONTROL_FS5 (1<<20)#define AU_CLOCK_FREQUENCY_CONTROL_FE5 (1<<21)#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV5 MSK(29,22) #define AU_CLOCK_FREQUENCY_CONTROL_FRDIV3_SH 2#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV4_SH 12#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV5_SH 22#define AU_CLOCK_SOURCE_CONTROL_CIR (1<<0) #define AU_CLOCK_SOURCE_CONTROL_DIR (1<<1) #define AU_CLOCK_SOURCE_CONTROL_MIR MSK(4,2) #define AU_CLOCK_SOURCE_CONTROL_CUD (1<<5) #define AU_CLOCK_SOURCE_CONTROL_DUD (1<<6) #define AU_CLOCK_SOURCE_CONTROL_MUD MSK(9,7) #define AU_CLOCK_SOURCE_CONTROL_CUH (1<<10) #define AU_CLOCK_SOURCE_CONTROL_DUH (1<<11) #define AU_CLOCK_SOURCE_CONTROL_MUH MSK(14,12) #define AU_CLOCK_SOURCE_CONTROL_CI2 (1<<15) #define AU_CLOCK_SOURCE_CONTROL_DI2 (1<<16) #define AU_CLOCK_SOURCE_CONTROL_MI2 MSK(19,17)#define AU_CLOCK_SOURCE_CONTROL_CE0 (1<<20) #define AU_CLOCK_SOURCE_CONTROL_DE0 (1<<21) #define AU_CLOCK_SOURCE_CONTROL_ME0 MSK(24,22) #define AU_CLOCK_SOURCE_CONTROL_CE1 (1<<25) #define AU_CLOCK_SOURCE_CONTROL_DE1 (1<<26) #define AU_CLOCK_SOURCE_CONTROL_ME1 MSK(29,27) #define AU_CLOCK_SOURCE_CONTROL_IR_SH 2#define AU_CLOCK_SOURCE_CONTROL_UD_SH 7#define AU_CLOCK_SOURCE_CONTROL_UH_SH 12#define AU_CLOCK_SOURCE_CONTROL_I2_SH 17#define AU_CLOCK_SOURCE_CONTROL_E0_SH 22#define AU_CLOCK_SOURCE_CONTROL_E1_SH 27#define AU_CLOCK_SOURCE_CONTROL_AUX 0x1#define AU_CLOCK_SOURCE_CONTROL_FREQ0 0x2#define AU_CLOCK_SOURCE_CONTROL_FREQ1 0x3#define AU_CLOCK_SOURCE_CONTROL_FREQ2 0x4#define AU_CLOCK_SOURCE_CONTROL_FREQ3 0x5#define AU_CLOCK_SOURCE_CONTROL_FREQ4 0x6#define AU_CLOCK_SOURCE_CONTROL_FREQ5 0x7/* GPIO */#define AU_GPIO_BASE (0xb1900000)#define AU_GPIO_REG(reg) (AU_GPIO_BASE + (reg))#define AU_GPIO_PINFUNC AU_GPIO_REG(0x02c)#define AU_GPIO_TRISTATE_STATE_READ AU_GPIO_REG(0x100)#define AU_GPIO_TRISTATE_STATE_SET AU_GPIO_REG(0x100)#define AU_GPIO_OUTPUT_STATE_READ AU_GPIO_REG(0x108)#define AU_GPIO_OUTPUT_STATE_SET AU_GPIO_REG(0x108)#define AU_GPIO_OUTPUT_STATE_CLEAR AU_GPIO_REG(0x10c)#define AU_GPIO_PIN_STATE_READ AU_GPIO_REG(0x110)#define AU_GPIO_PIN_INPUT_ENABLE AU_GPIO_REG(0x110)#define AU_SYS_PIN_INPUT_EN AU_GPIO_REG(0x110)/* AC'97 Controller */#define AU_AC97_BASE (0xb0000000)#define AU_AC97_REG(reg) (AU_AC97_BASE + (reg))#define AU_AC97_CONFIG AU_AC97_REG(0x00)#define AU_AC97_STATUS AU_AC97_REG(0x04)#define AU_AC97_DATA AU_AC97_REG(0x08)#define AU_AC97_CMMD AU_AC97_REG(0x0C)#define AU_AC97_CMMDRESP AU_AC97_REG(0x0C)#define AU_AC97_ENABLE AU_AC97_REG(0x10)#define AU_AC97_CONFIG_RSLOTS MSK(22,13)#define AU_AC97_CONFIG_RSLOT3 (1 << 13)#define AU_AC97_CONFIG_RSLOT4 (1 << 14)#define AU_AC97_CONFIG_RSLOT5 (1 << 15)#define AU_AC97_CONFIG_RSLOT6 (1 << 16)#define AU_AC97_CONFIG_RSLOT7 (1 << 17)#define AU_AC97_CONFIG_RSLOT8 (1 << 18)#define AU_AC97_CONFIG_RSLOT9 (1 << 19)#define AU_AC97_CONFIG_RSLOT10 (1 << 20)#define AU_AC97_CONFIG_RSLOT11 (1 << 21)#define AU_AC97_CONFIG_RSLOT12 (1 << 22)#define AU_AC97_CONFIG_TSLOTS MSK(12,3)#define AU_AC97_CONFIG_TSLOT3 (1 << 3)#define AU_AC97_CONFIG_TSLOT4 (1 << 4)#define AU_AC97_CONFIG_TSLOT5 (1 << 5)#define AU_AC97_CONFIG_TSLOT6 (1 << 6)#define AU_AC97_CONFIG_TSLOT7 (1 << 7)#define AU_AC97_CONFIG_TSLOT8 (1 << 8)#define AU_AC97_CONFIG_TSLOT9 (1 << 9)#define AU_AC97_CONFIG_TSLOT10 (1 << 10)#define AU_AC97_CONFIG_TSLOT11 (1 << 11)#define AU_AC97_CONFIG_TSLOT12 (1 << 12)#define AU_AC97_CONFIG_ACLINK_RESET (1 << 0)#define AU_AC97_STATUS_READY (1 << 7)#define AU_AC97_STATUS_CP (1 << 6)#define AU_AC97_CMMD_READ (1 << 7)#define AU_AC97_CMMD_INDEX MSK(6,0)#define AU_AC97_ENABLE_CTRL (1 << 4)#define AU_AC97_ENABLE_CLOCK (1 << 0)#define SET_AC97_COMMAND(reg, value) ((value) << 16 | reg )#define GET_AC97_COMMAND(reg) (reg >> 16)/* USB Controller */#define AU_USB_HOST_BASE (0xb0100000)#define AU_USB_HOST_REG(reg) (AU_USB_HOST_BASE + (reg))#define AU_USB_HOST_ENABLE AU_USB_HOST_REG(0x7fffc)/* bits in host config register */#define AU_USB_HOST_ENABLE_RD (1 << 4) /* Reset Done */#define AU_USB_HOST_ENABLE_CE (1 << 3) /* Clock Enable */#define AU_USB_HOST_ENABLE_E (1 << 2) /* Enable */#define AU_USB_HOST_ENABLE_C (1 << 1) /* Cacheable */#define AU_USB_HOST_ENABLE_BE (1 << 0) /* Big Endian */#define AU_SYS_BASE (0xb1900000)#define AU_SYS_REG(reg) (AU_SYS_BASE + (reg))#define AU_SYS_TOY_TRIM AU_SYS_REG(0x00)#define AU_SYS_TOY_WRITE AU_SYS_REG(0x04)#define AU_SYS_TOY_MATCH_0 AU_SYS_REG(0x08)#define AU_SYS_TOY_MATCH_1 AU_SYS_REG(0x0c)#define AU_SYS_TOY_MATCH_2 AU_SYS_REG(0x10)#define AU_SYS_COUNTER_CONTROL AU_SYS_REG(0x14)#define AU_SYS_SCRATCH_0 AU_SYS_REG(0x18)#define AU_SYS_SCRATCH_1 AU_SYS_REG(0x1c)#define AU_SYS_FREQ_CONTROL_0 AU_SYS_REG(0x20)#define AU_SYS_FREQ_CONTROL_1 AU_SYS_REG(0x24)#define AU_SYS_CLOCK_SOURCE AU_SYS_REG(0x28)#define AU_SYS_PIN_FUNCTION AU_SYS_REG(0x2c)#define AU_SYS_WAKE_MASK AU_SYS_REG(0x34)#define AU_SYS_ENDIAN AU_SYS_REG(0x38)#define AU_SYS_POWER_CONTROL AU_SYS_REG(0x3c)#define AU_SYS_TOY_READ AU_SYS_REG(0x40)#define AU_SYS_RTC_TRIM AU_SYS_REG(0x44)#define AU_SYS_RTC_WRITE AU_SYS_REG(0x48)#define AU_SYS_RTC_MATCH_0 AU_SYS_REG(0x4c)#define AU_SYS_RTC_MATCH_1 AU_SYS_REG(0x50)#define AU_SYS_RTC_MATCH_2 AU_SYS_REG(0x54)#define AU_SYS_RTC_READ AU_SYS_REG(0x58)#define AU_SYS_WAKE_SOURCE AU_SYS_REG(0x5c)#define AU_SYS_CPU_PLL AU_SYS_REG(0x60)#define AU_SYS_AUX_PLL AU_SYS_REG(0x64)#define AU_SYS_SLEEP_POWER AU_SYS_REG(0x78)#define AU_SYS_SLEEP AU_SYS_REG(0x7c)/* bits in RTC and TOY control register */#define AU_SYS_COUNTER_CONTROL_ERS (1 << 23)#define AU_SYS_COUNTER_CONTROL_RTS (1 << 20)#define AU_SYS_COUNTER_CONTROL_RM2 (1 << 19)#define AU_SYS_COUNTER_CONTROL_RM1 (1 << 18)#define AU_SYS_COUNTER_CONTROL_RM0 (1 << 17)#define AU_SYS_COUNTER_CONTROL_RS (1 << 16)#define AU_SYS_COUNTER_CONTROL_BP (1 << 14)#define AU_SYS_COUNTER_CONTROL_REN (1 << 13)#define AU_SYS_COUNTER_CONTROL_BRT (1 << 12)#define AU_SYS_COUNTER_CONTROL_TEN (1 << 11)#define AU_SYS_COUNTER_CONTROL_BTT (1 << 10)#define AU_SYS_COUNTER_CONTROL_EO (1 << 8)#define AU_SYS_COUNTER_CONTROL_ETS (1 << 7)#define AU_SYS_COUNTER_CONTROL_32S (1 << 5)#define AU_SYS_COUNTER_CONTROL_TTS (1 << 4)#define AU_SYS_COUNTER_CONTROL_TM2 (1 << 3)#define AU_SYS_COUNTER_CONTROL_TM1 (1 << 2)#define AU_SYS_COUNTER_CONTROL_TM0 (1 << 1)#define AU_SYS_COUNTER_CONTROL_TS (1 << 0)#ifdef __cplusplus}#endif /* __cplusplus */#endif /* __INCauah */⌨️ 快捷键说明
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