📄 aulib.h
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/* auLib.h - Au support header *//* Copyright 2001 Wind River Systems, Inc. *//* * This file has been developed or significantly modified by the * MIPS Center of Excellence Dedicated Engineering Staff. * This notice is as per the MIPS Center of Excellence Master Partner * Agreement, do not remove this notice without checking first with * WR/Platforms MIPS Center of Excellence engineering management. *//*modification history--------------------01m,14may02,zmm Global au1000 name changes. SPR 77333.01l,30apr02,zmm Add AU1000_GPIO_PINFUNC definition.01k,03dec01,zmm Add CofE comment.01j,27nov01,zmm Add bits of counter control register, fix __cpluscplus bug.01i,18oct01,pes Merge changes01h,03oct01,pes Remove references to PHYS_TO_K1 macro so that this file becomes assembler safe.01g,26sep01,tlc Correct AC'97 macros.01f,22aug01,pes Add USB HOST register information01e,13aug01,tlc Add AC'97 Controller Information.01d,13aug01,pes Add defines needed to support PCI. Adjust addresses to make their KSEG1 locations more obvious.01c,23jul01,zmm Added Static Bus, SDRAM, UART, and clock Controllers.01b,19jun01,zmm Fix AU1000_INTERRUPT_CONTROLLER1_BASE01a,18may01,mem written.*//*This file contains I/O addresses and related constants for theAlchemy Semiconductor Au1000.*/#ifndef __INCauh#define __INCauh#ifdef __cplusplusextern "C" {#endif /* __cplusplus */#define MSK(n,m) (((1<<(n+1)) - 1) & ~((1<<(m)) - 1))/* Interrupt controllers */#define AU_INTERRUPT_CONTROLLER0_BASE (0xb0400000)#define AU_INTERRUPT_CONTROLLER1_BASE (0xb1800000)#define AU_INT_CTRL_REG(ctrl, reg) \ (*(volatile UINT32 *)(((ctrl) ? AU_INTERRUPT_CONTROLLER1_BASE \ : AU_INTERRUPT_CONTROLLER0_BASE) + (reg)))#define AU_INTC_CONFIG0_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x40)#define AU_INTC_CONFIG0_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x40)#define AU_INTC_CONFIG0_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x44)#define AU_INTC_CONFIG1_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x48)#define AU_INTC_CONFIG1_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x48)#define AU_INTC_CONFIG1_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x4c)#define AU_INTC_CONFIG2_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x50)#define AU_INTC_CONFIG2_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x50)#define AU_INTC_CONFIG2_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x54)#define AU_INTC_REQUEST0_INT(ctrl) AU_INT_CTRL_REG(ctrl, 0x54)#define AU_INTC_SOURCE_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x58)#define AU_INTC_SOURCE_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x58)#define AU_INTC_SOURCE_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x5c)#define AU_INTC_REQUEST1_INT(ctrl) AU_INT_CTRL_REG(ctrl, 0x5c)#define AU_INTC_ASSIGN_REQUEST_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x60)#define AU_INTC_ASSIGN_REQUEST_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x60)#define AU_INTC_ASSIGN_REQUEST_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x64)#define AU_INTC_WAKEUP_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x68)#define AU_INTC_WAKEUP_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x68)#define AU_INTC_WAKEUP_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x6c)#define AU_INTC_MASK_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x70)#define AU_INTC_MASK_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x70)#define AU_INTC_MASK_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x74)#define AU_INTC_RISING_EDGE_DETECT(ctrl) AU_INT_CTRL_REG(ctrl, 0x78)#define AU_INTC_RISING_EDGE_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x78)#define AU_INTC_FALLING_EDGE_DETECT(ctrl) AU_INT_CTRL_REG(ctrl, 0x7c)#define AU_INTC_FALLING_EDGE_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x7c)#define AU_INTC_TEST_BIT(ctrl) AU_INT_CTRL_REG(ctrl, 0x80)/* SDRAM controller */#define AU_SDRAM_CONTROLLER_BASE (0xb4000000)#define AU_SDRAM_REG(reg) (AU_SDRAM_CONTROLLER_BASE + (reg))#define AU_SDRAM_CS_MODE_0 AU_SDRAM_REG(0x00)#define AU_SDRAM_CS_MODE_1 AU_SDRAM_REG(0x04)#define AU_SDRAM_CS_MODE_2 AU_SDRAM_REG(0x08)#define AU_SDRAM_CS_CONFIG_0 AU_SDRAM_REG(0x0c)#define AU_SDRAM_CS_CONFIG_1 AU_SDRAM_REG(0x10)#define AU_SDRAM_CS_CONFIG_2 AU_SDRAM_REG(0x14)#define AU_SDRAM_REFRESH_CONFIG AU_SDRAM_REG(0x18)#define AU_SDRAM_PRECHARGE_CMD AU_SDRAM_REG(0x1c)#define AU_SDRAM_AUTO_REFRESH_CMD AU_SDRAM_REG(0x20)#define AU_SDRAM_WRITE_EXTERN_0 AU_SDRAM_REG(0x24)#define AU_SDRAM_WRITE_EXTERN_1 AU_SDRAM_REG(0x28)#define AU_SDRAM_WRITE_EXTERN_2 AU_SDRAM_REG(0x2c)#define AU_SDRAM_SLEEP AU_SDRAM_REG(0x30)#define AU_SDRAM_TOGGLE_CKE AU_SDRAM_REG(0x34)#define AU_SDRAM_CS_MODE_F (1<<22)#define AU_SDRAM_CS_MODE_SR (1<<21)#define AU_SDRAM_CS_MODE_BS (1<<20)#define AU_SDRAM_CS_MODE_RS MSK(19,18)#define AU_SDRAM_CS_MODE_CS MSK(17,15)#define AU_SDRAM_CS_MODE_TRAS MSK(14,11)#define AU_SDRAM_CS_MODE_TMRD MSK(10,9)#define AU_SDRAM_CS_MODE_TWR MSK(8,7)#define AU_SDRAM_CS_MODE_TRP MSK(6,5)#define AU_SDRAM_CS_MODE_TRCD MSK(4,3)#define AU_SDRAM_CS_MODE_TCL MSK(2,0)#define SET_SDRAM_CS_MODE_RS(x) ((x)<<18)#define SET_SDRAM_CS_MODE_CS(x) ((x)<<15)#define SET_SDRAM_CS_MODE_TRAS(x) ((x)<<11)#define SET_SDRAM_CS_MODE_TMRD(x) ((x)<<9)#define SET_SDRAM_CS_MODE_TWR(x) ((x)<<7)#define SET_SDRAM_CS_MODE_TRP(x) ((x)<<5)#define SET_SDRAM_CS_MODE_TRCD(x) ((x)<<3)#define SET_SDRAM_CS_MODE_TCL(x) (x)#define AU_SDRAM_CS_CONFIG_E (1<<20)#define AU_SDRAM_CS_CONFIG_CSBA MSK(19,10)#define AU_SDRAM_CS_CONFIG_CSMASK MSK(9,0)#define SET_SDRAM_CS_CONFIG_CSBA(x) ((x)<<10)#define SET_SDRAM_CS_CONFIG_CSMASK(x) (x)#define AU_SDRAM_REFRESH_CONFIG_TRC MSK(31,28)#define AU_SDRAM_REFRESH_CONFIG_TRPM MSK(27,26)#define AU_SDRAM_REFRESH_CONFIG_E (1<<25)#define AU_SDRAM_REFRESH_CONFIG_REF_INTER MSK(24,0)#define SET_SDRAM_REFRESH_CONFIG_TRC(x) ((x)<<28)#define SET_SDRAM_REFRESH_CONFIG_TRPR(x) ((x)<<26)#define SET_SDRAM_REFRESH_CONFIG_REF_INTER(x) (x)/* Static BUS controllers */#define AU_STATIC_CONTROLLER_BASE (0xb4001000)#define AU_STATIC_REG(chipsel, reg) (AU_STATIC_CONTROLLER_BASE + 0x10*(chipsel) + reg)#define AU_STATIC_CONFIG(chipsel) AU_STATIC_REG(chipsel, 0x0)#define AU_STATIC_TIMING(chipsel) AU_STATIC_REG(chipsel, 0x4)#define AU_STATIC_ADDRESS(chipsel) AU_STATIC_REG(chipsel, 0x8)#define AU_STATIC_CONFIG_BV (1 << 12)#define AU_STATIC_CONFIG_D5 (1 << 11)#define AU_STATIC_CONFIG_AV (1 << 10)#define AU_STATIC_CONFIG_LE (1 << 9)#define AU_STATIC_CONFIG_TS (1 << 8)#define AU_STATIC_CONFIG_EW (1 << 7)#define AU_STATIC_CONFIG_H (1 << 6)#define AU_STATIC_CONFIG_BS (1 << 5)#define AU_STATIC_CONFIG_PM (1 << 4)#define AU_STATIC_CONFIG_RO (1 << 3)#define AU_STATIC_CONFIG_DTY MSK(2,0)#define AU_STATIC_TIMING_TWCS MSK(30,28)#define AU_STATIC_TIMING_TCSH MSK(27,24)#define AU_STATIC_TIMING_TWP MSK(19,14)#define AU_STATIC_TIMING_TCSW MSK(13,10)#define AU_STATIC_TIMING_TPM MSK(9,6)#define AU_STATIC_TIMING_TA MSK(5,0)#define AU_STATIC_TIMING_TMST MSK(31,24)#define AU_STATIC_TIMING_TMSU MSK(23,17)#define AU_STATIC_TIMING_TMIH MSK(16,11)#define AU_STATIC_TIMING_TIST MSK(10,5)#define AU_STATIC_TIMING_TISU MSK(4,0)#define AU_STATIC_ADDRESS_E (1<<28)#define AU_STATIC_ADDRESS_CSADDR MSK(27,14)#define AU_STATIC_ADDRESS_AMASK MSK(13,0)#define SET_STATIC_ADDRESS_CSADDR(x) ((x)<<14)#define SET_STATIC_ADDRESS_AMASK(x) (x)/* Serial devices, UART 1 - UART 4 */#define UART0_BASE_ADR AU_UART_BASE#define AU_UART_BASE (0xb1100000)#define AU_UART_REG(uart, reg) (AU_UART_BASE + 0x100000*(uart) + (reg))#define AU_UART_RXDATA(uart) AU_UART_REG(uart,0x000)#define AU_UART_TXDATA(uart) AU_UART_REG(uart,0x004)#define AU_UART_INTERRUPT_ENABLE(uart) AU_UART_REG(uart,0x008)#define AU_UART_INTERRUPT_CAUSE(uart) AU_UART_REG(uart,0x00C)#define AU_UART_FIFO_CONTROL(uart) AU_UART_REG(uart,0x010)#define AU_UART_LINE_CONTROL(uart) AU_UART_REG(uart,0x014)#define AU_UART_MODEM_CONTROL(uart) AU_UART_REG(uart,0x018)#define AU_UART_LINE_STATUS(uart) AU_UART_REG(uart,0x01C)#define AU_UART_MODEM_STATUS(uart) AU_UART_REG(uart,0x020)#define AU_UART_CLOCK_DIVIDER(uart) AU_UART_REG(uart,0x028)#define AU_UART_MODULE_CONTROL(uart) AU_UART_REG(uart,0x100)/* Clock controller */#define AU_CLOCK_BASE (0xb1900000)#define AU_CLOCK_REG(reg) (AU_CLOCK_BASE + (reg))#define AU_CLOCK_FREQUENCY_CONTROL0 AU_CLOCK_REG(0x20)#define AU_CLOCK_FREQUENCY_CONTROL1 AU_CLOCK_REG(0x24)#define AU_CLOCK_CLOCK_SOURCE_CONTROL AU_CLOCK_REG(0x28)#define AU_CLOCK_CPU_PLL_CONTROL AU_CLOCK_REG(0x60)#define AU_CLOCK_AUX_PLL_CONTROL AU_CLOCK_REG(0x64)/* for use with AU_CLOCK_FREQUENCY_CONTROL0 register */⌨️ 快捷键说明
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