fga002.h

IXP425的BSP代码

    /* CTL1 */
#define	FGA_CTL1_COPROC_ASYNC	0x0	/* asynchronous */
#define	FGA_CTL1_COPROC_0WAIT	0x1	/* zero wait states */
#define	FGA_CTL1_COPROC_1WAIT	0x2	/* one wait states */
#define	FGA_CTL1_COPROC_2WAIT	0x3	/* two wait states */
#define	FGA_CTL1_SCON		0x4	/* internal arbiter select */
#define	FGA_CTL1_SUPERVISOR	0x8	/* supervisor access only */

    /* CTL2 */
#define	FGA_CTL2_BYTESTROBE	0x1	/* all bytestrobe lines asserted on R */
#define	FGA_CTL2_CSDROPTION	0x2	/* CSDRP active in R/W cycles */
#define	FGA_CTL2_VMERESCALLENA	0x4	/* VME ResetCall enable */
#define	FGA_CTL2_PARITYOUTENA	0x8	/* parity enable */

    /* CTL3 */
#define	FGA_CTL3_VMEBUS16	0x1	/* VME bus 16 bit wide */
#define	FGA_CTL3_VSBENA		0x2	/* VSB bus decoding enable */
#define	FGA_CTL3_VEC_MASK	0xc	/* bit 7,6 of interrupt vec number */

    /* CTL5 */
#define	FGA_CTL5_AUXOPTIONA	0x1	/* AUXOPTIONA enabled */
#define	FGA_CTL5_AUXOPTIONB	0x2	/* AUXOPTIONB enabled */
#define	FGA_CTL5_VME_A16_USER	0x4	/* VME access for mailbox int. */
#define	FGA_CTL5_VME_A16_SUP	0x8	/* VME access for mailbox int. */
#define	FGA_CTL5_VME_A16_BOTH	0xc	/* VME access for mailbox int. */

    /* CTL7 */
#define	FGA_CTL7_RAT_1US	0x1	/* VME release timeout */
#define	FGA_CTL7_RAT_2US	0x2	/* VME release timeout */
#define	FGA_CTL7_RAT_4US	0x3	/* VME release timeout */
#define	FGA_CTL7_RAT_8US	0x4	/* VME release timeout */
#define	FGA_CTL7_RAT_16US	0x5	/* VME release timeout */
#define	FGA_CTL7_RAT_32US	0x6	/* VME release timeout */
#define	FGA_CTL7_RAT_64US	0x7	/* VME release timeout */
#define	FGA_CTL7_NO_RELEASE_ON_BCLR 0x8	/* don't release bus on BCLR* */

    /* CTL 8 */
#define	FGA_CTL8_ACFAIL		0x1	/* ACFAIL handler */
#define	FGA_CTL8_FAIR_ARB	0x2	/* VME bus fair arbitration */
#define	FGA_CTL8_SOFTSYSFAILINIT 0x4	/* Asserts SYSFLTOVME-pin to 0 */
#define	FGA_CTL8_BOOTSYSFAILINIT 0x8	/* INACTIVE */

    /* CTL 9 */
#define	FGA_CTL9_0WAIT		0x1	/* EPROM wait states */
#define	FGA_CTL9_1WAIT		0x2	/* EPROM wait states */
#define	FGA_CTL9_2WAIT		0x3	/* EPROM wait states */
#define	FGA_CTL9_3WAIT		0x4	/* EPROM wait states */
#define	FGA_CTL9_4WAIT		0x5	/* EPROM wait states */
#define	FGA_CTL9_5WAIT		0x6	/* EPROM wait states */
#define	FGA_CTL9_6WAIT		0x7	/* EPROM wait states */
#define	FGA_CTL9_RESET_BUS	0x8	/* SYSRESET propagates to VMEBUS */

    /* CTL 15 */
#define	FGA_CTL15_SHAREDRMW	0x1	/* slave RMW cycles are supported */
#define	FGA_CTL15_CINHLIO	0x2	/* do cache 0xff800000 - 0xfff00000 */
#define	FGA_CTL15_CINH16	0x4	/* do cache 0xfcxxxxxx, 0xfexxxxxx */
#define	FGA_CTL15_CINHOFFBOARD	0x8	/* do cache off board */
#define	FGA_CTL15_BURST_1WAIT	0x10	/* one waitstate burst cycles */
#define	FGA_CTL15_BURST_TWO	0x20	/* two transfers per burst */
#define	FGA_CTL15_VSB_TOUT_DIS	0x60	/* VSB bus error timeout disabled */
#define	FGA_CTL15_VSB_TOUT_16	0x80	/* VSB bus error timeout : 16 us */
#define	FGA_CTL15_VSB_TOUT_1000	0x40	/* VSB bus error timeout : 1000 us */
#define	FGA_CTL15_VSB_TOUT_64000 0x00	/* VSB bus error timeout : 64000 us */

    /* LOCALIACK */
#define FGA_LOCALIACK_INTERNAL	0x00	/* FGA responds with internal vector */
#define FGA_LOCALIACK_NONE	0x01	/* FGA ignores interrupt */
#define FGA_LOCALIACK_EXT_1US	0x02	/* FGA passes ext. vec., 1us response */
#define FGA_LOCALIACK_EXT_500NS	0x03	/* FGA passes ext. vec.,.5us response */
#define FGA_LOCALIACK_LOCAL5	0x03	/* LOCAL 5 MASK */
#define FGA_LOCALIACK_LOCAL6	0x0c	/* LOCAL 6 MASK */
#define FGA_LOCALIACK_LOCAL7	0x30	/* LOCAL 7 MASK */
#define FGA_LOCALIACK_LOCAL8	0xc0	/* LOCAL 8 MASK */

    /* DMA Source/Destination Attribute Register */
#define	FGA_DMA_MAIN_MEMORY	0xc0	/* MAIN MEMORY		32 bit */
#define	FGA_DMA_SECOND_BUS_32	0xe0	/* Secondary Bus	32 bit */
#define	FGA_DMA_SECOND_BUS_16	0xe8	/* Secondary Bus	16 bit */
#define	FGA_DMA_SECOND_BUS_8	0xf0	/* Secondary Bus	 8 bit */
#define	FGA_DMA_VMEBUS_32	0x00	/* VMEbus		32 bit */
#define	FGA_DMA_VMEBUS_16	0x80	/* VMEbus		16 bit */
#define	FGA_DMA_VMEBUS_8	0x40	/* VMEbus		 8 bit */
#define	FGA_DMA_AUX_BUS		0xc8	/* AUX bus		 8 bit */

    /* DMA General Control Register */
#define	FGA_DMA_SRC_NO_COUNT	0x80	/* Source register does not count */
#define	FGA_DMA_SRC_COUNTS	0x00	/* Source register counts up */
#define	FGA_DMA_DST_NO_COUNT	0x40	/* Destination reg does not count */
#define	FGA_DMA_DST_COUNTS	0x00	/* Destination register counts up */
#define	FGA_DMA_ENABLE		0x01	/* enable DMA controller */

    /* DMA Run Control Register */
#define	FGA_DMA_START		0x01	/* start the DMA operation */
#define	FGA_DMA_STOP		0x00	/* stop the DMA operation */

    /* AUX Source/Destination Start Register */
#define	FGA_ASSACK_1CLK		0x00	/* AUXACK pin asserted... 1 clock */
#define	FGA_ASSACK_2CLK		0x10	/* 		 2 clockcycles */
#define	FGA_ASSACK_3CLK		0x20	/*		 3 clockcycles */
#define	FGA_ASSACK_4CLK		0x30	/*		 4 clockcycles */
#define	FGA_ASSACK_5CLK		0x40	/*		 5 clockcycles */
#define	FGA_ASSACK_6CLK		0x50	/*		 6 clockcycles */
#define	FGA_ASSACK_7CLK		0x60	/*		 7 clockcycles */
#define	FGA_ASSACK_8CLK		0x70	/*		 8 clockcycles */
#define	FGA_ASSACK_9CLK		0x80	/*		 9 clockcycles */
#define	FGA_ASSACK_10CLK	0x90	/*		10 clockcycles */
#define	FGA_ASSACK_11CLK	0xa0	/*		11 clockcycles */
#define	FGA_ASSACK_12CLK	0xb0	/*		12 clockcycles */
#define	FGA_ASSACK_AUXREQ	0xc0	/*		AUXREQ pin asserted */
#define	FGA_ASSACK_NORDY	0xd0	/* AUXREQ asserted, AUXRDY released */
#define	FGA_ASSACK_DATARD	0xe0	/* data read into FIFO */
#define	FGA_ASSACK_AUXRDY	0xf0	/* AUXRDY pin asserted */

#define FGA_RDY_1CLK		0x00	/* READY after... 1 clockcycle */
#define FGA_RDY_2CLK		0x01	/*		 2 clockcycles */
#define FGA_RDY_3CLK		0x02	/*		 3 clockcycles */
#define FGA_RDY_4CLK		0x03	/*		 4 clockcycles */
#define FGA_RDY_5CLK		0x04	/*		 5 clockcycles */
#define FGA_RDY_6CLK		0x05	/*		 6 clockcycles */
#define FGA_RDY_7CLK		0x06	/*		 7 clockcycles */
#define FGA_RDY_8CLK		0x07	/*		 8 clockcycles */
#define FGA_RDY_9CLK		0x08	/*		 9 clockcycles */
#define FGA_RDY_10CLK		0x09	/*		10 clockcycles */
#define FGA_RDY_11CLK		0x0a	/*		11 clockcycles */
#define FGA_RDY_12CLK		0x0b	/*		12 clockcycles */
#define FGA_RDY_AUXREQ		0x0c	/*		AUXREQ pin asserted */
#define FGA_RDY_NORDY		0x0d	/* AUXREQ asserted, AUXRDY released */
#define FGA_RDY_DATARD		0x0e	/* data read into FIFO */
#define FGA_RDY_AUXRDY		0x0f	/* AUXRDY pin asserted */

    /* AUX Source/Destination Term Register */
#define FGA_RELACK_1CLK		0x00	/* AUXACK pin released... 1 clock */
#define FGA_RELACK_2CLK		0x10	/* (after READY) 2 clockcycles */
#define FGA_RELACK_3CLK		0x20	/*		 3 clockcycles */
#define FGA_RELACK_4CLK		0x30	/*		 4 clockcycles */
#define FGA_RELACK_5CLK		0x40	/*		 5 clockcycles */
#define FGA_RELACK_6CLK		0x50	/*		 6 clockcycles */
#define FGA_RELACK_7CLK		0x60	/*		 7 clockcycles */
#define FGA_RELACK_8CLK		0x70	/*		 8 clockcycles */
#define FGA_RELACK_9CLK		0x80	/*		 9 clockcycles */
#define FGA_RELACK_10CLK	0x90	/*		10 clockcycles */
#define FGA_RELACK_11CLK	0xa0	/*		11 clockcycles */
#define FGA_RELACK_12CLK	0xb0	/*		12 clockcycles */
#define FGA_RELACK_AUXRDY	0xc0	/*		AUXRDY pin asserted */
#define FGA_RELACK_NOTALLOWED	0xd0	/* 		DO NOT USE */
#define FGA_RELACK_DATARD	0xe0	/* 		data read into FIFO */
#define FGA_RELACK_VALIDRDY	0xf0	/* 		valid READY */

#define FGA_NEWCYC_1CLK		0x00	/* NEWCYCLE starts... 1 clockcycle */
#define FGA_NEWCYC_2CLK		0x01	/* (after READY) 2 clockcycles */
#define FGA_NEWCYC_3CLK		0x02	/*		 3 clockcycles */
#define FGA_NEWCYC_4CLK		0x03	/*		 4 clockcycles */
#define FGA_NEWCYC_5CLK		0x04	/*		 5 clockcycles */
#define FGA_NEWCYC_6CLK		0x05	/*		 6 clockcycles */
#define FGA_NEWCYC_7CLK		0x06	/*		 7 clockcycles */
#define FGA_NEWCYC_8CLK		0x07	/*		 8 clockcycles */
#define FGA_NEWCYC_9CLK		0x08	/*		 9 clockcycles */
#define FGA_NEWCYC_10CLK	0x09	/*		10 clockcycles */
#define FGA_NEWCYC_11CLK	0x0a	/*		11 clockcycles */
#define FGA_NEWCYC_12CLK	0x0b	/*		12 clockcycles */
#define FGA_NEWCYC_AUXRDY	0x0c	/*		AUXRDY pin asserted */
#define FGA_NEWCYC_AUXACK	0x0d	/* 		AUXACK pin asserted */
#define FGA_NEWCYC_DATARD	0x0e	/* 		data read into FIFO */
#define FGA_NEWCYC_VALIDRDY	0x0f	/* 		valid READY */

    /* AUX Pin Control */
#define	FGA_AUXPIN_AUTOREQ	0x08	/* autorequest enabled */
#define	FGA_AUXPIN_NOAUTOREQ	0x00	/* autorequest disabled */
#define	FGA_AUXPIN_RDY_HIGH	0x04	/* AUXRDY active high */
#define	FGA_AUXPIN_RDY_LOW	0x00	/* AUXRDY active low */
#define	FGA_AUXPIN_ACK_HIGH	0x02	/* AUXACK active high */
#define	FGA_AUXPIN_ACK_LOW	0x00	/* AUXACK active low */
#define	FGA_AUXPIN_REQ_HIGH	0x01	/* AUXREQ active high */
#define	FGA_AUXPIN_REQ_LOW	0x00	/* AUXREQ active low */

    /* AUX FIFO Write/Read Timing Register */
#define	FGA_AUXFIFO_TIMING0	0x00	/* AUXFIFO Wr/Rd Timing 0 */
#define FGA_AUXFIFO_TIMING1	0x01	/* AUXFIFO Wr/Rd Timing 1 */
#define FGA_AUXFIFO_TIMING2	0x02	/* AUXFIFO Wr/Rd Timing 2 */
#define FGA_AUXFIFO_TIMING3	0x03	/* AUXFIFO Wr/Rd Timing 3 */
#define FGA_AUXFIFO_TIMING4	0x04	/* AUXFIFO Wr/Rd Timing 4 */
#define FGA_AUXFIFO_TIMING5	0x05	/* AUXFIFO Wr/Rd Timing 5 */
#define FGA_AUXFIFO_TIMING6	0x06	/* AUXFIFO Wr/Rd Timing 6 */
#define FGA_AUXFIFO_TIMING7	0x07	/* AUXFIFO Wr/Rd Timing 7 */
#define FGA_AUXFIFO_TIMING8	0x08	/* AUXFIFO Wr/Rd Timing 8 */
#define FGA_AUXFIFO_TIMING9	0x09	/* AUXFIFO Wr/Rd Timing 9 */
#define FGA_AUXFIFO_TIMING10	0x0a	/* AUXFIFO Wr/Rd Timing 10 */
#define FGA_AUXFIFO_TIMING11	0x0b	/* AUXFIFO Wr/Rd Timing 11 */
#define FGA_AUXFIFO_TIMING12	0x0c	/* AUXFIFO Wr/Rd Timing 12 */
#define FGA_AUXFIFO_TIMING13	0x0d	/* AUXFIFO Wr/Rd Timing 13 */
#define FGA_AUXFIFO_TIMING14	0x0e	/* AUXFIFO Wr/Rd Timing 14 */
#define FGA_AUXFIFO_TIMING15	0x0f	/* AUXFIFO Wr/Rd Timing 15 */

    /* ENAMCODE */
#define	FGA_ENAMCODE_EXTUSRDAT_R	0x2	/* DPR R  access with AM 0x09 */
#define	FGA_ENAMCODE_EXTUSRDAT_RW	0x3	/* DPR RW access with AM 0x09 */
#define	FGA_ENAMCODE_EXTUSRPGM_R	0x8	/* DPR R  access with AM 0x0a */
#define	FGA_ENAMCODE_EXTUSRPGM_RW	0xc	/* DPR RW access with AM 0x0a */
#define	FGA_ENAMCODE_EXTSUPDAT_R	0x20	/* DPR R  access with AM 0x0d */
#define	FGA_ENAMCODE_EXTSUPDAT_RW	0x30	/* DPR RW access with AM 0x0d */
#define	FGA_ENAMCODE_EXTSUPPGM_R	0x80	/* DPR R  access with AM 0x0e */
#define	FGA_ENAMCODE_EXTSUPPGM_RW	0xc0	/* DPR RW access with AM 0x0e */

    /* FMBCTL */
#define	FGA_FMBCTL_SLOT_MASK		0x1f	/* slot # mask */
#define	FGA_FMBCTL_CHANNEL0		0x20	/* channel 0 enabled */
#define	FGA_FMBCTL_CHANNEL1		0x40	/* channel 1 enabled */
#define	FGA_FMBCTL_BOTH			0x80	/* FMB access w/ AM 0x0d/0x09 */

/* function declarations */

#ifndef _ASMLANGUAGE
#if defined(__STDC__) || defined(__cplusplus)

#if	CPU_FAMILY == I960
IMPORT  STATUS  sysIntDisable ();
IMPORT  STATUS  sysIntEnable ();
IMPORT	int	sysBusIntAck ();
IMPORT  STATUS  sysBusIntGen ();
IMPORT  STATUS  sysMailboxEnable ();
#else	/* CPU_FAMILY == I960 */
IMPORT  STATUS  sysIntDisable (int intLevel);
IMPORT  STATUS  sysIntEnable (int intLevel);
IMPORT  int	sysBusIntAck (int intLevel);
IMPORT  STATUS  sysBusIntGen (int level, int vector);
IMPORT  STATUS  sysMailboxEnable (char *mailboxAdrs);
#endif  /* CPU_FAMILY == I960 */

IMPORT  STATUS  sysMailboxConnect (FUNCPTR routine, int arg);

#else	/* __STDC__ */

IMPORT  STATUS  sysIntDisable ();
IMPORT  STATUS  sysIntEnable ();
IMPORT  int	sysBusIntAck ();
IMPORT  STATUS  sysBusIntGen ();
IMPORT  STATUS  sysMailboxEnable ();
IMPORT  STATUS  sysMailboxConnect ();

#endif  /* __STDC__ */

#endif  /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCfga002h */