fga002.h

IXP425的BSP代码

/* fga002.h - Force Computers FGA-002 gate array */

/* Copyright 1984-1992 Wind River Systems, Inc. */
/*
modification history
--------------------
01i,22sep92,rrr  added support for c++
01h,06aug92,ccc  added DMA definitions.
01g,13jul92,caf  added function declarations.
01f,26may92,rrr  the tree shuffle
01e,04oct91,rrr  passed through the ansification filter
		  -changed ASMLANGUAGE to _ASMLANGUAGE
		  -changed copyright notice
01d,24oct90,yao  added missing register definitions.allow for ASM & reg offset.
01c,05oct90,shl  added copyright notice.
		 made #endif ANSI style.
01b,06sep89,jcf  fixed CTRL15 definitions.
01a,14feb89,jcf  written.
*/

#ifndef __INCfga002h
#define __INCfga002h

#ifdef __cplusplus
extern "C" {
#endif

#ifdef 	_ASMLANGUAGE
#define	CAST
#define	CAST_INT
#else
#define	CAST	(char *)
#define	CAST_INT	(int *)
#endif	/* _ASMLANGUAGE */

#define	FGA_ADRS(reg)	(CAST (FGA_BASE_ADRS + (reg * FGA_REG_INTERVAL)))
#define	FGA_ADRS_INT(reg) (CAST_INT (FGA_BASE_ADRS + (reg * FGA_REG_INTERVAL)))

/* register definitions */

    /* interrupt control registers */
#define	FGA_ICRMBOX0	FGA_ADRS(0x000)  	/* mailbox 0 */
#define	FGA_ICRMBOX1	FGA_ADRS(0x004)  	/* mailbox 1 */
#define	FGA_ICRMBOX2	FGA_ADRS(0x008)  	/* mailbox 2 */
#define	FGA_ICRMBOX3	FGA_ADRS(0x00C)  	/* mailbox 3 */
#define	FGA_ICRMBOX4	FGA_ADRS(0x010)  	/* mailbox 4 */
#define	FGA_ICRMBOX5	FGA_ADRS(0x014)  	/* mailbox 5 */
#define	FGA_ICRMBOX6	FGA_ADRS(0x018)  	/* mailbox 6 */
#define	FGA_ICRMBOX7	FGA_ADRS(0x01C)  	/* mailbox 7 */

#define	FGA_ICRTIM0	FGA_ADRS(0x220)  	/* timer */

#define	FGA_ICRFMB0REF	FGA_ADRS(0x240)  	/* FMB0 refused */
#define	FGA_ICRFMB1REF	FGA_ADRS(0x244)  	/* FMB1 refused */
#define	FGA_ICRFMB0MES	FGA_ADRS(0x248)  	/* FMB0 message */
#define	FGA_ICRFMB1MES	FGA_ADRS(0x24C)  	/* FMB1 message */

#define	FGA_ICRDMANORM	FGA_ADRS(0x230)  	/* DMA normal */
#define	FGA_ICRDMAERR	FGA_ADRS(0x234)  	/* DMA error */

#define	FGA_ICRPARITY	FGA_ADRS(0x258)  	/* parity */

#define	FGA_ICRVME1	FGA_ADRS(0x204)  	/* VMEIRQ 1 */
#define	FGA_ICRVME2	FGA_ADRS(0x208)  	/* VMEIRQ 2 */
#define	FGA_ICRVME3	FGA_ADRS(0x20C)  	/* VMEIRQ 3 */
#define	FGA_ICRVME4	FGA_ADRS(0x210)  	/* VMEIRQ 4 */
#define	FGA_ICRVME5	FGA_ADRS(0x214)  	/* VMEIRQ 5 */
#define	FGA_ICRVME6	FGA_ADRS(0x218)  	/* VMEIRQ 6 */
#define	FGA_ICRVME7	FGA_ADRS(0x21C)  	/* VMEIRQ 7 */

    /* extended interrupt control registers */
#define	FGA_ICRABORT	FGA_ADRS(0x280)  	/* abort */
#define	FGA_ICRACFAIL	FGA_ADRS(0x284)  	/* acfail */
#define	FGA_ICRSYSFAIL	FGA_ADRS(0x288)  	/* sysfail */

#define	FGA_ICRLOCAL0	FGA_ADRS(0x28C)  	/* local 0 */
#define	FGA_ICRLOCAL1	FGA_ADRS(0x290)  	/* local 1 */
#define	FGA_ICRLOCAL2	FGA_ADRS(0x294)  	/* local 2 */
#define	FGA_ICRLOCAL3	FGA_ADRS(0x298)  	/* local 3 */
#define	FGA_ICRLOCAL4	FGA_ADRS(0x29C)  	/* local 4 */
#define	FGA_ICRLOCAL5	FGA_ADRS(0x2A0)  	/* local 5 */
#define	FGA_ICRLOCAL6	FGA_ADRS(0x2A4)  	/* local 6 */
#define	FGA_ICRLOCAL7	FGA_ADRS(0x2A8)  	/* local 7 */


    /* control registers */
#define	FGA_CTL1	FGA_ADRS(0x238)  	/* arbitration */
#define	FGA_CTL2	FGA_ADRS(0x23C)  	/* parity */
#define	FGA_CTL3 	FGA_ADRS(0x250)  	/* bus width,vec */
#define FGA_CTL4	FGA_ADRS(0x254)  	/* boot decode,ack */
#define	FGA_CTL5	FGA_ADRS(0x264)  	/* mbox VME acc */
#define FGA_CTL6	FGA_ADRS(0x270)  	/* local DSACK */
#define	FGA_CTL7	FGA_ADRS(0x274)  	/* VME timeout */
#define	FGA_CTL8	FGA_ADRS(0x278)  	/* arb, acfail */
#define	FGA_CTL9	FGA_ADRS(0x27C)  	/* sysReset */
#define FGA_CTL10	FGA_ADRS(0x2C0)  	/* memory size */
#define FGA_CTL11	FGA_ADRS(0x2C4)  	/* memory decode */
#define FGA_CTL12	FGA_ADRS(0x32C)  	/* VME release */
#define FGA_CTL13	FGA_ADRS(0x350)  	/* TEST ONLY!!! */
#define FGA_CTL14	FGA_ADRS(0x354) 	/* EPROM access */
#define	FGA_CTL15	FGA_ADRS(0x358) 	/* slave rmw */
#define FGA_CTL16	FGA_ADRS(0x35C) 	/* bus unaligned rmw */
						/* timeout,parity    */

#define	FGA_LOCALIACK	FGA_ADRS(0x334)		/* IACK for L5-L8 */

#define	FGA_ENAMCODE	FGA_ADRS(0x2B4)		/* dual port RAM */

#define	FGA_MAINUM	FGA_ADRS(0x2C8)		/* A23-A16 LOCAL */
#define	FGA_MAINUU	FGA_ADRS(0x2CC)		/* A31-A24 LOCAL */

#define	FGA_VMEPAGE	FGA_ADRS(0x200)		/* A31-A28 VME */
#define	FGA_BOTTOMPAGEU	FGA_ADRS(0x2D0)		/* A27-A20 VME */
#define	FGA_BOTTOMPAGEL	FGA_ADRS(0x2D4)		/* A19-A12 VME */
#define	FGA_TOPPAGEU	FGA_ADRS(0x2D8)		/* A27-A20 VME */
#define	FGA_TOPPAGEL	FGA_ADRS(0x2DC)		/* A19-A12 VME */

#define	FGA_MYVMEPAGE	FGA_ADRS(0x2FC)		/* A15-A8 VME */

#define	FGA_FMBCTL	FGA_ADRS(0x338)		/* FMB control */
#define	FGA_FMBAREA	FGA_ADRS(0x33C)		/* A31-A24 VME */

#define	FGA_ISABORT	FGA_ADRS(0x4C8)		/* abort status */
#define	FGA_ISACFAIL	FGA_ADRS(0x4CC)		/* acfail status */
#define	FGA_ISSYSFAIL	FGA_ADRS(0x4D0)		/* sysfail status */

#define FGA_MBOX0	FGA_ADRS(0x80000)	/* Mailbox 0 */
#define FGA_MBOX1	FGA_ADRS(0x80004)  	/* Mailbox 1 */
#define FGA_MBOX2	FGA_ADRS(0x80008)  	/* Mailbox 2 */
#define FGA_MBOX3	FGA_ADRS(0x8000C)  	/* Mailbox 3 */
#define FGA_MBOX4	FGA_ADRS(0x80010)  	/* Mailbox 4 */
#define FGA_MBOX5	FGA_ADRS(0x80014)  	/* Mailbox 5 */
#define FGA_MBOX6	FGA_ADRS(0x80018)  	/* Mailbox 6 */
#define FGA_MBOX7	FGA_ADRS(0x8001C)  	/* Mailbox 7 */

    /* auxiliary registers */
#define FGA_AUXPINCTL	FGA_ADRS(0x260) 	/* control */
#define FGA_AUXFIFWEX	FGA_ADRS(0x268) 	/* fifo write time */
#define FGA_AUXFIFREX	FGA_ADRS(0x26C) 	/* fifo read time */

#define FGA_AUXSRCSTART FGA_ADRS(0x340) 	/* src start */
#define FGA_AUXDSTSTART FGA_ADRS(0x344) 	/* dst start */
#define FGA_AUXSRCTERM  FGA_ADRS(0x348) 	/* src termination */
#define FGA_AUXDSTTERM  FGA_ADRS(0x34C) 	/* dst termination */

    /* timer register */
#define FGA_TIM0PRELOAD FGA_ADRS(0x300) 	/* time preload */
#define FGA_TIM0CTL	FGA_ADRS(0x310) 	/* time control */
#define FGA_TIM0COUNT	FGA_ADRS(0xC00) 	/* timer0 counter */

    /* DMA registers */
#define FGA_DMASRCATT	FGA_ADRS(0x320) 	/* DMA src attr */
#define FGA_DMADSTATT	FGA_ADRS(0x324) 	/* DMA dst attr */
#define FGA_DMAGENERAL	FGA_ADRS(0x328) 	/* DMA general */
#define FGA_DMASRCDST	FGA_ADRS(0x4EC) 	/* DMA mode */
#define FGA_DMASRCADR	FGA_ADRS_INT(0x500) 	/* DMA src addr */
#define FGA_DMADSTADR	FGA_ADRS_INT(0x504) 	/* DMA dst addr */
#define FGA_DMATRFCNT	FGA_ADRS_INT(0x508) 	/* DMA trans count */

    /* interrupt status register */
#define FGA_ISLOCAL0	FGA_ADRS(0x480)
#define FGA_ISLOCAL1	FGA_ADRS(0x484)
#define FGA_ISLOCAL2	FGA_ADRS(0x488)
#define FGA_ISLOCAL3	FGA_ADRS(0x48C)
#define FGA_ISLOCAL4	FGA_ADRS(0x490)
#define FGA_ISLOCAL5	FGA_ADRS(0x494)
#define FGA_ISLOCAL6	FGA_ADRS(0x498)
#define FGA_ISLOCAL7	FGA_ADRS(0x49C)

#define FGA_ISTIM0	FGA_ADRS(0x4A0) 	/* timer0 */
#define FGA_ISDMANORM	FGA_ADRS(0x4B0) 	/* DMA termination */
#define FGA_ISDMAERR	FGA_ADRS(0x4B4) 	/* DMA error */

#define FGA_ISFB0REF	FGA_ADRS(0x4B8) 	/* FMB0 refused */
#define FGA_ISFB1REF	FGA_ADRS(0x4BC) 	/* FMB1 refused */
#define FGA_ISFB0MES	FGA_ADRS(0x4E0) 	/* FMB0 message */
#define FGA_ISFB1MES	FGA_ADRS(0x4E4) 	/* FMB1 message */

#define FGA_ISPARITY	FGA_ADRS(0x4C0)

#define FGA_DMARUNCTL	FGA_ADRS(0x4C4)
#define FGA_ABORTPIN	FGA_ADRS(0x4D4)
#define FGA_ACFAILPIN	FGA_ADRS(0x4D8)
#define FGA_SFAILPIN	FGA_ADRS(0x4DC)

    /* reset status register */
#define FGA_RSVMECALL	FGA_ADRS(0x4F0) 	/* VME */
#define FGA_RSKEYRES	FGA_ADRS(0x4F4) 	/* KEY */
#define FGA_RSCPUCALL	FGA_ADRS(0x4F8) 	/* CPU */
#define FGA_RSLOCSW	FGA_ADRS(0x4FC) 	/* local switch */
#define FGA_SOFTRESCALL FGA_ADRS(0xE00) 	/* software */

    /* miscellanous registers */
#define FGA_LIOTIMING	FGA_ADRS(0x330) 	/* local IO timing */

#define FGA_PTYLL	FGA_ADRS(0x400) 	/* PERR address */
#define FGA_PTYLM	FGA_ADRS(0x404) 	/* PERR address */
#define FGA_PTYUM	FGA_ADRS(0x408) 	/* PERR address */
#define FGA_PTYUU	FGA_ADRS(0x40C) 	/* PERR address */
#define FGA_PTYATT	FGA_ADRS(0x410) 	/* access status */
#define FGA_IDENT	FGA_ADRS(0x41C) 	/* rev/ident reg */

#define FGA_SPECIAL	FGA_ADRS(0x420) 	/* SPECIAL reg */
#define FGA_SPECIALENA  FGA_ADRS(0x424) 	/* SPECIAL enable */

#define FGA_FMBCH0	FGA_ADRS(0xC0000) 	/* FMB0 channel */
#define FGA_FMBCH1	FGA_ADRS(0xC0004) 	/* FMB1 channel*/

/* Interrupt Vector Offsets */

#define FGA_INT_MBOX0		0x00
#define FGA_INT_MBOX1		0x01
#define FGA_INT_MBOX2		0x02
#define FGA_INT_MBOX3		0x03
#define FGA_INT_MBOX4		0x04
#define FGA_INT_MBOX5		0x05
#define FGA_INT_MBOX6		0x06
#define FGA_INT_MBOX7		0x07
#define FGA_INT_TIMER		0x20
#define FGA_INT_FMB1REF		0x24
#define FGA_INT_FMB0REF		0x25
#define FGA_INT_FMB1		0x26
#define FGA_INT_FMB0		0x27
#define FGA_INT_ABORT		0x28
#define FGA_INT_ACFAIL		0x29
#define FGA_INT_SYSFAIL		0x2a
#define FGA_INT_DMAERR		0x2b
#define FGA_INT_DMANORM		0x2c
#define FGA_INT_PARITY		0x2d
#define FGA_INT_LOCAL0		0x30
#define FGA_INT_LOCAL1		0x31
#define FGA_INT_LOCAL2		0x32
#define FGA_INT_LOCAL3		0x33
#define FGA_INT_LOCAL4		0x34		/* or external */
#define FGA_INT_LOCAL5		0x35		/* or external */
#define FGA_INT_LOCAL6		0x36		/* or external */
#define FGA_INT_LOCAL7		0x37		/* or external */


/* Register Masks */

    /* ICR */
#define	FGA_ICR_ENABLE		0x8	/* enable interrupt */
#define	FGA_ICR_LEVEL_MASK	0x7	/* interrupt level mask */

    /* following defines are only for extended interrupt control registers */
#define	FGA_ICR_AUTOCLEAR	0x10	/* autoclear interrupt */
#define	FGA_ICR_ACTIVITY	0x20	/* active high = 1 */
#define	FGA_ICR_EDGE		0x40	/* 1 = edge sensitive */