gt64120a.h

IXP425的BSP代码

#define GT_SDRAM_CFG_DUPBA_DUPLICATE	1

#define GT_SDRAM_CFG_DUPEOT0_SHF	21
#define GT_SDRAM_CFG_DUPEOT0_MSK	(GT_MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
#define GT_SDRAM_CFG_DUPEOT0_BIT	GT_SDRAM_CFG_DUPEOT0_MSK
#define GT_SDRAM_CFG_DUPEOT0_DO_NOT_DUP	0
#define GT_SDRAM_CFG_DUPEOT0_DUPLICATE	1

#define GT_SDRAM_CFG_DUPEOT1_SHF	22
#define GT_SDRAM_CFG_DUPEOT1_MSK	(GT_MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
#define GT_SDRAM_CFG_DUPEOT1_BIT	GT_SDRAM_CFG_DUPEOT1_MSK
#define GT_SDRAM_CFG_DUPEOT1_DO_NOT_DUP	0
#define GT_SDRAM_CFG_DUPEOT1_DUPLICATE	1

#define GT_SDRAM_CFG_REGSDRAM_SHF	23
#define GT_SDRAM_CFG_REGSDRAM_MSK	(GT_MSK(1) << GT_SDRAM_CFG_REGSDRAM_SHF)
#define GT_SDRAM_CFG_REGSDRAM_BIT	GT_SDRAM_CFG_REGSDRAM_MSK
#define GT_SDRAM_CFG_REGSDRAM_DISABLE	0
#define GT_SDRAM_CFG_REGSDRAM_ENABLE	1

#define GT_SDRAM_CFG_DADR12_SHF		24
#define GT_SDRAM_CFG_DADR12_MSK		(GT_MSK(1) << GT_SDRAM_CFG_DADR12_SHF)
#define GT_SDRAM_CFG_DADR12_BIT		GT_SDRAM_CFG_DADR12_MSK
#define GT_SDRAM_CFG_DADR12_ADP0	0
#define GT_SDRAM_CFG_DADR12_DMAREQ3	0


/* for SDRAM Operation Mode: GT_SDRAM_OP_MODE */

#define GT_SDRAM_OPMODE_OP_SHF		0
#define GT_SDRAM_OPMODE_OP_MSK		(GT_MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
#define GT_SDRAM_OPMODE_OP_NORMAL	0	/* Normal SDRAM mode */
#define GT_SDRAM_OPMODE_OP_NOP		1	/* NOP Command */
#define GT_SDRAM_OPMODE_OP_ABPC		2	/* All banks precharge cmd */
#define GT_SDRAM_OPMODE_OP_MRCE		3	/* Mode Register Cmd enable */
#define GT_SDRAM_OPMODE_OP_CBRCE	4	/* CBR cycle enable */


/* for SDRAM Burst Mode: GT_SDRAM_BURST_MODE */

#define GT_SDRAM_BURST_MODE_MBO		0xFFB	/* reserved bits, must be 1 */
#define GT_BURST_ORDER_SHF		2
#define GT_BURST_ORDER_MSK		(GT_MSK(1) << GT_BURST_ORDER_SHF)
#define GT_BURST_ORDER_BIT		GT_BURST_ORDER_MSK
#define GT_BURST_ORDER_SUBBLOCK		1
#define GT_BURST_ORDER_LINEAR		0


/* for SDRAM Address Decode: GT_SDRAM_ADRS_DEC */

#define GT_ADDRDECODE_DEF		0x2	/* default value */


/* for SDRAM Bank 0/1/2/3 Parameters: GT_SDRAM_BANK*_PARAM */

#define GT_SDRAM_B0_CASLAT_SHF		0
#define GT_SDRAM_B0_CASLAT_MSK		(GT_MSK(2) << GT_SDRAM_B0_CASLAT_SHF)
#define GT_SDRAM_B0_CASLAT_2		1
#define GT_SDRAM_B0_CASLAT_3		2

#define GT_SDRAM_B0_FLOWTHROUGH_SHF	2
#define GT_SDRAM_B0_FLOWTHROUGH_MSK	(GT_MSK(1) << GT_SDRAM_B0_FLOWTHROUGH_SHF)
#define GT_SDRAM_B0_FLOWTHROUGH_BIT	GT_SDRAM_B0_FLOWTHROUGH_MSK
#define GT_SDRAM_B0_FLOWTHROUGH_1_SAMPLE	0
#define GT_SDRAM_B0_FLOWTHROUGH_NO_SAMPLE	1

#define GT_SDRAM_B0_SRASPRCHG_SHF	3
#define GT_SDRAM_B0_SRASPRCHG_MSK	(GT_MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
#define GT_SDRAM_B0_SRASPRCHG_2		0
#define GT_SDRAM_B0_SRASPRCHG_3		1

#define GT_SDRAM_B0_COMPATIBLE_SHF	4 /* for GT64120A's predecessor */
#define GT_SDRAM_B0_COMPATIBLE_MSK	(GT_MSK(1) << GT_SDRAM_B0_COMPATIBLE_SHF)
#define GT_SDRAM_B0_COMPATIBLE_BIT	GT_SDRAM_B0_COMPATIBLE_MSK
#define GT_SDRAM_B0_COMPATIBLE_B1	0
#define GT_SDRAM_B0_COMPATIBLE_B0	1

#define GT_SDRAM_B0_64BITINT_SHF	5
#define GT_SDRAM_B0_64BITINT_MSK	(GT_MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
#define GT_SDRAM_B0_64BITINT_BIT	GT_SDRAM_B0_64BITINT_MSK
#define GT_SDRAM_B0_64BITINT_2		0
#define GT_SDRAM_B0_64BITINT_4		1

#define GT_SDRAM_B0_BANKWIDTH_SHF	6
#define GT_SDRAM_B0_BANKWIDTH_MSK	(GT_MSK(1) << GT_SDRAM_B0_BANKWIDTH_SHF)
#define GT_SDRAM_B0_BANKWIDTH_BIT	GT_SDRAM_B0_BANKWIDTH_MSK
#define GT_SDRAM_B0_BANKWIDTH_32	0
#define GT_SDRAM_B0_BANKWIDTH_64	1

#define GT_SDRAM_B0_BANKLOC_SHF		7
#define GT_SDRAM_B0_BANKLOC_MSK		(GT_MSK(1) << GT_SDRAM_B0_BANKLOC_SHF)
#define GT_SDRAM_B0_BANKLOC_BIT		GT_SDRAM_B0_BANKLOC_MSK
#define GT_SDRAM_B0_BANKLOC_EVEN	0
#define GT_SDRAM_B0_BANKLOC_ODD		1

#define GT_SDRAM_B0_ECC_SHF		8
#define GT_SDRAM_B0_ECC_MSK		(GT_MSK(1) << GT_SDRAM_B0_ECC_SHF)
#define GT_SDRAM_B0_ECC_BIT		GT_SDRAM_B0_ECC_MSK
#define GT_SDRAM_B0_ECC_NOT_SUPPORTED	0
#define GT_SDRAM_B0_ECC_SUPPORTED	1

#define GT_SDRAM_B0_BYPASS_SHF		9
#define GT_SDRAM_B0_BYPASS_MSK		(GT_MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
#define GT_SDRAM_B0_BYPASS_BIT		GT_SDRAM_B0_BYPASS_MSK
#define GT_SDRAM_B0_BYPASS_NO_BYPASS	0
#define GT_SDRAM_B0_BYPASS_BYPASS	1

#define GT_SDRAM_B0_SRASTOSCAS_SHF	10
#define GT_SDRAM_B0_SRASTOSCAS_MSK	(GT_MSK(1) << GT_SDRAM_B0_SRASTOSCAS_SHF)
#define GT_SDRAM_B0_SRASTOSCAS_BIT	GT_SDRAM_B0_SRASTOSCAS_MSK
#define GT_SDRAM_B0_SRASTOSCAS_2	0
#define GT_SDRAM_B0_SRASTOSCAS_3	1

#define GT_SDRAM_B0_SDRAMSIZE0_SHF	11
#define GT_SDRAM_B0_SDRAMSIZE0_MSK	(GT_MSK(1) << GT_SDRAM_B0_SDRAMSIZE0_SHF)
#define GT_SDRAM_B0_SDRAMSIZE0_BIT	GT_SDRAM_B0_SDRAMSIZE0_MSK
#define GT_SDRAM_B0_SDRAMSIZE0_16M	0
#define GT_SDRAM_B0_SDRAMSIZE0_64M	1
#define GT_SDRAM_B0_SDRAMSIZE0_128M	1
#define GT_SDRAM_B0_SDRAMSIZE0_256M	1

#define GT_SDRAM_B0_EXTPARITY_SHF	12
#define GT_SDRAM_B0_EXTPARITY_MSK	(GT_MSK(1) << GT_SDRAM_B0_EXTPARITY_SHF)
#define GT_SDRAM_B0_EXTPARITY_BIT	GT_SDRAM_B0_EXTPARITY_MSK
#define GT_SDRAM_B0_EXTPARITY_NO_GEN	0
#define GT_SDRAM_B0_EXTPARITY_GEN	1

#define GT_SDRAM_B0_BRSTLEN_SHF		13
#define GT_SDRAM_B0_BRSTLEN_MSK		(GT_MSK(1) << GT_SDRAM_B0_BRSTLEN_SHF)
#define GT_SDRAM_B0_BRSTLEN_BIT		GT_SDRAM_B0_BRSTLEN_MSK
#define GT_SDRAM_B0_BRSTLEN_8		0
#define GT_SDRAM_B0_BRSTLEN_4		1

#define GT_SDRAM_B0_SDRAMSIZE1_SHF	14
#define GT_SDRAM_B0_SDRAMSIZE1_MSK	(GT_MSK(1) << GT_SDRAM_B0_SDRAMSIZE1_SHF)
#define GT_SDRAM_B0_SDRAMSIZE1_BIT	GT_SDRAM_B0_SDRAMSIZE1_MSK
#define GT_SDRAM_B0_SDRAMSIZE1_16M	0
#define GT_SDRAM_B0_SDRAMSIZE1_64M	0
#define GT_SDRAM_B0_SDRAMSIZE1_128M	0
#define GT_SDRAM_B0_SDRAMSIZE1_256M	1


/* for Device Bank 0/1/2/3 Parameters: GT_DEV_BANK*_PARAM_OFS */

#define GT_DEV_BANK_TURNOFF_SHF		0
#define GT_DEV_BANK_TURNOFF_MSK		(GT_MSK(3) << GT_DEV_BANK_TURNOFF_SHF)

#define GT_DEV_BANK_ACCTOFIRST_SHF	3
#define GT_DEV_BANK_ACCTOFIRST_MSK	(GT_MSK(4) << GT_DEV_BANK_ACCTOFIRST_SHF)

#define GT_DEV_BANK_ACCTONEXT_SHF	7
#define GT_DEV_BANK_ACCTONEXT_MSK	(GT_MSK(4) << GT_DEV_BANK_ACCTONEXT_SHF)

#define GT_DEV_BANK_ALETOWR_SHF		11
#define GT_DEV_BANK_ALETOWR_MSK		(GT_MSK(3) << GT_DEV_BANK_ALETOWR_SHF)

#define GT_DEV_BANK_WRACTIVE_SHF	14
#define GT_DEV_BANK_WRACTIVE_MSK	(GT_MSK(3) << GT_DEV_BANK_WRACTIVE_SHF)

#define GT_DEV_BANK_WRHIGH_SHF		17
#define GT_DEV_BANK_WRHIGH_MSK		(GT_MSK(3) << GT_DEV_BANK_WRHIGH_SHF)

#define GT_DEV_BANK_DEVWIDTH_SHF	20
#define GT_DEV_BANK_DEVWIDTH_MSK	(GT_MSK(2) << GT_DEV_BANK_DEVWIDTH_SHF)
#define GT_DEV_BANK_DEVWIDTH_8		0
#define GT_DEV_BANK_DEVWIDTH_16		1
#define GT_DEV_BANK_DEVWIDTH_32		2
#define GT_DEV_BANK_DEVWIDTH_64		3

#define GT_DEV_BANK_DMAFLYBY0_SHF	22
#define GT_DEV_BANK_DMAFLYBY0_MSK	(GT_MSK(1) << GT_DEV_BANK_DMAFLYBY0_SHF)
#define GT_DEV_BANK_DMAFLYBY0_BIT	GT_DEV_BANK_DMAFLYBY_MSK

#define GT_DEV_BANK_DEVLOC_SHF		23
#define GT_DEV_BANK_DEVLOC_MSK		(GT_MSK(1) << GT_DEV_BANK_DEVLOC_SHF)
#define GT_DEV_BANK_DEVLOC_BIT		GT_DEV_BANK_DEVLOC_MSK
#define GT_DEV_BANK_DEVLOC_EVEN		0
#define GT_DEV_BANK_DEVLOC_ODD		1

#define GT_DEV_BANK_DMAFLYBY1_SHF	26
#define GT_DEV_BANK_DMAFLYBY1_MSK	(GT_MSK(4) << GT_DEV_BANK_DMAFLYBY1_SHF)


/* for PCI Command: PCI_0_COMMAND, PCI_1_COMMAND */

#define GT_MBYTESWAP_SHF		0
#define GT_MBYTESWAP_MSK		(GT_MSK(1) << GT_MBYTESWAP_SHF)
#define GT_MBYTESWAP_BIT		GT_MBYTESWAP_MSK
#define GT_MBYTESWAP_SWAP		0
#define GT_MBYTESWAP_DONT_SWAP		1

#define GT_SYNCMODE_SHF			1
#define GT_SYNCMODE_MSK			(GT_MSK(3) << GT_SYNCMODE_SHF)
#define GT_SYNCMODE_BIT			GT_SYNCMODE_MSK
#define GT_SYNCMODE_DC_TO_66		0
#define GT_SYNCMODE_P_GE_HALF_T		1
#define GT_SYNCMODE_SYNC_P_GE_HALF_T	2
#define GT_SYNCMODE_P_GE_THIRD_T	5
#define GT_SYNCMODE_SYNC_P_GE_THIRD_T	6

#define GT_MWORDSWAP_SHF		10
#define GT_MWORDSWAP_MSK		(GT_MSK(1) << GT_MWORDSWAP_SHF)
#define GT_MWORDSWAP_BIT		GT_MWORDSWAP_MSK
#define GT_MWORDSWAP_SWAP		1
#define GT_MWORDSWAP_DONT_SWAP		0

#define GT_SWORDSWAP_SHF		11
#define GT_SWORDSWAP_MSK		(GT_MSK(1) << GT_SWORDSWAP_SHF)
#define GT_SWORDSWAP_BIT		GT_SWORDSWAP_MSK
#define GT_SWORDSWAP_SWAP		1
#define GT_SWORDSWAP_DONT_SWAP		0

#define GT_SSBWORDSWAP_SHF		12
#define GT_SSBWORDSWAP_MSK		(GT_MSK(1) << GT_SSBWORDSWAP_SHF)
#define GT_SSBWORDSWAP_BIT		GT_SSBWORDSWAP_MSK
#define GT_SSBWORDSWAP_SWAP		1
#define GT_SSBWORDSWAP_DONT_SWAP	0

#define GT_SBYTESWAP_SHF		16
#define GT_SBYTESWAP_MSK		(GT_MSK(1) << GT_SBYTESWAP_SHF)
#define GT_SBYTESWAP_BIT		GT_SBYTESWAP_MSK
#define GT_SBYTESWAP_SWAP		0
#define GT_SBYTESWAP_DONT_SWAP		1


/* for PCI Timeout & Retry: GT_PCI0_TIMEOUT_RETRY, GT_PCI1_TIMEOUT_RETRY */

#define GT_TIMEOUT0_SHF			0
#define GT_TIMEOUT0_MSK			(GT_MSK(8) << GT_TIMEOUT0_SHF)
#define GT_TIMEOUT0_MAX			GT_TIMEOUT0_MSK
#define GT_TIMEOUT0_DEF			0x0f

#define GT_TIMEOUT1_SHF			8
#define GT_TIMEOUT1_MSK			(GT_MSK(8) << GT_TIMEOUT1_SHF)
#define GT_TIMEOUT1_MAX			GT_TIMEOUT1_MSK
#define GT_TIMEOUT1_DEF			0x07

#define GT_RETRYCTR_SHF			16
#define GT_RETRYCTR_MSK			(GT_MSK(8) << GT_RETRYCTR_SHF)
#define GT_RETRYCTR_MAX			GT_RETRYCTR_MSK
#define GT_RETRYCTR_RETRY_FOREVER	0
#define GT_RETRYCTR_DEF			GT_RETRYCTR_RETRY_FOREVER

#define GT_TIMEOUT_MAX	(GT_TIMEOUT0_MAX | GT_TIMEOUT1_MAX | GT_RETRYCTR_MAX)


/* for PCI configuration cycles: GT_PCI0_CFG_ADRS, GT_PCI1_CFG_ADRS */

#define GT_CONFIGEN_SHF			31
#define GT_CONFIGEN_MSK			(GT_MSK(1) << GT_CONFIGEN_SHF)
#define GT_CONFIGEN_BIT			GT_CONFIGEN_MSK

#define GT_BUSNUM_SHF			16
#define GT_BUSNUM_MSK			(GT_MSK(8) << GT_BUSNUM_SHF)

#define GT_DEVNUM_SHF			11
#define GT_DEVNUM_MSK			(GT_MSK(5) << GT_DEVNUM_SHF)

#define GT_FUNCNUM_SHF			8
#define GT_FUNCNUM_MSK			(GT_MSK(3) << GT_FUNCNUM_SHF)

#define GT_REGNUM_SHF			2
#define GT_REGNUM_MSK			(GT_MSK(6) << GT_REGNUM_SHF)


/*
 * for Interrupt Cause & Mask: GT_INTR_CAUSE, GT_CPU_INTR_MASK,
 * GT_PCI0_INTR_CAUSE_MASK
 *
 * (1) can also be used for High Interrupt Cause & Mask: GT_H_INTR_CAUSE,
 * GT_CPU_H_INTR_MASK, GT_PCI0_H_INTR_CAUSE_MASK
 */

#define GT_INTR_INTSUM			0x00000001
#define GT_INTR_MEMOUT			0x00000002
#define GT_INTR_DMAOUT			0x00000004
#define GT_INTR_CPUOUT			0x00000008
#define GT_INTR_DMA0COMP		0x00000010
#define GT_INTR_DMA1COMP		0x00000020
#define GT_INTR_DMA2COMP		0x00000040
#define GT_INTR_DMA3COMP		0x00000080
#define GT_INTR_T0EXP			0x00000100
#define GT_INTR_T1EXP			0x00000200
#define GT_INTR_T2EXP			0x00000400
#define GT_INTR_T3EXP			0x00000800
#define GT_INTR_MASRDERR		0x00001000	/* (1) */
#define GT_INTR_SLVWRERR		0x00002000	/* (1) */
#define GT_INTR_MASWRERR		0x00004000	/* (1) */
#define GT_INTR_SLVRDERR		0x00008000	/* (1) */
#define GT_INTR_ADDRERR 		0x00010000	/* (1) */
#define GT_INTR_MEMERR			0x00020000
#define GT_INTR_MASABORT		0x00040000	/* (1) */
#define GT_INTR_TARABORT		0x00080000	/* (1) */
#define GT_INTR_RETRYCTR		0x00100000	/* (1) */
#define GT_INTR_PMCINT			0x00200000	/* (1) */

#define GT_INTR_CPUINT_SHF		22
#define GT_INTR_CPUINT_MSK		(GT_MSK(4) << GT_CPUINT_SHF)

#define GT_INTR_PCIINT_SHF		26
#define GT_INTR_PCIINT_MSK		(GT_MSK(4) << GT_PCIINT_SHF)

#define GT_INTR_CPUINTSUM		0x40000000
#define GT_INTR_PCIINTSUM		0x80000000


/* for SErr0/1* Mask, PCI_0/1 Events: GT_PCI0_SERR0_MASK, GT_PC1_SERR1_MASK */

#define GT_SERR_ADDRERR			0x00000001
#define GT_SERR_MASWRERR		0x00000002
#define GT_SERR_MASRDERR		0x00000004
#define GT_SERR_MEMERR			0x00000008
#define GT_SERR_MASABORT		0x00000010
#define GT_SERR_TARABORT		0x00000020


/* Miscellenous */

#define GT_BANKSIZE_MAX		(256 * 1024 * 1024)   /* Max 256MB bank */

/* GT Internal register data must be swapped when CPU is in big-endian mode */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#define GT_SWAP(x)			LONGSWAP(x)
#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
#define GT_SWAP(x)			(x)
#endif /* _BYTE_ORDER */

#ifdef __cplusplus
}
#endif

#endif	/* __INCgt64120ah */