📄 gt64120a.h

📁 IXP425的BSP代码
💻 H
📖 第 1 页 / 共 3 页
字号:
#define GT_PCI0_MEM_1_L_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_1_L_DEC_ADRS_OFS)#define GT_PCI0_MEM_1_H_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_1_H_DEC_ADRS_OFS)#define GT_PCI1_IO_L_DEC_ADRS		(GT_BASE+GT_PCI1_IO_L_DEC_ADRS_OFS)#define GT_PCI1_IO_H_DEC_ADRS		(GT_BASE+GT_PCI1_IO_H_DEC_ADRS_OFS)#define GT_PCI1_MEM_0_L_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_0_L_DEC_ADRS_OFS)#define GT_PCI1_MEM_0_H_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_0_H_DEC_ADRS_OFS)#define GT_PCI1_MEM_1_L_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_1_L_DEC_ADRS_OFS)#define GT_PCI1_MEM_1_H_DEC_ADRS	(GT_BASE+GT_PCI1_MEM_1_H_DEC_ADRS_OFS)#define GT_INTERNAL_SPACE_DEC		(GT_BASE+GT_INTERNAL_SPACE_DEC_OFS)#define GT_SCS10_ADRS_REMAP		(GT_BASE+GT_SCS10_ADRS_REMAP_OFS)#define GT_SCS32_ADRS_REMAP		(GT_BASE+GT_SCS32_ADRS_REMAP_OFS)#define GT_CS20_REMAP			(GT_BASE+GT_CS20_REMAP_OFS)#define GT_CS3_BOOTCS_REMAP		(GT_BASE+GT_CS3_BOOTCS_REMAP_OFS)#define GT_PCI0_IO_REMAP		(GT_BASE+GT_PCI0_IO_REMAP_OFS)#define GT_PCI0_MEM_0_REMAP		(GT_BASE+GT_PCI0_MEM_0_REMAP_OFS)#define GT_PCI0_MEM_1_REMAP		(GT_BASE+GT_PCI0_MEM_1_REMAP_OFS)#define GT_PCI1_IO_REMAP		(GT_BASE+GT_PCI1_IO_REMAP_OFS)#define GT_PCI1_MEM_0_REMAP		(GT_BASE+GT_PCI1_MEM_0_REMAP_OFS)#define GT_PCI1_MEM_1_REMAP		(GT_BASE+GT_PCI1_MEM_1_REMAP_OFS)/* CPU Errors Report */#define GT_CPU_ERROR_ADRS_L		(GT_BASE+GT_CPU_ERROR_ADRS_L_OFS)#define GT_CPU_ERROR_ADRS_H		(GT_BASE+GT_CPU_ERROR_ADRS_H_OFS)#define GT_CPU_ERROR_DATA_L		(GT_BASE+GT_CPU_ERROR_DATA_L_OFS)#define GT_CPU_ERROR_DATA_H		(GT_BASE+GT_CPU_ERROR_DATA_H_OFS)#define GT_CPU_ERROR_PARITY		(GT_BASE+GT_CPU_ERROR_PARITY_OFS)/* CPU Sync Barrier */#define GT_PCI0_SYNC_BARRIER_VIRT	(GT_BASE+GT_PCI0_SYNC_BARRIER_VIRT_OFS)#define GT_PCI1_SYNC_BARRIER_VIRT	(GT_BASE+GT_PCI1_SYNC_BARRIER_VIRT_OFS)/* SDRAM and Device Address Decode */#define GT_SCS0_L_DEC_ADRS		(GT_BASE+GT_SCS0_L_DEC_ADRS_OFS)#define GT_SCS0_H_DEC_ADRS		(GT_BASE+GT_SCS0_H_DEC_ADRS_OFS)#define GT_SCS1_L_DEC_ADRS		(GT_BASE+GT_SCS1_L_DEC_ADRS_OFS)#define GT_SCS1_H_DEC_ADRS		(GT_BASE+GT_SCS1_H_DEC_ADRS_OFS)#define GT_SCS2_L_DEC_ADRS		(GT_BASE+GT_SCS2_L_DEC_ADRS_OFS)#define GT_SCS2_H_DEC_ADRS		(GT_BASE+GT_SCS2_H_DEC_ADRS_OFS)#define GT_SCS3_L_DEC_ADRS		(GT_BASE+GT_SCS3_L_DEC_ADRS_OFS)#define GT_SCS3_H_DEC_ADRS		(GT_BASE+GT_SCS3_H_DEC_ADRS_OFS)#define GT_CS0_L_DEC_ADRS		(GT_BASE+GT_CS0_L_DEC_ADRS_OFS)#define GT_CS0_H_DEC_ADRS		(GT_BASE+GT_CS0_H_DEC_ADRS_OFS)#define GT_CS1_L_DEC_ADRS		(GT_BASE+GT_CS1_L_DEC_ADRS_OFS)#define GT_CS1_H_DEC_ADRS		(GT_BASE+GT_CS1_H_DEC_ADRS_OFS)#define GT_CS2_L_DEC_ADRS		(GT_BASE+GT_CS2_L_DEC_ADRS_OFS)#define GT_CS2_H_DEC_ADRS		(GT_BASE+GT_CS2_H_DEC_ADRS_OFS)#define GT_CS3_L_DEC_ADRS		(GT_BASE+GT_CS3_L_DEC_ADRS_OFS)#define GT_CS3_H_DEC_ADRS		(GT_BASE+GT_CS3_H_DEC_ADRS_OFS)#define GT_BOOTCS_L_DEC_ADRS		(GT_BASE+GT_BOOTCS_L_DEC_ADRS_OFS)#define GT_BOOTCS_H_DEC_ADRS		(GT_BASE+GT_BOOTCS_H_DEC_ADRS_OFS)#define GT_ADRS_DEC_ERROR		(GT_BASE+GT_ADRS_DEC_ERROR_OFS)/* SDRAM Configuration */#define GT_SDRAM_CFG			(GT_BASE+GT_SDRAM_CFG_OFS)#define GT_SDRAM_OP_MODE		(GT_BASE+GT_SDRAM_OP_MODE_OFS)#define GT_SDRAM_BURST_MODE		(GT_BASE+GT_SDRAM_BURST_MODE_OFS)#define GT_SDRAM_ADRS_DEC		(GT_BASE+GT_SDRAM_ADRS_DEC_OFS)/* SDRAM Parameters */#define GT_SDRAM_BANK0_PARAM		(GT_BASE+GT_SDRAM_BANK0_PARAM_OFS)#define GT_SDRAM_BANK1_PARAM		(GT_BASE+GT_SDRAM_BANK1_PARAM_OFS)#define GT_SDRAM_BANK2_PARAM		(GT_BASE+GT_SDRAM_BANK2_PARAM_OFS)#define GT_SDRAM_BANK3_PARAM		(GT_BASE+GT_SDRAM_BANK3_PARAM_OFS)/* ECC */#define GT_ECC_ERROR_ADRS		(GT_BASE+GT_ECC_ERROR_ADRS_OFS)#define GT_ECC_ERROR_DATA_H		(GT_BASE+GT_ECC_ERROR_DATA_H_OFS)#define GT_ECC_ERROR_DATA_L		(GT_BASE+GT_ECC_ERROR_DATA_L_OFS)#define GT_ECC_FROM_MEM			(GT_BASE+GT_ECC_FROM_MEM_OFS)#define GT_ECC_CALCULATED		(GT_BASE+GT_ECC_CALCULATED_OFS)/* Device Parameters*/#define GT_DEV_BANK0_PARAM		(GT_BASE+GT_DEV_BANK0_PARAM_OFS)#define GT_DEV_BANK1_PARAM		(GT_BASE+GT_DEV_BANK1_PARAM_OFS)#define GT_DEV_BANK2_PARAM		(GT_BASE+GT_DEV_BANK2_PARAM_OFS)#define GT_DEV_BANK3_PARAM		(GT_BASE+GT_DEV_BANK3_PARAM_OFS)#define GT_DEV_BOOT_BANK_PARAM		(GT_BASE+GT_DEV_BOOT_BANK_PARAM_OFS)/* DMA Record */#define GT_CHAN_0_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_0_DMA_BYTE_COUNT_OFS)#define GT_CHAN_1_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_1_DMA_BYTE_COUNT_OFS)#define GT_CHAN_2_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_2_DMA_BYTE_COUNT_OFS)#define GT_CHAN_3_DMA_BYTE_COUNT	(GT_BASE+GT_CHAN_3_DMA_BYTE_COUNT_OFS)#define GT_CHAN_0_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_0_DMA_SRC_ADRS_OFS)#define GT_CHAN_1_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_1_DMA_SRC_ADRS_OFS)#define GT_CHAN_2_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_2_DMA_SRC_ADRS_OFS)#define GT_CHAN_3_DMA_SRC_ADRS		(GT_BASE+GT_CHAN_3_DMA_SRC_ADRS_OFS)#define GT_CHAN_0_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_0_DMA_DEST_ADRS_OFS)#define GT_CHAN_1_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_1_DMA_DEST_ADRS_OFS)#define GT_CHAN_2_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_2_DMA_DEST_ADRS_OFS)#define GT_CHAN_3_DMA_DEST_ADRS		(GT_BASE+GT_CHAN_3_DMA_DEST_ADRS_OFS)#define GT_CHAN_0_NEXT_REC_PTR		(GT_BASE+GT_CHAN_0_NEXT_REC_PTR_OFS)#define GT_CHAN_1_NEXT_REC_PTR		(GT_BASE+GT_CHAN_1_NEXT_REC_PTR_OFS)#define GT_CHAN_2_NEXT_REC_PTR		(GT_BASE+GT_CHAN_2_NEXT_REC_PTR_OFS)#define GT_CHAN_3_NEXT_REC_PTR		(GT_BASE+GT_CHAN_3_NEXT_REC_PTR_OFS)#define GT_CHAN_0_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_0_CURRENT_DESCRIPTOR_PTR_OFS)#define GT_CHAN_1_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_1_CURRENT_DESCRIPTOR_PTR_OFS)#define GT_CHAN_2_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_2_CURRENT_DESCRIPTOR_PTR_OFS)#define GT_CHAN_3_CURRENT_DESCRIPTOR_PTR	(GT_BASE+GT_CHAN_3_CURRENT_DESCRIPTOR_PTR_OFS)#define GT_CHAN_0_CTL			(GT_BASE+GT_CHAN_0_CTL_OFS)#define GT_CHAN_1_CTL			(GT_BASE+GT_CHAN_1_CTL_OFS)#define GT_CHAN_2_CTL			(GT_BASE+GT_CHAN_2_CTL_OFS)#define GT_CHAN_3_CTL			(GT_BASE+GT_CHAN_3_CTL_OFS)/* DMA Arbiter */#define GT_ARBITER_CTL			(GT_BASE+GT_ARBITER_CTL_OFS)/* Timer/COUNTER */#define GT_TIMER_COUNTER_0		(GT_BASE+GT_TIMER_COUNTER_0_OFS)#define GT_TIMER_COUNTER_1		(GT_BASE+GT_TIMER_COUNTER_1_OFS)#define GT_TIMER_COUNTER_2		(GT_BASE+GT_TIMER_COUNTER_2_OFS)#define GT_TIMER_COUNTER_3		(GT_BASE+GT_TIMER_COUNTER_3_OFS)#define GT_TIMER_COUNTER_CTL		(GT_BASE+GT_TIMER_COUNTER_CTL_OFS)/* PCI Internal */#define GT_PCI0_COMMAND			(GT_BASE+GT_PCI0_COMMAND_OFS)#define GT_PCI1_COMMAND			(GT_BASE+GT_PCI1_COMMAND_OFS)#define GT_PCI0_TIMEOUT_RETRY		(GT_BASE+GT_PCI0_TIMEOUT_RETRY_OFS)#define GT_PCI1_TIMEOUT_RETRY		(GT_BASE+GT_PCI1_TIMEOUT_RETRY_OFS)#define GT_PCI0_SCS10_BANK_SZ		(GT_BASE+GT_PCI0_SCS10_BANK_SZ_OFS)#define GT_PCI1_SCS10_BANK_SZ		(GT_BASE+GT_PCI1_SCS10_BANK_SZ_OFS)#define GT_PCI0_SCS32_BANK_SZ		(GT_BASE+GT_PCI0_SCS32_BANK_SZ_OFS)#define GT_PCI1_SCS32_BANK_SZ		(GT_BASE+GT_PCI1_SCS32_BANK_SZ_OFS)#define GT_PCI0_CS20_BANK_SZ		(GT_BASE+GT_PCI0_CS20_BANK_SZ_OFS)#define GT_PCI1_CS20_BANK_SZ		(GT_BASE+GT_PCI1_CS20_BANK_SZ_OFS)#define GT_PCI0_CS3_BOOTCS_BANK_SZ	(GT_BASE+GT_PCI0_CS3_BOOTCS_BANK_SZ_OFS)#define GT_PCI1_CS3_BOOTCS_BANK_SZ	(GT_BASE+GT_PCI1_CS3_BOOTCS_BANK_SZ_OFS)#define GT_PCI0_BASE_ADRS_REGS_ENABLE	(GT_BASE+GT_PCI0_BASE_ADRS_REGS_ENABLE_OFS)#define GT_PCI1_BASE_ADRS_REGS_ENABLE	(GT_BASE+GT_PCI1_BASE_ADRS_REGS_ENABLE_OFS)#define GT_PCI0_PREFETCH_MAX_BURST_SZ	(GT_BASE+GT_PCI0_PREFETCH_MAX_BURST_SZ_OFS)#define GT_PCI1_PREFETCH_MAX_BURST_SZ	(GT_BASE+GT_PCI1_PREFETCH_MAX_BURST_SZ_OFS)#define GT_PCI0_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SCS10_BASE_ADRS_REMAP_OFS)#define GT_PCI1_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SCS10_BASE_ADRS_REMAP_OFS)#define GT_PCI0_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SCS32_BASE_ADRS_REMAP_OFS)#define GT_PCI1_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SCS32_BASE_ADRS_REMAP_OFS)#define GT_PCI0_CS20_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_CS20_BASE_ADRS_REMAP_OFS)#define GT_PCI1_CS20_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_CS20_BASE_ADRS_REMAP_OFS)#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)#define GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS)#define GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS)#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS)#define GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS)#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)#define GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP	(GT_BASE+GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)#define GT_PCI0_CFG_ADRS		(GT_BASE+GT_PCI0_CFG_ADRS_OFS)#define GT_PCI1_CFG_ADRS		(GT_BASE+GT_PCI1_CFG_ADRS_OFS)#define GT_PCI0_CFG_DATA_VIRT		(GT_BASE+GT_PCI0_CFG_DATA_VIRT_OFS)#define GT_PCI1_CFG_DATA_VIRT		(GT_BASE+GT_PCI1_CFG_DATA_VIRT_OFS)#define GT_PCI0_INTR_ACK_VIRT		(GT_BASE+GT_PCI0_INTR_ACK_VIRT_OFS)#define GT_PCI1_INTR_ACK_VIRT		(GT_BASE+GT_PCI1_INTR_ACK_VIRT_OFS)/* Interrupts */#define GT_INTR_CAUSE			(GT_BASE+GT_INTR_CAUSE_OFS)#define GT_H_INTR_CAUSE			(GT_BASE+GT_H_INTR_CAUSE_OFS)#define GT_CPU_INTR_MASK		(GT_BASE+GT_CPU_INTR_MASK_OFS)#define GT_CPU_H_INTR_MASK		(GT_BASE+GT_CPU_H_INTR_MASK_OFS)#define GT_PCI0_INTR_CAUSE_MASK		(GT_BASE+GT_PCI0_INTR_CAUSE_MASK_OFS)#define GT_PCI0_H_INTR_CAUSE_MASK	(GT_BASE+GT_PCI0_H_INTR_CAUSE_MASK_OFS)#define GT_PCI0_SERR0_MASK		(GT_BASE+GT_PCI0_SERR0_MASK_OFS)#define GT_PCI1_SERR1_MASK		(GT_BASE+GT_PCI1_SERR1_MASK_OFS)#define GT_CPU_SELECT_CAUSE		(GT_BASE+GT_CPU_SELECT_CAUSE_OFS)#define GT_PCI0_INTR_SELECT		(GT_BASE+GT_PCI0_INTR_SELECT_OFS)/* * I2O Support Registers * * "I20 registers can be accessed from the CPU and PCI_0 sides (unless * stated otherwise). If accessed from the PCI_0 side, address offset is * with respect to the PCI_0 SCS[1:0]* Base Address Register contents. * If accessed from the CPU side, the address offset is with respect to * the CPU Internal Space Base Register + 0x1c00" *			-- GT64120A Data Sheet Revision 1.0 p. 171 */#define GT_I2O_CPU_BASE_OFS		0x1c00#define GT_INBOUND_MESSAGE_0		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_MESSAGE_0_OFS)#define GT_INBOUND_MESSAGE_1		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_MESSAGE_1_OFS)#define GT_OUTBOUND_MESSAGE_0		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_MESSAGE_0_OFS)#define GT_OUTBOUND_MESSAGE_1		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_MESSAGE_1_OFS)#define GT_INBOUND_DOORBELL		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_DOORBELL_OFS)#define GT_INBOUND_INTR_CAUSE		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_INTR_CAUSE_OFS)#define GT_INBOUND_INTR_MASK		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_INTR_MASK_OFS)#define GT_OUTBOUND_DOORBELL		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_DOORBELL_OFS)#define GT_OUTBOUND_INTR_CAUSE		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_INTR_CAUSE_OFS)#define GT_OUTBOUND_INTR_MASK		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_INTR_MASK_OFS)#define GT_INBOUND_QUEUE_PORT_VIRT	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_QUEUE_PORT_VIRT_OFS)#define GT_OUTBOUND_QUEUE_PORT_VIRT	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_QUEUE_PORT_VIRT_OFS)#define GT_QUEUE_CTL			(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_QUEUE_CTL_OFS)#define GT_QUEUE_BASE_ADRS		(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_QUEUE_BASE_ADRS_OFS)#define GT_INBOUND_FREE_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_FREE_HEAD_PTR_OFS)#define GT_INBOUND_FREE_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_FREE_TAIL_PTR_OFS)#define GT_INBOUND_POST_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_POST_HEAD_PTR_OFS)#define GT_INBOUND_POST_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_POST_TAIL_PTR_OFS)#define GT_OUTBOUND_FREE_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_FREE_HEAD_PTR_OFS)#define GT_OUTBOUND_FREE_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_FREE_TAIL_PTR_OFS)#define GT_OUTBOUND_POST_HEAD_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_POST_HEAD_PTR_OFS)#define GT_OUTBOUND_POST_TAIL_PTR	(GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_POST_TAIL_PTR_OFS)/*********************************************************************** * * Register encodings * ***********************************************************************//* create a mask of n ones */#ifndef GT_MSK#define GT_MSK(n)				((1 << (n)) - 1)#endif/* for CPU Interface Config: GT_CPU_INTF_CFG */#define GT_CACHEOPMAP_SHF		0#define GT_CACHEOPMAP_MSK		(GT_MSK(9) << GT_CACHEOPMAP_SHF)#define GT_CACHEPRES_SHF		9#define GT_CACHEPRES_MSK		(GT_MSK(1) << GT_CACHEPRES_SHF)#define GT_CACHEPRES_BIT		GT_CACHEPRES_MSK#define GT_CACHEPRES_GT64012_NOT_PRESENT	0#define GT_CACHEPRES_GT64012_PRESENT	1#define GT_WRITEMODE_SHF		11#define GT_WRITEMODE_MSK		(GT_MSK(1) << GT_WRITEMODE_SHF)#define GT_WRITEMODE_BIT		GT_WRITEMODE_MSK#define GT_WRITEMODE_PIPELINED		0#define GT_WRITEMODE_R4000		1#define GT_ENDIANESS_SHF		12#define GT_ENDIANESS_MSK		(GT_MSK(1) << GT_ENDIANESS_SHF)#define GT_ENDIANESS_BIT		GT_ENDIANESS_MSK#define GT_ENDIANESS_BIG		0#define GT_ENDIANESS_LITTLE		1#define GT_R5KL2_PRESENT_SHF		14#define GT_R5KL2_PRESENT_MSK		(GT_MSK(1) << GT_R5KL2_PRESENT_SHF)#define GT_R5KL2_PRESENT_BIT		GT_R5KL2_PRESENT_MSK#define GT_R5KL2_PRESENT_NOT_PRESENT	0#define GT_R5KL2_PRESENT_PRESENT	1#define GT_EXTERNAL_HIT_DELAY_SHF	15#define GT_EXTERNAL_HIT_DELAY_MSK	(GT_MSK(1) << GT_EXTERNAL_HIT_DELAY_SHF)#define GT_EXTERNAL_HIT_DELAY_BIT	GT_EXTERNAL_HIT_DELAY_MSK#define GT_EXTERNAL_HIT_DELAY_NON_REGISTERED	0#define GT_EXTERNAL_HIT_DELAY_REGISTERED	1#define GT_CPU_WRITE_RATE_SHF		16#define GT_CPU_WRITE_RATE_MSK		(GT_MSK(1) << GT_CPU_WRITE_RATE_SHF)#define GT_CPU_WRITE_RATE_BIT		GT_CPU_WRITE_RATE_MSK#define GT_CPU_WRITE_RATE_DXDXDXDX	0#define GT_CPU_WRITE_RATE_DDDD		1#define GT_STOP_RETRY_SHF		17#define GT_STOP_RETRY_MSK		(GT_MSK(1) << GT_STOP_RETRY_SHF)#define GT_STOP_RETRY_BIT		GT_STOP_RETRY_MSK#define GT_STOP_RETRY_CONTINUE		0#define GT_STOP_RETRY_STOP		1#define GT_MULTIGT_SHF			18#define GT_MULTIGT_MSK			(GT_MSK(1) << GT_MULTIGT_SHF)#define GT_MULTIGT_BIT			GT_MULTIGT_BIT#define GT_MULTIGT_NOT_SUPPORTED	0#define GT_MULTIGT_SUPPORTED		1#define GT_SYSADCVALID_SHF		19#define GT_SYSADCVALID_MSK		(GT_MSK(1) << GT_SYSADCVALID_SHF)#define GT_SYSADCVALID_BIT		GT_SYSADCVALID_MSK#define GT_SYSADCVALID_NOT_CONNECTED	0#define GT_SYSADCVALID_CONNECTED	1#define GT_PCI0OVERRIDE_SHF		20#define GT_PCI0OVERRIDE_MSK		(GT_MSK(2) << GT_PCI0OVERRIDE_SHF)#define GT_PCI0OVERRIDE_NORMAL		0	/* normal address decoding */#define GT_PCI0OVERRIDE_1GBYTE		1	/* 1 GB PCI_0 Mem0 space */#define GT_PCI0OVERRIDE_2GBYTE		2	/* 2 GB PCI_0 Mem0 space */#define GT_PCI1OVERRIDE_SHF		24#define GT_PCI1OVERRIDE_MSK		(GT_MSK(2) << GT_PCI1OVERRIDE_SHF)#define GT_PCI1OVERRIDE_NORMAL		0	/* normal address decoding */#define GT_PCI1OVERRIDE_1GBYTE		1	/* 1 GB PCI_1 Mem0 space */#define GT_PCI1OVERRIDE_2GBYTE		2	/* 2 GB PCI_1 Mem0 space *//* * for Internal Space Decode: GT_INTERNAL_SPACE_DEC */#define GT_INTERNAL_SPACE_DEC_DEF	0x000000a0/* for SDRAM Configuration: GT_SDRAM_CFG */#define GT_SDRAM_CFG_REFINTCNT_SHF	0#define GT_SDRAM_CFG_REFINTCNT_MSK	(GT_MSK(14) << GT_SDRAM_CFG_REFINTCNT_SHF)#define GT_SDRAM_CFG_INTERLEAVE_SHF	14#define GT_SDRAM_CFG_INTERLEAVE_MSK    (GT_MSK(1) << GT_SDRAM_CFG_INTERLEAVE_SHF)#define GT_SDRAM_CFG_INTERLEAVE_BIT	GT_SDRAM_CFG_INTERLEAVE_MSK#define GT_SDRAM_CFG_INTERLEAVE_ENABLED	0#define GT_SDRAM_CFG_INTERLEAVE_DISABLED	1#define GT_SDRAM_CFG_RMW_SHF		15#define GT_SDRAM_CFG_RMW_MSK		(GT_MSK(1) << GT_SDRAM_CFG_RMW_SHF)#define GT_SDRAM_CFG_RMW_BIT		GT_SDRAM_CFG_RMW_MSK#define GT_SDRAM_CFG_RMW_DISABLED	0#define GT_SDRAM_CFG_RMW_ENABLED	1#define GT_SDRAM_CFG_STAGREF_SHF	16#define GT_SDRAM_CFG_STAGREF_MSK	(GT_MSK(1) << GT_SDRAM_CFG_STAGREF_SHF)#define GT_SDRAM_CFG_STAGREF_BIT	GT_SDRAM_CFG_STAGREF_MSK#define GT_SDRAM_CFG_STAGREF_STAGGERED	0#define GT_SDRAM_CFG_STAGREF_NON_STAGGERED	1#define GT_SDRAM_CFG_CPUTODRAMERR_SHF	17#define GT_SDRAM_CFG_CPUTODRAMERR_MSK	(GT_MSK(1) << GT_SDRAM_CFG_CPUTODRAMERR_SHF)#define GT_SDRAM_CFG_CPUTODRAMERR_BIT	GT_SDRAM_CFG_CPUTODRAMERR_MSK#define GT_SDRAM_CFG_CPUTODRAMERR_GENERATE_ERR	0#define GT_SDRAM_CFG_CPUTODRAMERR_ALWAYS_GOOD	1#define GT_SDRAM_CFG_ECCINT_SHF		18#define GT_SDRAM_CFG_ECCINT_MSK		(GT_MSK(1) << GT_SDRAM_CFG_ECCINT_SHF)#define GT_SDRAM_CFG_ECCINT_BIT		GT_SDRAM_CFG_ECCINT_MSK#define GT_SDRAM_CFG_ECCINT_2_ERRORS	0#define GT_SDRAM_CFG_ECCINT_1_ERROR	1#define GT_SDRAM_CFG_DUPCNTL_SHF	19#define GT_SDRAM_CFG_DUPCNTL_MSK	(GT_MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)#define GT_SDRAM_CFG_DUPCNTL_BIT	GT_SDRAM_CFG_DUPCNTL_MSK#define GT_SDRAM_CFG_DUPBA_SHF		20#define GT_SDRAM_CFG_DUPBA_MSK		(GT_MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)#define GT_SDRAM_CFG_DUPBA_BIT		GT_SDRAM_CFG_DUPBA_MSK#define GT_SDRAM_CFG_DUPBA_DO_NOT_DUP	0
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -