gt64120a.h

IXP425的BSP代码

/* gt64120a.h - Galileo gt64120A bridge device header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,26apr02,dat  Adding cplusplus protection, SPR 75017
01a,15jun00,dra	 Written from earlier Galileo version of BSP.
*/

/*
* This file contains register offsets and programming values for the
* GT64120A bridge chip, which appears on the Galileo Technologies ev64120a
* evaluation board.
*/

/* Copyright (c) Galileo Technology Inc. All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY GALILEO TECHNOLOGY INC. ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL GALILEO TECHNOLOGY INC. BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * ANY REDISTRIBUTION OF THIS SOURCE CODE MUST RETAIN THE COPYRIGHT AND
 * DECLARATION STATED ABOVE.
 *
 */

#ifndef __INCgt64120ah
#define __INCgt64120ah

#ifdef __cplusplus
extern "C" {
#endif

/**********************************************************************
 *
 * GT64120A Internal Register OFFSETS
 *
 **********************************************************************/

/* CPU Configuration */
#define GT_CPU_INTF_CFG_OFS			0x000
#define GT_MULTI_GT_REG_OFS			0x120

/* CPU Address Decode */
#define GT_SCS10_L_DEC_ADRS_OFS			0x008
#define GT_SCS10_H_DEC_ADRS_OFS			0x010
#define GT_SCS32_L_DEC_ADRS_OFS			0x018
#define GT_SCS32_H_DEC_ADRS_OFS			0x020
#define GT_CS20_L_DEC_ADRS_OFS			0x028
#define GT_CS20_H_DEC_ADRS_OFS			0x030
#define GT_CS3_BOOTCS_L_DEC_ADRS_OFS		0x038
#define GT_CS3_BOOTCS_H_DEC_ADRS_OFS		0x040
#define GT_PCI0_IO_L_DEC_ADRS_OFS		0x048
#define GT_PCI0_IO_H_DEC_ADRS_OFS		0x050
#define GT_PCI0_MEM_0_L_DEC_ADRS_OFS		0x058
#define GT_PCI0_MEM_0_H_DEC_ADRS_OFS		0x060
#define GT_PCI0_MEM_1_L_DEC_ADRS_OFS		0x080
#define GT_PCI0_MEM_1_H_DEC_ADRS_OFS		0x088
#define GT_PCI1_IO_L_DEC_ADRS_OFS		0x090
#define GT_PCI1_IO_H_DEC_ADRS_OFS		0x098
#define GT_PCI1_MEM_0_L_DEC_ADRS_OFS		0x0a0
#define GT_PCI1_MEM_0_H_DEC_ADRS_OFS		0x0a8
#define GT_PCI1_MEM_1_L_DEC_ADRS_OFS		0x0b0
#define GT_PCI1_MEM_1_H_DEC_ADRS_OFS		0x0b8
#define GT_INTERNAL_SPACE_DEC_OFS		0x068
#define GT_SCS10_ADRS_REMAP_OFS			0x0d0
#define GT_SCS32_ADRS_REMAP_OFS			0x0d8
#define GT_CS20_REMAP_OFS			0x0e0
#define GT_CS3_BOOTCS_REMAP_OFS			0x0e8
#define GT_PCI0_IO_REMAP_OFS			0x0f0
#define GT_PCI0_MEM_0_REMAP_OFS			0x0f8
#define GT_PCI0_MEM_1_REMAP_OFS			0x100
#define GT_PCI1_IO_REMAP_OFS			0x108
#define GT_PCI1_MEM_0_REMAP_OFS			0x110
#define GT_PCI1_MEM_1_REMAP_OFS			0x118

/* CPU Errors Report */
#define GT_CPU_ERROR_ADRS_L_OFS			0x070
#define GT_CPU_ERROR_ADRS_H_OFS			0x078
#define GT_CPU_ERROR_DATA_L_OFS			0x128
#define GT_CPU_ERROR_DATA_H_OFS			0x130
#define GT_CPU_ERROR_PARITY_OFS			0x138

/* CPU Sync Barrier */
#define GT_PCI0_SYNC_BARRIER_VIRT_OFS		0x0c0
#define GT_PCI1_SYNC_BARRIER_VIRT_OFS		0x0c8

/* SDRAM and Device Address Decode */
#define GT_SCS0_L_DEC_ADRS_OFS			0x400
#define GT_SCS0_H_DEC_ADRS_OFS			0x404
#define GT_SCS1_L_DEC_ADRS_OFS			0x408
#define GT_SCS1_H_DEC_ADRS_OFS			0x40c
#define GT_SCS2_L_DEC_ADRS_OFS			0x410
#define GT_SCS2_H_DEC_ADRS_OFS			0x414
#define GT_SCS3_L_DEC_ADRS_OFS			0x418
#define GT_SCS3_H_DEC_ADRS_OFS			0x41c
#define GT_CS0_L_DEC_ADRS_OFS			0x420
#define GT_CS0_H_DEC_ADRS_OFS			0x424
#define GT_CS1_L_DEC_ADRS_OFS			0x428
#define GT_CS1_H_DEC_ADRS_OFS			0x42c
#define GT_CS2_L_DEC_ADRS_OFS			0x430
#define GT_CS2_H_DEC_ADRS_OFS			0x434
#define GT_CS3_L_DEC_ADRS_OFS			0x438
#define GT_CS3_H_DEC_ADRS_OFS			0x43c
#define GT_BOOTCS_L_DEC_ADRS_OFS		0x440
#define GT_BOOTCS_H_DEC_ADRS_OFS		0x444
#define GT_ADRS_DEC_ERROR_OFS			0x470

/* SDRAM Configuration */
#define GT_SDRAM_CFG_OFS			0x448
#define GT_SDRAM_OP_MODE_OFS			0x474
#define GT_SDRAM_BURST_MODE_OFS			0x478
#define GT_SDRAM_ADRS_DEC_OFS			0x47c

/* SDRAM Parameters */
#define GT_SDRAM_BANK0_PARAM_OFS		0x44c
#define GT_SDRAM_BANK1_PARAM_OFS		0x450
#define GT_SDRAM_BANK2_PARAM_OFS		0x454
#define GT_SDRAM_BANK3_PARAM_OFS		0x458

/* ECC */
#define GT_ECC_ERROR_ADRS_OFS			0x490
#define GT_ECC_ERROR_DATA_H_OFS			0x480
#define GT_ECC_ERROR_DATA_L_OFS			0x484
#define GT_ECC_FROM_MEM_OFS			0x488
#define GT_ECC_CALCULATED_OFS			0x48c

/* Device Parameters*/
#define GT_DEV_BANK0_PARAM_OFS			0x45c
#define GT_DEV_BANK1_PARAM_OFS			0x460
#define GT_DEV_BANK2_PARAM_OFS			0x464
#define GT_DEV_BANK3_PARAM_OFS			0x468
#define GT_DEV_BOOT_BANK_PARAM_OFS		0x46c

/* DMA Record */
#define GT_CHAN_0_DMA_BYTE_COUNT_OFS		0x800
#define GT_CHAN_1_DMA_BYTE_COUNT_OFS		0x804
#define GT_CHAN_2_DMA_BYTE_COUNT_OFS		0x808
#define GT_CHAN_3_DMA_BYTE_COUNT_OFS		0x80c
#define GT_CHAN_0_DMA_SRC_ADRS_OFS		0x810
#define GT_CHAN_1_DMA_SRC_ADRS_OFS		0x814
#define GT_CHAN_2_DMA_SRC_ADRS_OFS		0x818
#define GT_CHAN_3_DMA_SRC_ADRS_OFS		0x81c
#define GT_CHAN_0_DMA_DEST_ADRS_OFS		0x820
#define GT_CHAN_1_DMA_DEST_ADRS_OFS		0x824
#define GT_CHAN_2_DMA_DEST_ADRS_OFS		0x828
#define GT_CHAN_3_DMA_DEST_ADRS_OFS		0x82c
#define GT_CHAN_0_NEXT_REC_PTR_OFS		0x830
#define GT_CHAN_1_NEXT_REC_PTR_OFS		0x834
#define GT_CHAN_2_NEXT_REC_PTR_OFS		0x838
#define GT_CHAN_3_NEXT_REC_PTR_OFS		0x83c
#define GT_CHAN_0_CURRENT_DESCRIPTOR_PTR_OFS	0x870
#define GT_CHAN_1_CURRENT_DESCRIPTOR_PTR_OFS	0x874
#define GT_CHAN_2_CURRENT_DESCRIPTOR_PTR_OFS	0x878
#define GT_CHAN_3_CURRENT_DESCRIPTOR_PTR_OFS	0x87c
#define GT_CHAN_0_CTL_OFS			0x840
#define GT_CHAN_1_CTL_OFS			0x844
#define GT_CHAN_2_CTL_OFS			0x848
#define GT_CHAN_3_CTL_OFS			0x84c

/* DMA Arbiter */
#define GT_ARBITER_CTL_OFS			0x860

/* Timer/COUNTER */
#define GT_TIMER_COUNTER_0_OFS			0x850
#define GT_TIMER_COUNTER_1_OFS			0x854
#define GT_TIMER_COUNTER_2_OFS			0x858
#define GT_TIMER_COUNTER_3_OFS			0x85c
#define GT_TIMER_COUNTER_CTL_OFS		0x864

/* PCI Internal */
#define GT_PCI0_COMMAND_OFS			0xc00
#define GT_PCI1_COMMAND_OFS			0xc80
#define GT_PCI0_TIMEOUT_RETRY_OFS		0xc04
#define GT_PCI1_TIMEOUT_RETRY_OFS		0xc84
#define GT_PCI0_SCS10_BANK_SZ_OFS		0xc08
#define GT_PCI1_SCS10_BANK_SZ_OFS		0xc88
#define GT_PCI0_SCS32_BANK_SZ_OFS		0xc0c
#define GT_PCI1_SCS32_BANK_SZ_OFS		0xc8c
#define GT_PCI0_CS20_BANK_SZ_OFS		0xc10
#define GT_PCI1_CS20_BANK_SZ_OFS		0xc90
#define GT_PCI0_CS3_BOOTCS_BANK_SZ_OFS		0xc14
#define GT_PCI1_CS3_BOOTCS_BANK_SZ_OFS		0xc94
#define GT_PCI0_BASE_ADRS_REGS_ENABLE_OFS	0xc3c
#define GT_PCI1_BASE_ADRS_REGS_ENABLE_OFS	0xcbc
#define GT_PCI0_PREFETCH_MAX_BURST_SZ_OFS	0xc40
#define GT_PCI1_PREFETCH_MAX_BURST_SZ_OFS	0xcc0
#define GT_PCI0_SCS10_BASE_ADRS_REMAP_OFS	0xc48
#define GT_PCI1_SCS10_BASE_ADRS_REMAP_OFS	0xcc8
#define GT_PCI0_SCS32_BASE_ADRS_REMAP_OFS	0xc4c
#define GT_PCI1_SCS32_BASE_ADRS_REMAP_OFS	0xccc
#define GT_PCI0_CS20_BASE_ADRS_REMAP_OFS	0xc50
#define GT_PCI1_CS20_BASE_ADRS_REMAP_OFS	0xcd0
#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xc54
#define GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xcd4
#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS	0xc58
#define GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS	0xcd8
#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS	0xc5c
#define GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS	0xcdc
#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xc64
#define GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS	0xce4
#define GT_PCI0_CFG_ADRS_OFS			0xcf8
#define GT_PCI1_CFG_ADRS_OFS			0xcf0
#define GT_PCI0_CFG_DATA_VIRT_OFS		0xcfc
#define GT_PCI1_CFG_DATA_VIRT_OFS		0xcf4
#define GT_PCI0_INTR_ACK_VIRT_OFS		0xc34
#define GT_PCI1_INTR_ACK_VIRT_OFS		0xc30

/* Interrupts */
#define GT_INTR_CAUSE_OFS			0xc18
#define GT_H_INTR_CAUSE_OFS			0xc98
#define GT_CPU_INTR_MASK_OFS			0xc1c
#define GT_CPU_H_INTR_MASK_OFS			0xc9c
#define GT_PCI0_INTR_CAUSE_MASK_OFS		0xc24
#define GT_PCI0_H_INTR_CAUSE_MASK_OFS		0xca4
#define GT_PCI0_SERR0_MASK_OFS			0xc28
#define GT_PCI1_SERR1_MASK_OFS			0xca8
#define GT_CPU_SELECT_CAUSE_OFS			0xc70
#define GT_PCI0_INTR_SELECT_OFS			0xc74

/*
 * PCI Configuration
 * 
 * This is done by writing a register offset from pciConfigLib.h into
 * GT_PCI0_CFG_ADRS, and then writing or reading the register value at
 * GT_PCI0_CFG_DATA_VIRT.  For register offsets, use definitions from
 * pciConfigLib.h
 *
 * for PCI1, use GT_PCI1_CFG_{ADRS,DATA_VIRT}. Alternatively, add the
 * constant offset GT_PCI1_CFG_OFS to the register offset, and use
 * GT_PCI0_CFG_{ADRS,DATA_VIRT}
 */

#define GT_PCI1_CFG_OFS				0x080

#define GT_PCI0_SCS10_BASE_ADRS_OFS		PCI_CFG_BASE_ADDRESS_0
#define GT_PCI0_SCS32_BASE_ADRS_OFS		PCI_CFG_BASE_ADDRESS_1
#define GT_PCI0_CS20_BASE_ADRS_OFS		PCI_CFG_BASE_ADDRESS_2
#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_OFS	PCI_CFG_BASE_ADDRESS_3
#define GT_PCI0_INTERNAL_REGS_MEM_MAPPED_BASE_ADRS_OFS	PCI_CFG_BASE_ADDRESS_4
#define GT_PCI0_INTERNAL_REGS_IO_MAPPED_BASE_ADRS_OFS	PCI_CFG_BASE_ADDRESS_5
#define GT_EXPANSION_ROM_BASE_ADRS_OFS		PCI_CFG_EXPANSION_ROM

/* PCI Configuration, Function 1 */
#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_OFS	0x110
#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_OFS	0x114
#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_OFS	0x11c

/* I2O Support Registers */
#define GT_INBOUND_MESSAGE_0_OFS		0x10
#define GT_INBOUND_MESSAGE_1_OFS		0x14
#define GT_OUTBOUND_MESSAGE_0_OFS		0x18
#define GT_OUTBOUND_MESSAGE_1_OFS		0x1c
#define GT_INBOUND_DOORBELL_OFS			0x20
#define GT_INBOUND_INTR_CAUSE_OFS		0x24
#define GT_INBOUND_INTR_MASK_OFS			0x28
#define GT_OUTBOUND_DOORBELL_OFS		0x2c
#define GT_OUTBOUND_INTR_CAUSE_OFS		0x30
#define GT_OUTBOUND_INTR_MASK_OFS		0x34
#define GT_INBOUND_QUEUE_PORT_VIRT_OFS		0x40
#define GT_OUTBOUND_QUEUE_PORT_VIRT_OFS		0x44
#define GT_QUEUE_CTL_OFS			0x50
#define GT_QUEUE_BASE_ADRS_OFS			0x54
#define GT_INBOUND_FREE_HEAD_PTR_OFS		0x60
#define GT_INBOUND_FREE_TAIL_PTR_OFS		0x64
#define GT_INBOUND_POST_HEAD_PTR_OFS		0x68
#define GT_INBOUND_POST_TAIL_PTR_OFS		0x6c
#define GT_OUTBOUND_FREE_HEAD_PTR_OFS		0x70
#define GT_OUTBOUND_FREE_TAIL_PTR_OFS		0x74
#define GT_OUTBOUND_POST_HEAD_PTR_OFS		0x78
#define GT_OUTBOUND_POST_TAIL_PTR_OFS		0x7c


/**********************************************************************
 *
 * GT64120A Internal Register ABSOLUTE ADDRESSES
 *
 * These require the includer of this header to define a GT_BASE macro.
 * Here's an assembly-language example:
 *
 *   #include <gt64120a.h>
 *
 *   #define K1BASE	0xa0000000	/@ MIPS base address for phys mem @/
 *   #define GT_BASE	(K1BASE | GT_INTERNAL_REGS_BASE_DEF)
 *
 *	   lw	   k0,GT_CPU_INTF_CFG	/@ get CPU Interface Configuration @/
 *
 **********************************************************************/

/* Default memory map */

#define GT_SCS0_BASE_DEF		0x00000000
#define GT_SCS1_BASE_DEF		0x00800000
#define GT_SCS2_BASE_DEF		0x01000000
#define GT_SCS3_BASE_DEF		0x01800000
#define GT_PCI0_IO_0_BASE_DEF		0x10000000
#define GT_PCI0_MEM_0_BASE_DEF		0x12000000
#define GT_INTERNAL_REGS_BASE_DEF	0x14000000
#define GT_CS0_BASE_DEF			0x1c000000
#define GT_CS1_BASE_DEF			0x1c800000
#define GT_CS2_BASE_DEF			0x1d000000
#define GT_CS3_BASE_DEF			0x1f000000
#define GT_BOOTCS_BASE_DEF		0x1fc00000
#define GT_PCI1_IO_BASE_DEF		0x20000000
#define GT_PCI1_MEM_0_BASE_DEF		0x22000000
#define GT_PCI1_MEM_1_BASE_DEF		0x24000000
#define GT_PCI0_MEM_1_BASE_DEF		0xf2000000

/* CPU Configuration */
#define GT_CPU_INTF_CFG			(GT_BASE+GT_CPU_INTF_CFG_OFS)
#define GT_MULTI_GT_REG			(GT_BASE+GT_MULTI_GT_REG_OFS)

/* CPU Address Decode */
#define GT_SCS10_L_DEC_ADRS		(GT_BASE+GT_SCS10_L_DEC_ADRS_OFS)
#define GT_SCS10_H_DEC_ADRS		(GT_BASE+GT_SCS10_H_DEC_ADRS_OFS)
#define GT_SCS32_L_DEC_ADRS		(GT_BASE+GT_SCS32_L_DEC_ADRS_OFS)
#define GT_SCS32_H_DEC_ADRS		(GT_BASE+GT_SCS32_H_DEC_ADRS_OFS)
#define GT_CS20_L_DEC_ADRS		(GT_BASE+GT_CS20_L_DEC_ADRS_OFS)
#define GT_CS20_H_DEC_ADRS		(GT_BASE+GT_CS20_H_DEC_ADRS_OFS)
#define GT_CS3_BOOTCS_L_DEC_ADRS	(GT_BASE+GT_CS3_BOOTCS_L_DEC_ADRS_OFS)
#define GT_CS3_BOOTCS_H_DEC_ADRS	(GT_BASE+GT_CS3_BOOTCS_H_DEC_ADRS_OFS)
#define GT_PCI0_IO_L_DEC_ADRS		(GT_BASE+GT_PCI0_IO_L_DEC_ADRS_OFS)
#define GT_PCI0_IO_H_DEC_ADRS		(GT_BASE+GT_PCI0_IO_H_DEC_ADRS_OFS)
#define GT_PCI0_MEM_0_L_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_0_L_DEC_ADRS_OFS)
#define GT_PCI0_MEM_0_H_DEC_ADRS	(GT_BASE+GT_PCI0_MEM_0_H_DEC_ADRS_OFS)