mpc105.h

IXP425的BSP代码

#define PICR2_CF_HIT_HIGH	    0x00010000	/* Cache HIT signal polarity */
#define PICR2_CF_ADDR_ONLY_DISABLE  0x00004000	/* L2 normal operation */
#define PICR2_CF_HOLD		    0x00002000	/* L2 tag address hold */
#define PICR2_CF_INV_MODE	    0x00001000	/* L2 invalidate mode enable */
#define PICR2_CF_L2_HIT_DELAY(n)    ((n)<<9)	/* L2 cache hit delay */
#define PICR2_CF_BURST_RATE	    0x00000100	/* L2 cache burst rate */
#define PICR2_CF_FAST_CASTOUT	    0x00000080	/* Fast L2 castout timing */
#define PICR2_TOE_WIDTH		    0x00000040	/* TOE active pulse width */
#define PICR2_L2_SIZE		    0x00000030	/* L2 cache size mask */
#define	PICR2_L2_SIZE_256K	    0x00000000
#define	PICR2_L2_SIZE_512K	    0x00000010
#define	PICR2_L2_SIZE_1MEG	    0x00000020
#define PICR2_CF_APHASE_WS(n)	    ((n)<<2)	/* Address phase wait states */
#define PICR2_CF_DOE		    0x00000002	/* 1st data read access tim. */
#define PICR2_CF_WDATA		    0x00000001	/* 1st data write setup time */


/* OS Visible Parameters Register 1 - 0xba */

#define OS_VPR1_RX_SERR_EN	0X20	/* Assertion of SERR from other PCI */ 
#define OS_VPR1_XIO_MODE	0X04	/* Contiguous IO mode address map A */
#define OS_VPR1_TEA_EN		0X02	/* Transfer error enable */ 
#define OS_VPR1_MCP_EN		0X01	/* Machine check enable */ 

/* OS Visible Parameters Register 2 - 0xbb */

#define OS_VPR2_FLASH_WR_EN	0x01	/* Flash write enable */

/* Error Enable Register 1 (ERR_EN_R1) - 0xc0 */

#define ERR_EN_R1_TGT_ABRT      0x80	/* PCI target-abort error */
#define ERR_EN_R1_TGT_PERR      0x40	/* PCI target PERR */
#define ERR_EN_R1_MEM_SEL_ER    0x20 	/* Memory select error */
#define ERR_EN_R1_MASTER_PERR   0x10	/* PCI master PERR */
#define ERR_EN_R1_MEM_RD_PARITY 0x04 	/* Memory read parity error */
#define ERR_EN_R1_MASTER_ABRT   0x02 	/* PCI master-abort error */
#define ERR_EN_R1_60X_BUS_ER    0x01 	/* 60x bus error */

/* Error Detection Register 1 (ERR_DR1_PCI) - 0xc1 */

#define ERR_DR1_PCI_SERR        0x80	/* PCI SERR signaled */
#define ERR_DR1_TGT_PERR        0x40	/* PCI target PERR */
#define ERR_DR1_MEM_SEL_ER      0x20	/* Memory select error */
#define ERR_DR1_60XPCI_CYCLE    0x80	/* 60x/PCI cycle */
#define ERR_DR1_MEM_RD_PARITY     0x40	/* Memory read parity error */
#define ERR_DR1_NO_60XBUS_CYCLE 0x03	/* Unsupported 60x bus cycle */

/* 60x Bus Error Status Register - 0xc3 */

#define BESR_TT0_TT4		0xf8	/* TT0-TT4 signals copy */
#define BESR_TSIZ0_TSIZ2	0x07	/* TSIZ0-TSIZ2 signals copy */

/* Error Enable Register 2 (ERR_EN_R2) - 0xc4 */

#define ERR_EN_R2_L2_PARITY     0x10 	/* L2 Parity error */
#define ERR_EN_R2_FLASHROM_WRT  0x01 	/* FLASH ROM write error */

/* Error Detection Register 2 (ERR_DR2) - 0xc5 */

#define ERR_DR2_INVLD_ER_ADR    0x80	/* Invalid error address */
#define ERR_DR2_L2_PARITY       0x10	/* L2 parity error */
#define ERR_DR2_FLASHROM_WRT    0x01	/* FLASH ROM write error */

/* PCI Bus Error Status Register - 0xc7 */

#define PCI_BESR_MSTR_TGT	0x10	/* Master/target status */
#define PCI_BESR_CBE3_CBE0	0x0f	/* C/BE3-C/BE0 copy */

/* 60x/PCI Error Address Register - 0xc8 */

#define PCI_EAR_A24_A31_MSK	0xff000000	/* 60x: A24-A31 PCI: AD7-AD0 */
#define PCI_EAR_A16_A23_MSK	0x00ff0000	/* 60x: A16-A23 PCI: AD15-AD8 */
#define PCI_EAR_A8_A15_MSK	0x0000ff00	/* 60x: A8-A15 PCI: AD23-AD16 */
#define PCI_EAR_A0_A7_MSK	0x000000ff	/* 60x: A0-A7 PCI: AD31-AD24 */

/* Memory Control Configuration Register 1 (MCCR1) - 0xf0 */

#define MCCR1_ROMNAL_MASK	0xf0000000
#define MCCR1_ROMNAL(n)		((n)<<28)
#define MCCR1_ROMFAL_MASK	0x0f800000
#define MCCR1_ROMFAL(n)		((n)<<23)
#define MCCR1_FNR		0x00400000	/* Flash ROM configuration */
#define MCCR1_32N64		0x00200000	/* 64/32 Bit data bus wide */
#define MCCR1_BURST		0x00100000	/* Burst mode Rom access */
#define MCCR1_MEMGO		0x00080000	/* MPC105 RAM interface enable*/
#define MCCR1_SREN		0x00040000	/* DRam Self Refresh enable */
#define MCCR1_RAMTYP		0x00020000	/* DRAM type (synch/standard) */
#define MCCR1_PCKEN		0x00010000	/* Parity Check/gen. enable */
#define MCCR1_BK7_9BITS		0x00000000	/* Bank 7 -  9 row bits */
#define MCCR1_BK7_10BITS	0x00004000	/* Bank 7 - 10 row bits */
#define MCCR1_BK7_11BITS	0x00008000	/* Bank 7 - 11 row bits */
#define MCCR1_BK7_12BITS	0x0000c000	/* Bank 7 - 12 row bits */
#define MCCR1_BK6_9BITS		0x00000000	/* Bank 6 -  9 row bits */
#define MCCR1_BK6_10BITS	0x00001000	/* Bank 6 - 10 row bits */
#define MCCR1_BK6_11BITS	0x00002000	/* Bank 6 - 11 row bits */
#define MCCR1_BK6_12BITS	0x00003000	/* Bank 6 - 12 row bits */
#define MCCR1_BK5_9BITS		0x00000000	/* Bank 5 -  9 row bits */
#define MCCR1_BK5_10BITS	0x00000400	/* Bank 5 - 10 row bits */
#define MCCR1_BK5_11BITS	0x00000800	/* Bank 5 - 11 row bits */
#define MCCR1_BK5_12BITS	0x00000c00	/* Bank 5 - 12 row bits */
#define MCCR1_BK4_9BITS		0x00000000	/* Bank 4 -  9 row bits */
#define MCCR1_BK4_10BITS	0x00000100	/* Bank 4 - 10 row bits */
#define MCCR1_BK4_11BITS	0x00000200	/* Bank 4 - 11 row bits */
#define MCCR1_BK4_12BITS	0x00000300	/* Bank 4 - 12 row bits */
#define MCCR1_BK3_9BITS		0x00000000	/* Bank 3 -  9 row bits */
#define MCCR1_BK3_10BITS	0x00000040	/* Bank 3 - 10 row bits */
#define MCCR1_BK3_11BITS	0x00000080	/* Bank 3 - 11 row bits */
#define MCCR1_BK3_12BITS	0x000000c0	/* Bank 3 - 12 row bits */
#define MCCR1_BK2_9BITS		0x00000000	/* Bank 2 -  9 row bits */
#define MCCR1_BK2_10BITS	0x00000010	/* Bank 2 - 10 row bits */
#define MCCR1_BK2_11BITS	0x00000020	/* Bank 2 - 11 row bits */
#define MCCR1_BK2_12BITS	0x00000030	/* Bank 2 - 12 row bits */
#define MCCR1_BK1_9BITS		0x00000000	/* Bank 1 -  9 row bits */
#define MCCR1_BK1_10BITS	0x00000004	/* Bank 1 - 10 row bits */
#define MCCR1_BK1_11BITS	0x00000008	/* Bank 1 - 11 row bits */
#define MCCR1_BK1_12BITS	0x0000000c	/* Bank 1 - 12 row bits */
#define MCCR1_BK0_9BITS		0x00000000	/* Bank 0 -  9 row bits */
#define MCCR1_BK0_10BITS	0x00000001	/* Bank 0 - 10 row bits */
#define MCCR1_BK0_11BITS	0x00000002	/* Bank 0 - 11 row bits */
#define MCCR1_BK0_12BITS	0x00000003	/* Bank 0 - 12 row bits */

/* Memory Control Configuration Register 2 (MCCR2) - 0xf4 */

#define MCCR2_SRF		0xfffc0000	/* Self-refesh entry delay */
#define MCCR2_REFINT		0x0000fffc	/* Refresh interval */
#define MCCR2_BUF		0x00000002	/* Buffer mode */
#define MCCR2_WMODE		0x00000001	/* 8 beats per burst */

/* Memory Control Configuration Register 3 (MCCR3) - 0xf8 */

#define MCCR3_RDTOACT_MSK	0xf0000000	/* Read to active interval */
#define MCCR3_REFREC_MSK	0x0f000000	/* Refresh to active interval */
#define MCCR3_RDLAT_MSK		0x00f00000	/* Data latency from read cmd */
#define MCCR3_RAS6P_MSK		0x00078000	/* RAS assertion interval mask*/
#define MCCR3_RAS6P(n)		((n)<<15)	/* RAS assertion interval */
#define MCCR3_CAS5_MSK		0x00007000	/* CAS assertion interval mask*/
#define MCCR3_CAS5(n)		((n)<<12)	/* CAS assertion interval */
#define MCCR3_CP4_MSK		0x00000e00	/* CAS precharge interval mask*/
#define MCCR3_CP4(n)		((n)<<9)	/* CAS precharge interval */
#define MCCR3_CAS3_MSK		0x000001c0	/* CAS assertion 1st access */
#define MCCR3_CAS3(n)		((n)<<6)	/* CAS assertion 1st access */
#define MCCR3_RCD2_MSK		0x00000038	/* RAS to CAS delay interval */
#define MCCR3_RCD2(n)		((n)<<3)	/* RAS to CAS delay interval */
#define MCCR3_RP1_MSK		0x00000007	/* RAS precharge interval */
#define MCCR3_RP1(n)		(n)/* RAS precharge interval */

/* Memory Control Configuration Register 4 (MCCR4) - 0xfc */

#define MCCR4_PRETOACT		0xf0000000	/* Precharge to act. intvl */
#define MCCR4_ACTOPRE		0x0f000000	/* Activate to prech. intvl */
#define MCCR4_WCBUF		0x00200000	/* Memory write buffer type */
#define MCCR4_RCBUF		0x00100000	/* Memory read buffer type */
#define MCCR4_SDMODE		0x000fff00	/* SDRAM mode register data */
#define MCCR4_ACTORW		0x000000f0	/* Act. to read/write intvl */
#define MCCR4_WRTOACT		0x0000000f	/* Write to activate intvl */

/* External Configuration Register 1 - 0x80000092 */

#define ECR1_LE_MODE		0x02	/* Little-endian mode */ 

/* External Configuration Register 2 - 0x8000081c */

#define ECR2_L2_UPDATE_EN	0x80	/* Update cache misses */
#define ECR2_L2_EN		0x40	/* L2 cache enable */
#define ECR2_TEA_EN		0x20	/* Transfer error enable */
#define ECR2_CF_FLUSH_L2	0x10	/* L2 cache flush */

/* External Configuration Register 3 - 0x80000850 */

#define ECR3_XIO_MODE		0x01	/* Contiguous IO mode address map A*/

/* first parameter to mpc105Ioctl */

#define MPC105_IOCTL_WRITE      0
#define MPC105_IOCTL_READ       1
#define MPC105_IOCTL_OR         2
#define MPC105_IOCTL_AND        3
#define MPC105_IOCTL_AND_OR     4
#define MPC105_IOCTL_AND_NOT    5

#define SWAP32(x)	((((x) & 0x000000ff) << 24) |	\
			(((x) & 0x0000ff00) <<  8)  |	\
			(((x) & 0x00ff0000) >>  8)  |	\
			(((unsigned int)(x)) >> 24))
#define B2L_ENDIAN(x)   SWAP32(x)
#define L2B_ENDIAN(x)   SWAP32(x)


#ifndef _ASMLANGUAGE

#if     defined(__STDC__) || defined(__cplusplus)

extern void     mpc105Init      (void * devAddr);
extern void     mpc105Dram      (void * devAddr, int boardType, int speedMhz);
extern void     mpc105Ioctl     (int op, int regSize, int regNum,
                                 unsigned int wdata1, unsigned int wdata2);

#else   /* !__STDC__ */

extern void     mpc105Init      ();
extern void     mpc105Dram      ();
extern void     mpc105Ioctl     ();

#endif	/* (__STDC__) || (__cplusplus) */

#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCmpc105h */