mpc105.h

IXP425的BSP代码

/* mpc105.h - Motorola MPC105 PCI Bridge/Memory Controller */

/* Copyright 1984-1996 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,10oct96,tam  added missing macros.
01a,03apr96,tpr  written.
*/

/*
This file contains the related constants for the MPC105.
*/

#ifndef __INCmpc105h
#define __INCmpc105h

#ifdef __cplusplus
extern "C" {
#endif

#define MPC105_VEND_ID		0x00	/* Vendor ID Reg */
#define MPC105_DEV_ID		0x02	/* Device ID Reg */
#define MPC105_CMD		0x04	/* Pci Command Reg */
#define MPC105_STAT		0x06	/* Pci Status Reg */
#define MPC105_PMCR		0x70	/* Power Management Configuration Reg */
#define MPC105_MSAR1		0x80	/* Memory Starting Address Register 1 */
#define MPC105_MSAR2		0x84	/* Memory Starting Address Register 2 */
#define MPC105_EMSAR1		0x88	/* Extended Memory Start Addr Reg 1 */
#define MPC105_EMSAR2		0x8c	/* Extended Memory Start Addr Reg 2 */
#define MPC105_MEAR1		0x90	/* Memory Ending Address Register 1 */
#define MPC105_MEAR2		0x94	/* Memory Ending Address Register 2 */
#define MPC105_EMEAR1		0x98	/* Extended Memory Ending Addr Reg 1 */
#define MPC105_EMEAR2		0x9c	/* Extended Memory Ending Addr Reg 2 */
#define MPC105_MBER		0xa0	/* Memory Bank Enable Register */
#define MPC105_PICR1		0xa8	/* Processor Interface Config. Reg 1 */
#define MPC105_PICR2		0xac	/* Processor Interface Config. Reg 2 */
#define MPC105_OS_VPR1		0xba	/* OS Visible Parameters Register 1 */	
#define MPC105_OS_VPR2		0xbb	/* OS Visible Parameters Register 2 */	
#define MPC105_ERR_EN_R1	0xc0	/* Error Enable Register 1 */
#define MPC105_ERR_DR1		0xc1	/* Error Detection Register 1 */
#define MPC105_60X_BESR		0xc3	/* 60x Bus Error Status Register */
#define MPC105_ERR_EN_R2	0xc4	/* Error Enable Register 2 */
#define MPC105_ERR_DR2		0xc5	/* Error Detection Register 2 */
#define MPC105_PCI_BESR		0xc7	/* PCI Bus Error Status Register */
#define MPC105_60XPCI_EAR	0xc8	/* 60x/PCI Error Address Register */
#define MPC105_MCCR1		0xf0	/* Memory Control Configuration Reg 1 */
#define MPC105_MCCR2		0xf4	/* Memory Control Configuration Reg 2 */
#define MPC105_MCCR3		0xf8	/* Memory Control Configuration Reg 3 */
#define MPC105_MCCR4		0xfc	/* Memory Control Configuration Reg 4 */

/* External Configuration Registers - Address Map A */

#define MPC105_ECR1		0x80000092 /* External Configuration Reg 1 */
#define MPC105_ECR2		0x8000081c /* External Configuration Reg 2 */
#define MPC105_ECR3		0x80000850 /* External Configuration Reg 3 */

/* Other registers are accessed indirectly via the registers below */

#define	MPC105_REG_SELECT	(int *)0x80000cf8 /* register select */
#define	MPC105_REG_DATA		(int *)0x80000cfc /* register data */
#define	MPC105_REG(nn)		((nn << 24) | 0x80)

/* Pci Command Reg (CMD) - 0x04 */

#define CMD_SERR		0x0100	/* enable SERR signal */
#define CMD_PAR_ERR		0x0040	/* respond to parity errors */
#define CMD_PCI_MASTER		0x0004	/* generate pci mem. accesses */
#define CMD_PCI_SLAVE		0x0002	/* respond to pci mem. accesses */

/* Pci Status Reg (STAT) - 0x6 */

#define STAT_PAR_ERR		0x8000	/* parity error detected */
#define STAT_SERR		0x4000	/* SERR is asserted */
#define STAT_MASTER_MST_ABORT	0x2000	/* transaction using master-abort */
#define STAT_MASTER_TGT_ABORT	0x1000	/* transaction using master-abort */
#define STAT_TARGET_TGT_ABORT	0x0800	/* transaction using master-abort */
#define STAT_DATA_PAR_ERR	0x0100	/* data parity error detected */
#define STAT_NO_RSV_BITS	0xf900	/* non reserved or non hardwired bits */


/* Power Management Configuration Register (PMCR) - 0x70 */

#define PMCR_NO_NAP_MSG		0x8000	/* HALT command broadcast */
#define PMCR_NO_SLEEP_MSG	0x4000	/* Sleep message broadcast */
#define PMCR_SLEEP_MSG_TYPE	0x2000	/* Sleep message type */
#define PMCR_LP_REF_EN		0x1000	/* Low-power refresh enable */
#define PMCR_NO_604_RUN		0x0800	/* Do not assert QACK (PPC604 only) */
#define PMCR_601_NEED_QREQ	0x0400	/* QREQ requested (PPC601 only) */
#define PMCR_SUSP_QACK		0x0200	/* Suspend mode will assert QACK */
#define PMCR_PM			0x0080	/* Power Management enable */
#define PMCR_DOZE		0x0020	/* Doze mode enable */
#define PMCR_NAP		0x0010	/* Nap mode enable */
#define PMCR_SLEEP		0x0008	/* Sleep mode enable */
#define PMCR_CKO_EN		0x0004	/* test clock output driver enable */
#define PMCR_CKO_SEL		0x0002	/* Selects the clock source */
#define PMCR_BR1_WAKE		0x0001	/* Enable awareness of a second CPU */

/* Memory Starting Address Register 1 - 0x80 */

#define MSAR1_BANK3_MSK		0xff000000	/* Starting addr for bank 3 */
#define MSAR1_BANK2_MSK		0x00ff0000	/* Starting addr for bank 2 */
#define MSAR1_BANK1_MSK		0x0000ff00	/* Starting addr for bank 1 */
#define MSAR1_BANK0_MSK		0x000000ff	/* Starting addr for bank 0 */

/* Memory Starting Address Register 2 - 0x84 */

#define MSAR2_BANK7_MSK		0xff000000	/* Starting addr for bank 7 */
#define MSAR2_BANK6_MSK		0x00ff0000	/* Starting addr for bank 6 */
#define MSAR2_BANK5_MSK		0x0000ff00	/* Starting addr for bank 5 */
#define MSAR2_BANK4_MSK		0x000000ff	/* Starting addr for bank 4 */

/* Extended Memory Start Address Register 1 - 0x88 */

#define EMSAR1_BANK3_MSK	0x03000000	/* Extended starting addr 3 */ 
#define EMSAR1_BANK2_MSK	0x00030000	/* Extended starting addr 2 */ 
#define EMSAR1_BANK1_MSK	0x00000300	/* Extended starting addr 1 */ 
#define EMSAR1_BANK0_MSK	0x00000003	/* Extended starting addr 0 */ 

/* Extended Memory Start Address Register 2 - 0x8c */

#define EMSAR2_BANK7_MSK	0x03000000	/* Extended starting addr 7 */ 
#define EMSAR2_BANK6_MSK	0x00030000	/* Extended starting addr 6 */ 
#define EMSAR2_BANK5_MSK	0x00000300	/* Extended starting addr 5 */ 
#define EMSAR2_BANK4_MSK	0x00000003	/* Extended starting addr 4 */ 

/* Memory Ending Address Register 1 - 0x90 */

#define MEAR1_BANK3_MSK         0xff000000      /* Ending addr for bank 3 */
#define MEAR1_BANK2_MSK         0x00ff0000      /* Ending addr for bank 2 */
#define MEAR1_BANK1_MSK         0x0000ff00      /* Ending addr for bank 1 */
#define MEAR1_BANK0_MSK         0x000000ff      /* Ending addr for bank 0 */

/* Memory Ending Address Register 2 - 0x94 */

#define MEAR2_BANK7_MSK         0xff000000      /* Ending addr for bank 7 */
#define MEAR2_BANK6_MSK         0x00ff0000      /* Ending addr for bank 6 */
#define MEAR2_BANK5_MSK         0x0000ff00      /* Ending addr for bank 5 */
#define MEAR2_BANK4_MSK         0x000000ff      /* Ending addr for bank 4 */

/* Extended Memory Ending Address Register 1 - 0x98 */

#define EMEAR1_BANK3_MSK	0x03000000	/* Extended ending addr 3 */ 
#define EMEAR1_BANK2_MSK	0x00030000	/* Extended ending addr 2 */ 
#define EMEAR1_BANK1_MSK	0x00000300	/* Extended ending addr 1 */ 
#define EMEAR1_BANK0_MSK	0x00000003	/* Extended ending addr 0 */ 

/* Extended Memory Ending Address Register 2 - 0x9c */

#define EMEAR2_BANK7_MSK	0x03000000	/* Extended ending addr 7 */ 
#define EMEAR2_BANK6_MSK	0x00030000	/* Extended ending addr 6 */ 
#define EMEAR2_BANK5_MSK	0x00000300	/* Extended ending addr 5 */ 
#define EMEAR2_BANK4_MSK	0x00000003	/* Extended ending addr 4 */ 

/* Memory Bank Enable Register - 0xa0 */

#define MBER_BANK7		0x80		/* Enable/disable bank 7 */
#define MBER_BANK6		0x40		/* Enable/disable bank 6 */
#define MBER_BANK5		0x20		/* Enable/disable bank 5 */
#define MBER_BANK4		0x10		/* Enable/disable bank 4 */
#define MBER_BANK3		0x08		/* Enable/disable bank 3 */
#define MBER_BANK2		0x04		/* Enable/disable bank 2 */
#define MBER_BANK1		0x02		/* Enable/disable bank 1 */
#define MBER_BANK0		0x01		/* Enable/disable bank 0 */

/* Processor Interface Configuration Register 1 (PICR1) - 0xa8 */

#define PICR1_CF_CBA_MASK	0xff000000	/* L2 copy-back address mask */
#define PICR1_CF_CBA(n)		((n)<<24)
#define PICR1_CF_BREAD_WS(n)	((n)<<22)	/* Burst read wait states */
#define PICR1_CF_CACHE_1G	0x00200000	/* L2 cache 0-1Gbyte only */
#define PICR1_RCS0 		0x00100000	/* ROM location: PCI or 60x */
#define PICR1_XIO_MODE 		0x00080000	/* Discontigous IO mode map A */
#define PICR1_PROC_TYPE_MASK 	0x00060000	/* Processor type */
#define PICR1_PROC_TYPE_601 	0x00000000	/* Processor type */
#define PICR1_PROC_TYPE_603 	0x00040000	/* Processor type */
#define PICR1_PROC_TYPE_604 	0x00060000	/* Processor type */
#define PICR1_XATS		0x00010000	/* Address map: A or B */
#define PICR1_CF_MP_ID		0x00008000	/* Multiprocessor id */
#define PICR1_CF_LBA_EN		0x00002000	/* Local bus slave access en */
#define PICR1_FLASH_WR_EN	0x00001000	/* Flash writes enable */
#define PICR1_MCP_EN		0x00000800	/* Machine check enable */
#define PICR1_TEA_EN		0x00000400	/* Transfer error enable */ 
#define PICR1_CF_DPARK		0x00000200	/* 60x parked on data bus */
#define PICR1_NO_PORT_REGS	0x00000080	/* No ext configuration reg */ 
#define PICR1_ST_GATH_EN	0x00000040	/* Store gathering of writes */
#define PICR1_LE_MODE		0x00000020	/* Little-Endian mode */
#define PICR1_CF_LOOP_SNOOP	0x00000010	/* Snoop looping enable */
#define PICR1_CF_APARK		0x00000008	/* 60x parked on address bus */
#define PICR1_SPEC_PCI_READ	0x00000004	/* Speculative PCI reads en */
#define PICR1_CF_L2_CACHE_MASK	0x00000003	/* L2/multiprocessor config. */
#define	PICR1_CF_L2_NOCACHE	0x00000000
#define	PICR1_CF_L2_WRITE_THROUGH 0x00000001
#define	PICR1_CF_L2_COPY_BACK	0x00000002
#define	PICR1_CF_L2_MP		0x00000003


/* Processor Interface Configuration Register 2 (PICR2) - 0xac */

#define PICR2_L2_UPDATE_EN	    0x80000000	/* Update cache misses */
#define PICR2_L2_EN		    0x40000000	/* L2 cache enable */
#define PICR2_CF_FLUSH_L2	    0x10000000	/* Initiate L2 cache flush */
#define PICR2_CF_BYTE_DECODE	    0x02000000	/* on-chip byte-write decode */
#define PICR2_CF_FAST_L2_MODE	    0x01000000	/* Fast L2 mode timing */
#define PICR2_CF_DATA_RAM_TYPE	    0x00c00000	/* L2 data RAM type */
#define	PICR2_CF_DATA_RAM_SYNC	    0x00000000
#define	PICR2_CF_DATA_RAM_ASYNC	    0x00800000
#define PICR2_CF_WMODE		    0x00300000	/* SRAM write timing */
#define	PICR2_CF_WMODE_NORMAL	    0x00100000
#define	PICR2_CF_WMODE_DELAY	    0x00200000
#define	PICR2_CF_WMODE_EARLY	    0x00300000
#define PICR2_CF_SNOOP_WS(n)	    ((n)<<18)	/* Snoop wait states */
#define PICR2_CF_MOD_HIGH	    0x00020000	/* Cache mod. signal polarity */