vmechip2.h

IXP425的BSP代码

#define	ILR2_DMA_LEVEL7		(7 << 24)  /* DMA Controller Int Lvl 7	26-24 */

#define	ILR2_SIG3_LEVEL1	(1 << 20)  /* GCSR SIG3 Int on Level 1	22-20 */
#define	ILR2_SIG3_LEVEL2	(2 << 20)  /* GCSR SIG3 Int on Level 2	22-20 */
#define	ILR2_SIG3_LEVEL3	(3 << 20)  /* GCSR SIG3 Int on Level 3	22-20 */
#define	ILR2_SIG3_LEVEL4	(4 << 20)  /* GCSR SIG3 Int on Level 4	22-20 */
#define	ILR2_SIG3_LEVEL5	(5 << 20)  /* GCSR SIG3 Int on Level 5	22-20 */
#define	ILR2_SIG3_LEVEL6	(6 << 20)  /* GCSR SIG3 Int on Level 6	22-20 */
#define	ILR2_SIG3_LEVEL7	(7 << 20)  /* GCSR SIG3 Int on Level 7	22-20 */

#define	ILR2_SIG2_LEVEL1	(1 << 16)  /* GCSR SIG2 Int on Level 1	18-16 */
#define	ILR2_SIG2_LEVEL2	(2 << 16)  /* GCSR SIG2 Int on Level 2	18-16 */
#define	ILR2_SIG2_LEVEL3	(3 << 16)  /* GCSR SIG2 Int on Level 3	18-16 */
#define	ILR2_SIG2_LEVEL4	(4 << 16)  /* GCSR SIG2 Int on Level 4	18-16 */
#define	ILR2_SIG2_LEVEL5	(5 << 16)  /* GCSR SIG2 Int on Level 5	18-16 */
#define	ILR2_SIG2_LEVEL6	(6 << 16)  /* GCSR SIG2 Int on Level 6	18-16 */
#define	ILR2_SIG2_LEVEL7	(7 << 16)  /* GCSR SIG2 Int on Level 7	18-16 */

#define	ILR2_SIG1_LEVEL1	(1 << 12)  /* GCSR SIG1 Int on Level 1	14-12 */
#define	ILR2_SIG1_LEVEL2	(2 << 12)  /* GCSR SIG1 Int on Level 2	14-12 */
#define	ILR2_SIG1_LEVEL3	(3 << 12)  /* GCSR SIG1 Int on Level 3	14-12 */
#define	ILR2_SIG1_LEVEL4	(4 << 12)  /* GCSR SIG1 Int on Level 4	14-12 */
#define	ILR2_SIG1_LEVEL5	(5 << 12)  /* GCSR SIG1 Int on Level 5	14-12 */
#define	ILR2_SIG1_LEVEL6	(6 << 12)  /* GCSR SIG1 Int on Level 6	14-12 */
#define	ILR2_SIG1_LEVEL7	(7 << 12)  /* GCSR SIG1 Int on Level 7	14-12 */

#define	ILR2_SIG0_LEVEL1	(1 << 8)   /* GCSR SIG0 Int on Level 1	10-8 */
#define	ILR2_SIG0_LEVEL2	(2 << 8)   /* GCSR SIG0 Int on Level 2	10-8 */
#define	ILR2_SIG0_LEVEL3	(3 << 8)   /* GCSR SIG0 Int on Level 3	10-8 */
#define	ILR2_SIG0_LEVEL4	(4 << 8)   /* GCSR SIG0 Int on Level 4	10-8 */
#define	ILR2_SIG0_LEVEL5	(5 << 8)   /* GCSR SIG0 Int on Level 5	10-8 */
#define	ILR2_SIG0_LEVEL6	(6 << 8)   /* GCSR SIG0 Int on Level 6	10-8 */
#define	ILR2_SIG0_LEVEL7	(7 << 8)   /* GCSR SIG0 Int on Level 7	10-8 */

#define	ILR2_LM1_LEVEL1		(1 << 4)   /* GCSR LM1 Int on Level 1	6-4 */
#define	ILR2_LM1_LEVEL2		(2 << 4)   /* GCSR LM1 Int on Level 2	6-4 */
#define	ILR2_LM1_LEVEL3		(3 << 4)   /* GCSR LM1 Int on Level 3	6-4 */
#define	ILR2_LM1_LEVEL4		(4 << 4)   /* GCSR LM1 Int on Level 4	6-4 */
#define	ILR2_LM1_LEVEL5		(5 << 4)   /* GCSR LM1 Int on Level 5	6-4 */
#define	ILR2_LM1_LEVEL6		(6 << 4)   /* GCSR LM1 Int on Level 6	6-4 */
#define	ILR2_LM1_LEVEL7		(7 << 4)   /* GCSR LM1 Int on Level 7	6-4 */

#define	ILR2_LM0_LEVEL1		1	   /* GCSR LM0 Int on Level 1	2-0 */
#define	ILR2_LM0_LEVEL2		2	   /* GCSR LM0 Int on Level 2	2-0 */
#define	ILR2_LM0_LEVEL3		3	   /* GCSR LM0 Int on Level 3	2-0 */
#define	ILR2_LM0_LEVEL4		4	   /* GCSR LM0 Int on Level 4	2-0 */
#define	ILR2_LM0_LEVEL5		5	   /* GCSR LM0 Int on Level 5	2-0 */
#define	ILR2_LM0_LEVEL6		6	   /* GCSR LM0 Int on Level 6	2-0 */
#define	ILR2_LM0_LEVEL7		7	   /* GCSR LM0 Int on Level 7	2-0 */

/* Interrupt Level Register 3				0x80	31-00	*/

#define	ILR3_SW7_LEVEL7		(7 << 28)  /* Software Inter 7 on Lvl 7	30-28 */
#define	ILR3_SW7_LEVEL7		(7 << 28)  /* Software Inter 7 on Lvl 7	30-28 */
#define	ILR3_SW7_LEVEL7		(7 << 28)  /* Software Inter 7 on Lvl 7	30-28 */
#define	ILR3_SW7_LEVEL7		(7 << 28)  /* Software Inter 7 on Lvl 7	30-28 */
#define	ILR3_SW7_LEVEL7		(7 << 28)  /* Software Inter 7 on Lvl 7	30-28 */
#define	ILR3_SW7_LEVEL7		(7 << 28)  /* Software Inter 7 on Lvl 7	30-28 */
#define	ILR3_SW7_LEVEL7		(7 << 28)  /* Software Inter 7 on Lvl 7	30-28 */

#define	ILR3_SW6_LEVEL1		(1 << 24)  /* Software Inter 6 on Lvl 1	26-24 */
#define	ILR3_SW6_LEVEL2		(2 << 24)  /* Software Inter 6 on Lvl 2	26-24 */
#define	ILR3_SW6_LEVEL3		(3 << 24)  /* Software Inter 6 on Lvl 3	26-24 */
#define	ILR3_SW6_LEVEL4		(4 << 24)  /* Software Inter 6 on Lvl 4	26-24 */
#define	ILR3_SW6_LEVEL5		(5 << 24)  /* Software Inter 6 on Lvl 5	26-24 */
#define	ILR3_SW6_LEVEL6		(6 << 24)  /* Software Inter 6 on Lvl 6	26-24 */
#define	ILR3_SW6_LEVEL7		(7 << 24)  /* Software Inter 6 on Lvl 7	26-24 */

#define	ILR3_SW5_LEVEL1		(1 << 20)  /* Software Inter 5 on Lvl 1	22-20 */
#define	ILR3_SW5_LEVEL2		(2 << 20)  /* Software Inter 5 on Lvl 2	22-20 */
#define	ILR3_SW5_LEVEL3		(3 << 20)  /* Software Inter 5 on Lvl 3	22-20 */
#define	ILR3_SW5_LEVEL4		(4 << 20)  /* Software Inter 5 on Lvl 4	22-20 */
#define	ILR3_SW5_LEVEL5		(5 << 20)  /* Software Inter 5 on Lvl 5	22-20 */
#define	ILR3_SW5_LEVEL6		(6 << 20)  /* Software Inter 5 on Lvl 6	22-20 */
#define	ILR3_SW5_LEVEL7		(7 << 20)  /* Software Inter 5 on Lvl 7	22-20 */

#define	ILR3_SW4_LEVEL1		(1 << 16)  /* Software Inter 4 on Lvl 1	18-16 */
#define	ILR3_SW4_LEVEL2		(2 << 16)  /* Software Inter 4 on Lvl 2	18-16 */
#define	ILR3_SW4_LEVEL3		(3 << 16)  /* Software Inter 4 on Lvl 3	18-16 */
#define	ILR3_SW4_LEVEL4		(4 << 16)  /* Software Inter 4 on Lvl 4	18-16 */
#define	ILR3_SW4_LEVEL5		(5 << 16)  /* Software Inter 4 on Lvl 5	18-16 */
#define	ILR3_SW4_LEVEL6		(6 << 16)  /* Software Inter 4 on Lvl 6	18-16 */
#define	ILR3_SW4_LEVEL7		(7 << 16)  /* Software Inter 4 on Lvl 7	18-16 */

#define	ILR3_SW3_LEVEL1		(1 << 12)  /* Software Inter 3 on Lvl 1	14-12 */
#define	ILR3_SW3_LEVEL2		(2 << 12)  /* Software Inter 3 on Lvl 2	14-12 */
#define	ILR3_SW3_LEVEL3		(3 << 12)  /* Software Inter 3 on Lvl 3	14-12 */
#define	ILR3_SW3_LEVEL4		(4 << 12)  /* Software Inter 3 on Lvl 4	14-12 */
#define	ILR3_SW3_LEVEL5		(5 << 12)  /* Software Inter 3 on Lvl 5	14-12 */
#define	ILR3_SW3_LEVEL6		(6 << 12)  /* Software Inter 3 on Lvl 6	14-12 */
#define	ILR3_SW3_LEVEL7		(7 << 12)  /* Software Inter 3 on Lvl 7	14-12 */

#define	ILR3_SW2_LEVEL1		(1 << 8)   /* Software Inter 2 on Lvl 1	10-8 */
#define	ILR3_SW2_LEVEL2		(2 << 8)   /* Software Inter 2 on Lvl 2	10-8 */
#define	ILR3_SW2_LEVEL3		(3 << 8)   /* Software Inter 2 on Lvl 3	10-8 */
#define	ILR3_SW2_LEVEL4		(4 << 8)   /* Software Inter 2 on Lvl 4	10-8 */
#define	ILR3_SW2_LEVEL5		(5 << 8)   /* Software Inter 2 on Lvl 5	10-8 */
#define	ILR3_SW2_LEVEL6		(6 << 8)   /* Software Inter 2 on Lvl 6	10-8 */
#define	ILR3_SW2_LEVEL7		(7 << 8)   /* Software Inter 2 on Lvl 7	10-8 */

#define	ILR3_SW1_LEVEL1		(1 << 4)   /* Software Inter 1 on Lvl 1	6-4 */
#define	ILR3_SW1_LEVEL2		(2 << 4)   /* Software Inter 1 on Lvl 2	6-4 */
#define	ILR3_SW1_LEVEL3		(3 << 4)   /* Software Inter 1 on Lvl 3	6-4 */
#define	ILR3_SW1_LEVEL4		(4 << 4)   /* Software Inter 1 on Lvl 4	6-4 */
#define	ILR3_SW1_LEVEL5		(5 << 4)   /* Software Inter 1 on Lvl 5	6-4 */
#define	ILR3_SW1_LEVEL6		(6 << 4)   /* Software Inter 1 on Lvl 6	6-4 */
#define	ILR3_SW1_LEVEL7		(7 << 4)   /* Software Inter 1 on Lvl 7	6-4 */

#define	ILR3_SW0_LEVEL1		1	   /* Software Inter 0 on Lvl 1	2-0 */
#define	ILR3_SW0_LEVEL2		2	   /* Software Inter 0 on Lvl 2	2-0 */
#define	ILR3_SW0_LEVEL3		3	   /* Software Inter 0 on Lvl 3	2-0 */
#define	ILR3_SW0_LEVEL4		4	   /* Software Inter 0 on Lvl 4	2-0 */
#define	ILR3_SW0_LEVEL5		5	   /* Software Inter 0 on Lvl 5	2-0 */
#define	ILR3_SW0_LEVEL6		6	   /* Software Inter 0 on Lvl 6	2-0 */
#define	ILR3_SW0_LEVEL7		7	   /* Software Inter 0 on Lvl 7	2-0 */

/* Interrupt Level Register 4				0x84	31-00	*/

#define	ILR4_VIRQ7_LEVEL1	(1 << 24)  /* VMEbus IRQ7 on Level 1	26-24 */
#define	ILR4_VIRQ7_LEVEL2	(2 << 24)  /* VMEbus IRQ7 on Level 2	26-24 */
#define	ILR4_VIRQ7_LEVEL3	(3 << 24)  /* VMEbus IRQ7 on Level 3	26-24 */
#define	ILR4_VIRQ7_LEVEL4	(4 << 24)  /* VMEbus IRQ7 on Level 4	26-24 */
#define	ILR4_VIRQ7_LEVEL5	(5 << 24)  /* VMEbus IRQ7 on Level 5	26-24 */
#define	ILR4_VIRQ7_LEVEL6	(6 << 24)  /* VMEbus IRQ7 on Level 6	26-24 */
#define	ILR4_VIRQ7_LEVEL7	(7 << 24)  /* VMEbus IRQ7 on Level 7	26-24 */

#define	ILR4_VIRQ6_LEVEL1	(1 << 20)  /* VMEbus IRQ6 on Level 1	22-20 */
#define	ILR4_VIRQ6_LEVEL2	(2 << 20)  /* VMEbus IRQ6 on Level 2	22-20 */
#define	ILR4_VIRQ6_LEVEL3	(3 << 20)  /* VMEbus IRQ6 on Level 3	22-20 */
#define	ILR4_VIRQ6_LEVEL4	(4 << 20)  /* VMEbus IRQ6 on Level 4	22-20 */
#define	ILR4_VIRQ6_LEVEL5	(5 << 20)  /* VMEbus IRQ6 on Level 5	22-20 */
#define	ILR4_VIRQ6_LEVEL6	(6 << 20)  /* VMEbus IRQ6 on Level 6	22-20 */
#define	ILR4_VIRQ6_LEVEL7	(7 << 20)  /* VMEbus IRQ6 on Level 7	22-20 */

#define	ILR4_VIRQ5_LEVEL1	(1 << 16)  /* VMEbus IRQ5 on Level 1	18-16 */
#define	ILR4_VIRQ5_LEVEL2	(2 << 16)  /* VMEbus IRQ5 on Level 2	18-16 */
#define	ILR4_VIRQ5_LEVEL3	(3 << 16)  /* VMEbus IRQ5 on Level 3	18-16 */
#define	ILR4_VIRQ5_LEVEL4	(4 << 16)  /* VMEbus IRQ5 on Level 4	18-16 */
#define	ILR4_VIRQ5_LEVEL5	(5 << 16)  /* VMEbus IRQ5 on Level 5	18-16 */
#define	ILR4_VIRQ5_LEVEL6	(6 << 16)  /* VMEbus IRQ5 on Level 6	18-16 */
#define	ILR4_VIRQ5_LEVEL7	(7 << 16)  /* VMEbus IRQ5 on Level 7	18-16 */

#define	ILR4_VIRQ4_LEVEL1	(1 << 12)  /* VMEbus IRQ4 on Level 1	14-12 */
#define	ILR4_VIRQ4_LEVEL2	(2 << 12)  /* VMEbus IRQ4 on Level 2	14-12 */
#define	ILR4_VIRQ4_LEVEL3	(3 << 12)  /* VMEbus IRQ4 on Level 3	14-12 */
#define	ILR4_VIRQ4_LEVEL4	(4 << 12)  /* VMEbus IRQ4 on Level 4	14-12 */
#define	ILR4_VIRQ4_LEVEL5	(5 << 12)  /* VMEbus IRQ4 on Level 5	14-12 */
#define	ILR4_VIRQ4_LEVEL6	(6 << 12)  /* VMEbus IRQ4 on Level 6	14-12 */
#define	ILR4_VIRQ4_LEVEL7	(7 << 12)  /* VMEbus IRQ4 on Level 7	14-12 */

#define	ILR4_VIRQ3_LEVEL1	(1 << 8)   /* VMEbus IRQ3 on Level 1	10-8 */
#define	ILR4_VIRQ3_LEVEL2	(2 << 8)   /* VMEbus IRQ3 on Level 2	10-8 */
#define	ILR4_VIRQ3_LEVEL3	(3 << 8)   /* VMEbus IRQ3 on Level 3	10-8 */
#define	ILR4_VIRQ3_LEVEL4	(4 << 8)   /* VMEbus IRQ3 on Level 4	10-8 */
#define	ILR4_VIRQ3_LEVEL5	(5 << 8)   /* VMEbus IRQ3 on Level 5	10-8 */
#define	ILR4_VIRQ3_LEVEL6	(6 << 8)   /* VMEbus IRQ3 on Level 6	10-8 */
#define	ILR4_VIRQ3_LEVEL7	(7 << 8)   /* VMEbus IRQ3 on Level 7	10-8 */

#define	ILR4_VIRQ2_LEVEL1	(1 << 4)   /* VMEbus IRQ2 on Level 1	6-4 */
#define	ILR4_VIRQ2_LEVEL2	(2 << 4)   /* VMEbus IRQ2 on Level 2	6-4 */
#define	ILR4_VIRQ2_LEVEL3	(3 << 4)   /* VMEbus IRQ2 on Level 3	6-4 */
#define	ILR4_VIRQ2_LEVEL4	(4 << 4)   /* VMEbus IRQ2 on Level 4	6-4 */
#define	ILR4_VIRQ2_LEVEL5	(5 << 4)   /* VMEbus IRQ2 on Level 5	6-4 */
#define	ILR4_VIRQ2_LEVEL6	(6 << 4)   /* VMEbus IRQ2 on Level 6	6-4 */
#define	ILR4_VIRQ2_LEVEL7	(7 << 4)   /* VMEbus IRQ2 on Level 7	6-4 */

#define	ILR4_VIRQ1_LEVEL1	1	   /* VMEbus IRQ1 on Level 1	2-0 */
#define	ILR4_VIRQ1_LEVEL2	2	   /* VMEbus IRQ1 on Level 2	2-0 */
#define	ILR4_VIRQ1_LEVEL3	3	   /* VMEbus IRQ1 on Level 3	2-0 */
#define	ILR4_VIRQ1_LEVEL4	4	   /* VMEbus IRQ1 on Level 4	2-0 */
#define	ILR4_VIRQ1_LEVEL5	5	   /* VMEbus IRQ1 on Level 5	2-0 */
#define	ILR4_VIRQ1_LEVEL6	6	   /* VMEbus IRQ1 on Level 6	2-0 */
#define	ILR4_VIRQ1_LEVEL7	7	   /* VMEbus IRQ1 on Level 7	2-0 */

/*
 * Vector Base Register					0x88	31-24
 * I/O Control Register 1				0x88	23-16
 * I/O Control Register 2				0x88	15-08
 * I/O Control Register 3				0x88	07-00
 */

#define	IOCR_MEIN		(1 << 23)  /* Enable Interrupts		23 */
#define	IOCR_SYSFL		(1 << 22)  /* SYSFAIL VMEbus Status	22 */
#define	IOCR_ACFL		(1 << 21)  /* ACFAIL VMEbus Status	21 */
#define	IOCR_ABRTL		(1 << 20)  /* ABORT Switch Status	20 */
#define	IOCR_GPOEN3		(1 << 19)  /* GPIO3 Set as Output	19 */
#define	IOCR_GPIEN3		0x00	   /* GPIO3 Set as Input	19 */
#define	IOCR_GPOEN2		(1 << 18)  /* GPIO2 Set as Output	18 */
#define	IOCR_GPIEN2		0x00	   /* GPIO2 Set as Input	18 */
#define	IOCR_GPOEN1		(1 << 17)  /* GPIO1 Set as Output	17 */
#define	IOCR_GPIEN1		0x00	   /* GPIO1 Set as Input	17 */
#define	IOCR_GPOEN0		(1 << 16)  /* GPIO0 Set as Output	16 */
#define	IOCR_GPIEN0		0x00	   /* GPIO0 Set as Input	16 */

#define	IOCR_GPIOO3_HIGH	(1 << 15)  /* GPIO3 set to HIGH		15 */
#define	IOCR_GPIOO3_LOW		0x00	   /* GPIO3 set to LOW		15 */
#define	IOCR_GPIOO2_HIGH	(1 << 14)  /* GPIO2 set to HIGH		14 */
#define	IOCR_GPIOO2_LOW		0x00	   /* GPIO2 set to LOW		14 */
#define	IOCR_GPIOO1_HIGH	(1 << 13)  /* GPIO1 set to HIGH		13 */
#define	IOCR_GPIOO1_LOW		0x00	   /* GPIO1 set to LOW		13 */
#define	IOCR_GPIOO0_HIGH	(1 << 12)  /* GPIO0 set to HIGH		12 */
#define	IOCR_GPIOO0_LOW		0x00	   /* GPIO0 set to LOW		12 */
#define	IOCR_GPIOI3		(1 << 11)  /* GPIO3 Status		11 */
#define	IOCR_GPIOI2		(1 << 10)  /* GPIO2 Status		10 */
#define	IOCR_GPIOI1		(1 << 9)   /* GPIO1 Status		 9 */
#define	IOCR_GPIOI0		(1 << 8)   /* GPIO0 Status		 8 */

#define	IOCR_GPI7		(1 << 7)   /* GPI7 Status		 7 */
#define	IOCR_GPI6		(1 << 6)   /* GPI6 Status		 6 */
#define	IOCR_GPI5		(1 << 5)   /* GPI5 Status		 5 */
#define	IOCR_GPI4		(1 << 4)   /* GPI4 Status		 4 */
#define	IOCR_GPI3		(1 << 3)   /* GPI3 Status		 3 */
#define	IOCR_GPI2		(1 << 2)   /* GPI2 Status		 2 */
#define	IOCR_GPI1		(1 << 1)   /* GPI1 Status		 1 */
#define	IOCR_GPI0		1	   /* GPI0 Status		 0 */

/* Miscellaneous Control Register			0x8c	07-00 */

#define	MISCCR_DISSRAM		(1 << 5)   /* Disable SRAM decoder       5 */

/* VMEchip2 LM/SIG Register				0x06	*/

#define	LM_SIG_LM3		0x80	  /* Location Monitor 3		7 */
#define	LM_SIG_LM2		0x40	  /* Location Monitor 2		6 */
#define	LM_SIG_LM1		0x20	  /* Location Monitor 1		5 */
#define	LM_SIG_LM0		0x10	  /* Location Monitor 0		4 */
#define	LM_SIG_SIG3		0x08	  /* SIG3			3 */
#define	LM_SIG_SIG2		0x04	  /* SIG2			2 */
#define	LM_SIG_SIG1		0x02	  /* SIG1			1 */
#define	LM_SIG_SIG0		0x01	  /* SIG0			0 */

/* VMEchip2 Board Status/Control Register		0x07	*/

#define	BSCR_RST		0x80	  /* Allow VMEbus master reset	7 */
#define	BSCR_ISF		0x40	  /* Inhibit SYSFAIL to VMEbus	6 */
#define	BSCR_BF			0x20	  /* Board Fail active		5 */
#define	BSCR_SCON		0x10	  /* Board is System Controller	4 */
#define	BSCR_SYSFL		0x08	  /* Board Driving SYSFAIL	3 */


/*
 * Local Bus Interrupter Summary (2-65 of '167 manual)
 * These are values for the interrupt vector related to various
 * interrupts generated locally.
 */

/* These have the upper 4 bits defined by the contents of
 * vector base register 1
 */
#define	LBIV_SOFTWARE0		0x08
#define	LBIV_SOFTWARE1		0x09
#define	LBIV_SOFTWARE2		0x0a
#define	LBIV_SOFTWARE3		0x0b
#define	LBIV_SOFTWARE4		0x0c
#define	LBIV_SOFTWARE5		0x0d
#define	LBIV_SOFTWARE6		0x0e
#define	LBIV_SOFTWARE7		0x0f

/* These have the upper 4 bits defined by the contents of
 * vector base register 0
 */
#define	LBIV_GCSR_LM0		0x00
#define	LBIV_GCSR_LM1		0x01
#define	LBIV_GCSR_SIG0		0x02
#define	LBIV_GCSR_SIG1		0x03
#define	LBIV_GCSR_SIG2		0x04
#define	LBIV_GCSR_SIG3		0x05
#define	LBIV_DMAC		0x06
#define	LBIV_VIA		0x07
#define	LBIV_TT1		0x08
#define	LBIV_TT2		0x09
#define	LBIV_VIRQ1_ES		0x0a
#define	LBIV_PARITY_ERROR	0x0b
#define	LBIV_VMWPE		0x0c
#define	LBIV_VME_SYSFAIL	0x0d
#define	LBIV_ABORT		0x0e
#define	LBIV_VME_ACFAIL		0x0f

#ifdef __cplusplus
}
#endif

#endif	/* __INCvmechip2h */