vmechip2.h

IXP425的BSP代码

#define	ICR_DLBE		(1 << 6)   /* DMAC received a TEA	 6 */
#define	ICR_DLPE		(1 << 5)   /* DMAC -TEA + Parity Error	 5 */
#define	ICR_DLOB		(1 << 4)   /* DMAC -TEA + Off Board	 4 */
#define	ICR_DLTO		(1 << 3)   /* DMAC -TEA + Locl Time Out	 3 */
#define	ICR_TBL			(1 << 2)   /* DMAC error reading command 2 */
#define	ICR_VME			(1 << 1)   /* DMAC got VMEbus BERR	 1 */
#define	ICR_DONE		1	   /* DMAC finished		 0 */

/*
 * VMEbus Arbiter Timeout Control Register		0x4c	31-24
 * DMAC Ton/Toff Timers and VMEbus Global Timeout	0x4c	23-16
 * VME Access, Local Bus and Watchdog Timeout		0x4c	15-08
 * Prescaler Control Register				0x4c	07-00
 */

#define	TIMEOUTCR_ARBTO		(1 << 24)  /* Enable Grant Timeout	24 */
#define	TIMEOUTCR_OFF_0US	0x00	   /* DMAC off VMEbus for 0us	23-21 */
#define	TIMEOUTCR_OFF_16US	(1 << 21)  /*			16us	23-21 */
#define	TIMEOUTCR_OFF_32US	(2 << 21)  /*			32us	23-21 */
#define	TIMEOUTCR_OFF_64US	(3 << 21)  /*			64us	23-21 */
#define	TIMEOUTCR_OFF_128US	(4 << 21)  /*			128us	23-21 */
#define	TIMEOUTCR_OFF_256US	(5 << 21)  /*			256us	23-21 */
#define	TIMEOUTCR_OFF_512US	(6 << 21)  /*			512us	23-21 */
#define	TIMEOUTCR_OFF_1024US	(7 << 21)  /*			1024us	23-21 */
#define	TIMEOUTCR_ON_16US	0x00	   /* DMAC on VMEbus for 16us	20-18 */
#define	TIMEOUTCR_ON_32US	(1 << 18)  /*			32us	20-18 */
#define	TIMEOUTCR_ON_64US	(2 << 18)  /*			64us	20-18 */
#define	TIMEOUTCR_ON_128US	(3 << 18)  /*			128us	20-18 */
#define	TIMEOUTCR_ON_256US	(4 << 18)  /*			256us	20-18 */
#define	TIMEOUTCR_ON_512US	(5 << 18)  /*			512us	20-18 */
#define	TIMEOUTCR_ON_1024US	(6 << 18)  /*			1024us	20-18 */
#define	TIMEOUTCR_ON_DONE	(7 << 18)  /* DMAC on VMEbus until done	20-18 */
#define	TIMEOUTCR_VGTO_8US	0x00	   /* VMEbus global timeout 8us	17-16 */
#define	TIMEOUTCR_VGTO_64US	(1 << 16)  /*			 16us	17-16 */
#define	TIMEOUTCR_VGTO_256US	(2 << 16)  /*			256us	17-16 */
#define	TIMEOUTCR_VGTO_DISABLE	(3 << 16)  /* global timeout disabled	17-16 */
#define	TIMEOUTCR_VATO_64US	0x00	   /* VMEbus timeout    64us	15-14 */
#define	TIMEOUTCR_VATO_1MS	(1 << 14)  /*			 1ms	15-14 */
#define	TIMEOUTCR_VATO_32MS	(2 << 14)  /*			32ms	15-14 */
#define	TIMEOUTCR_VATO_DISABLE	(3 << 14)  /* access timeout disabled	15-14 */
#define	TIMEOUTCR_LBTO_8US	0x00	   /* Local Bus Timeout	8us	13-12 */
#define	TIMEOUTCR_LBTO_64US	(1 << 12)  /*			64us	13-12 */
#define	TIMEOUTCR_LBTO_256US	(2 << 12)  /*			256us	13-12 */
#define	TIMEOUTCR_LBTO_DISABLE	(3 << 12)  /* Local Timeout Disabled	13-12 */
#define	TIMEOUTCR_WDTO_512US	0x00	   /* Watchdog Timeout	512us	11-08 */
#define	TIMEOUTCR_WDTO_1MS	(1 << 8)   /* Watchdog Timeout	1ms	11-08 */
#define	TIMEOUTCR_WDTO_2MS	(2 << 8)   /* Watchdog Timeout	2ms	11-08 */
#define	TIMEOUTCR_WDTO_4MS	(3 << 8)   /* Watchdog Timeout	4ms	11-08 */
#define	TIMEOUTCR_WDTO_8MS	(4 << 8)   /* Watchdog Timeout	8ms	11-08 */
#define	TIMEOUTCR_WDTO_16MS	(5 << 8)   /* Watchdog Timeout	16ms	11-08 */
#define	TIMEOUTCR_WDTO_32MS	(6 << 8)   /* Watchdog Timeout	32ms	11-08 */
#define	TIMEOUTCR_WDTO_64MS	(7 << 8)   /* Watchdog Timeout	64ms	11-08 */
#define	TIMEOUTCR_WDTO_128MS	(8 << 8)   /* Watchdog Timeout	128ms	11-08 */
#define	TIMEOUTCR_WDTO_256MS	(9 << 8)   /* Watchdog Timeout	256ms	11-08 */
#define	TIMEOUTCR_WDTO_512MS	(10 << 8)  /* Watchdog Timeout	512ms	11-08 */
#define	TIMEOUTCR_WDTO_1S	(11 << 8)  /* Watchdog Timeout	1s	11-08 */
#define	TIMEOUTCR_WDTO_4S	(12 << 8)  /* Watchdog Timeout	4s	11-08 */
#define	TIMEOUTCR_WDTO_16S	(13 << 8)  /* Watchdog Timeout	16s	11-08 */
#define	TIMEOUTCR_WDTO_32S	(14 << 8)  /* Watchdog Timeout	32s	11-08 */
#define	TIMEOUTCR_WDTO_64S	(15 << 8)  /* Watchdog Timeout	64s	11-08 */

/*
 * Board Control Register				0x60	31-24
 * Watchdog Timer Control Register			0x60	23-16
 * Tick Timer 2 Control Register			0x60	15-08
 * Tick Timer 1 Control Register			0x60	07-00
 */

#define	TIMERCR_SCON		(1 << 30)  /* Board is System Cont	30 */
#define	TIMERCR_SFFL		(1 << 29)  /* VMEbus SYSFAIL is assertd	29 */
#define	TIMERCR_BRFLI		(1 << 28)  /* Board Fail is asserted	28 */
#define	TIMERCR_PURS		(1 << 27)  /* Power-Up Reset		27 */
#define	TIMERCR_CPURS		(1 << 26)  /* Clear Power-Up Reset	26 */
#define	TIMERCR_BDFLO		(1 << 25)  /* Assert the BRDFAIL Signal	25 */
#define	TIMERCR_RSWE		(1 << 24)  /* Enable Reset Switch	24 */
#define	TIMERCR_RSWD		0x00	   /* Disable Reset Switch	24 */
#define	TIMERCR_SRST		(1 << 23)  /* Assert SYSRESET on VMEbus	23 */
#define	TIMERCR_WDCS		(1 << 22)  /* Clear watchdog timeout	22 */
#define	TIMERCR_WDCC		(1 << 21)  /* Reset watchdog counter	21 */
#define	TIMERCR_WDTO		(1 << 20)  /* Watchdog Timeout occurd	20 */
#define	TIMERCR_WDBFE		(1 << 19)  /* Set Board Fail on WD TO	19 */
#define	TIMERCR_WDSYSRESET	(1 << 18)  /* Set SYSRESET on WD TO	18 */
#define	TIMERCR_WDLRESET	0x00	   /* Set LRESET on WD TO	18 */
#define	TIMERCR_WDRSE		(1 << 17)  /* RESET on Watchdog Timeout	17 */
#define	TIMERCR_WDEN		(1 << 16)  /* Enable Watchdog Timeout	16 */
#define	TIMERCR_WDDIS		0x00	   /* Disable Watchdog Timeout	16 */
#define	TIMERCR_TT2_COVF	(1 << 10)  /* Clear Over Flow Counter	10 */
#define	TIMERCR_TT2_COC		(1 << 9)   /* Clear On Compare		 9 */
#define	TIMERCR_TT2_EN		(1 << 8)   /* Enable Counter		 8 */
#define	TIMERCR_TT1_COVF	(1 << 2)   /* Clear Over Flow Counter	 2 */
#define	TIMERCR_TT1_COC		(1 << 1)   /* Clear On Compare		 1 */
#define	TIMERCR_TT1_EN		1	   /* Enable Counter		 0 */

/* Local Bus Interrupter Status Register		0x68	31-00	*/

#define	LBISR_ACF		(1 << 31)  /* VMEbus ACFAIL Interrupt	31 */
#define	LBISR_AB		(1 << 30)  /* ABORT Switch Interrupt	30 */
#define	LBISR_SYSF		(1 << 29)  /* VMEbus SYSFAIL Interrupt	29 */
#define	LBISR_MWP		(1 << 28)  /* VMEbus master write post	28 */
#define	LBISR_PE		(1 << 27)  /* External Inter (parity)	27 */
#define	LBISR_VI1E		(1 << 26)  /* VMEbus IRQ1 edge Intr	26 */
#define	LBISR_TIC2		(1 << 25)  /* Tick Timer 2 Interrupt	25 */
#define	LBISR_TIC1		(1 << 24)  /* Tick Timer 1 Interrupt	24 */
#define	LBISR_VIA		(1 << 23)  /* VMEbus Inter Ack Inter	23 */
#define	LBISR_DMA		(1 << 22)  /* DMAC Interrupt		22 */
#define	LBISR_SIG3		(1 << 21)  /* GCSR SIG3 interrupt	21 */
#define	LBISR_SIG2		(1 << 20)  /* GCSR SIG2 interrupt	20 */
#define	LBISR_SIG1		(1 << 19)  /* GCSR SIG1 interrupt	19 */
#define	LBISR_SIG0		(1 << 18)  /* GCSR SIG0 interrupt	18 */
#define	LBISR_LM1		(1 << 17)  /* GCSR LM1 interrupt	17 */
#define	LBISR_LM0		(1 << 16)  /* GCSR LM0 interrupt	16 */
#define	LBISR_SW7		(1 << 15)  /* Software 7 interrupt	15 */
#define	LBISR_SW6		(1 << 14)  /* Software 6 interrupt	14 */
#define	LBISR_SW5		(1 << 13)  /* Software 5 interrupt	13 */
#define	LBISR_SW4		(1 << 12)  /* Software 4 interrupt	12 */
#define	LBISR_SW3		(1 << 11)  /* Software 3 interrupt	11 */
#define	LBISR_SW2		(1 << 10)  /* Software 2 interrupt	10 */
#define	LBISR_SW1		(1 << 9)   /* Software 1 interrupt	 9 */
#define	LBISR_SW0		(1 << 8)   /* Software 0 interrupt	 8 */
#define	LBISR_VME7		(1 << 6)   /* VMEbus IRQ7 interrupt	 6 */
#define	LBISR_VME6		(1 << 5)   /* VMEbus IRQ6 interrupt	 5 */
#define	LBISR_VME5		(1 << 4)   /* VMEbus IRQ5 interrupt	 4 */
#define	LBISR_VME4		(1 << 3)   /* VMEbus IRQ4 interrupt	 3 */
#define	LBISR_VME3		(1 << 2)   /* VMEbus IRQ3 interrupt	 2 */
#define	LBISR_VME2		(1 << 1)   /* VMEbus IRQ2 interrupt	 1 */
#define	LBISR_VME1		1	   /* VMEbus IRQ1 interrupt	 0 */

/* Local Bus Interrupter Enable Register		0x6c	31-00	*/

#define	LBIER_EACF		(1 << 31)  /* Enable VMEbus ACFAIL IRQ	31 */
#define	LBIER_EAB		(1 << 30)  /* Enable ABORT switch IRQ	30 */
#define	LBIER_ESYSF		(1 << 29)  /* Enable VMEbus SYSFAIL IRQ	29 */
#define	LBIER_EMWP		(1 << 28)  /* Enable VMEbus WPE IRQ	28 */
#define	LBIER_EPE		(1 << 27)  /* Enable Parity Error IRQ	27 */
#define	LBIER_EVI1E		(1 << 26)  /* Enable VMEbus IRQ1 IRQ	26 */
#define	LBIER_ETIC2		(1 << 25)  /* Enable Tick Timer 2 IRQ	25 */
#define	LBIER_ETIC1		(1 << 24)  /* Enable Tick Timer 1 IRQ	24 */

#define	LBIER_EVIA		(1 << 23)  /* Enable VME Intptr Ack IRQ	23 */
#define	LBIER_EDMA		(1 << 22)  /* Enable DMAC IRQ		22 */
#define	LBIER_ESIG3		(1 << 21)  /* Enable GCSR SIG3 IRQ	21 */
#define	LBIER_ESIG2		(1 << 20)  /* Enable GCSR SIG2 IRQ	20 */
#define	LBIER_ESIG1		(1 << 19)  /* Enable GCSR SIG1 IRQ	19 */
#define	LBIER_ESIG0		(1 << 18)  /* Enable GCSR SIG0 IRQ	18 */
#define	LBIER_ELM1		(1 << 17)  /* Enable GCSR LM1 IRQ	17 */
#define	LBIER_ELM0		(1 << 16)  /* Enable GCSR LM0 IRQ	16 */

#define	LBIER_ESW7		(1 << 15)  /* Enable Software 7 Inter	15 */
#define	LBIER_ESW6		(1 << 14)  /* Enable Software 6 Inter	14 */
#define	LBIER_ESW5		(1 << 13)  /* Enable Software 5 Inter	13 */
#define	LBIER_ESW4		(1 << 12)  /* Enable Software 4 Inter	12 */
#define	LBIER_ESW3		(1 << 11)  /* Enable Software 3 Inter	11 */
#define	LBIER_ESW2		(1 << 10)  /* Enable Software 2 Inter	10 */
#define	LBIER_ESW1		(1 << 9)   /* Enable Software 1 Inter	 9 */
#define	LBIER_ESW0		(1 << 8)   /* Enable Software 0 Inter	 8 */

#define	LBIER_EIRQ7		(1 << 6)   /* Enable VMEbus IRQ7 Inter	 6 */
#define	LBIER_EIRQ6		(1 << 5)   /* Enable VMEbus IRQ6 Inter	 5 */
#define	LBIER_EIRQ5		(1 << 4)   /* Enable VMEbus IRQ5 Inter	 4 */
#define	LBIER_EIRQ4		(1 << 3)   /* Enable VMEbus IRQ4 Inter	 3 */
#define	LBIER_EIRQ3		(1 << 2)   /* Enable VMEbus IRQ3 Inter	 2 */
#define	LBIER_EIRQ2		(1 << 1)   /* Enable VMEbus IRQ2 Inter	 1 */
#define	LBIER_EIRQ1		1	   /* Enable VMEbus IRQ1 Inter	 0 */

/* Software Interrupt Set Register			0x70	15-08	*/

#define	SISR_SSW7		(1 << 15)  /* Set Software 7 Interrupt	15 */
#define	SISR_SSW6		(1 << 14)  /* Set Software 6 Interrupt	14 */
#define	SISR_SSW5		(1 << 13)  /* Set Software 5 Interrupt	13 */
#define	SISR_SSW4		(1 << 12)  /* Set Software 4 Interrupt	12 */
#define	SISR_SSW3		(1 << 11)  /* Set Software 3 Interrupt	11 */
#define	SISR_SSW2		(1 << 10)  /* Set Software 2 Interrupt	10 */
#define	SISR_SSW1		(1 << 9)   /* Set Software 1 Interrupt	 9 */
#define	SISR_SSW0		(1 << 8)   /* Set Software 0 Interrupt	 8 */

/* Interrupt Clear Register				0x74	31-08	*/

#define	ICLR_CACF		(1 << 31)  /* Clr VMEbus ACFAIL Inter	31 */
#define	ICLR_CAB		(1 << 30)  /* Clr ABORT Switch Inter	30 */
#define	ICLR_CSYSF		(1 << 29)  /* Clr VMEbus SYSFAIL Inter	29 */
#define	ICLR_CMWP		(1 << 28)  /* Clr VME Master Write Post	28 */
#define	ICLR_CPE		(1 << 27)  /* Clr Ext Inter (PARITY)	27 */
#define	ICLR_CVI1E		(1 << 26)  /* Clr VME IRQ1 Edge Inter	26 */
#define	ICLR_CTIC2		(1 << 25)  /* Clr Tick Timer 2 Inter	25 */
#define	ICLR_CTIC1		(1 << 24)  /* Clr Tick Timer 1 Inter	24 */

#define	ICLR_CVIA		(1 << 23)  /* Clr VMEbus Interrupt Ack	23 */
#define	ICLR_CDMA		(1 << 22)  /* Clr DMA Controller Inter	22 */
#define	ICLR_CSIG3		(1 << 21)  /* Clr GCSR SIG3 Interrupt	21 */
#define	ICLR_CSIG2		(1 << 20)  /* Clr GCSR SIG2 Interrupt	20 */
#define	ICLR_CSIG1		(1 << 19)  /* Clr GCSR SIG1 Interrupt	19 */
#define	ICLR_CSIG0		(1 << 18)  /* Clr GCSR SIG0 Interrupt	18 */
#define	ICLR_CLM1		(1 << 17)  /* Clr GCSR LM1 Interrupt	17 */
#define	ICLR_CLM0		(1 << 16)  /* Clr GCSR LM0 Interrupt	16 */

#define	ICLR_CSW7		(1 << 15)  /* Clr Software 7 Interrupt	15 */
#define	ICLR_CSW6		(1 << 14)  /* Clr Software 6 Interrupt	14 */
#define	ICLR_CSW5		(1 << 13)  /* Clr Software 5 Interrupt	13 */
#define	ICLR_CSW4		(1 << 12)  /* Clr Software 4 Interrupt	12 */
#define	ICLR_CSW3		(1 << 11)  /* Clr Software 3 Interrupt	11 */
#define	ICLR_CSW2		(1 << 10)  /* Clr Software 2 Interrupt	10 */
#define	ICLR_CSW1		(1 << 9)   /* Clr Software 1 Interrupt	 9 */
#define	ICLR_CSW0		(1 << 8)   /* Clr Software 0 Interrupt	 8 */

/* Interrupt Level Register 1				0x78	31-00	*/

#define	ILR1_ACF_LEVEL1		(1 << 28)  /* ACFAIL Inter on Level 1	30-28 */
#define	ILR1_ACF_LEVEL2		(2 << 28)  /* ACFAIL Inter on Level 2	30-28 */
#define	ILR1_ACF_LEVEL3		(3 << 28)  /* ACFAIL Inter on Level 3	30-28 */
#define	ILR1_ACF_LEVEL4		(4 << 28)  /* ACFAIL Inter on Level 4	30-28 */
#define	ILR1_ACF_LEVEL5		(5 << 28)  /* ACFAIL Inter on Level 5	30-28 */
#define	ILR1_ACF_LEVEL6		(6 << 28)  /* ACFAIL Inter on Level 6	30-28 */
#define	ILR1_ACF_LEVEL7		(7 << 28)  /* ACFAIL Inter on Level 7	30-28 */

#define ILR1_AB_LEVEL1		(1 << 24)  /* ABORT Inter on Level 1	26-24 */
#define ILR1_AB_LEVEL2		(2 << 24)  /* ABORT Inter on Level 2	26-24 */
#define ILR1_AB_LEVEL3		(3 << 24)  /* ABORT Inter on Level 3	26-24 */
#define ILR1_AB_LEVEL4		(4 << 24)  /* ABORT Inter on Level 4	26-24 */
#define ILR1_AB_LEVEL5		(5 << 24)  /* ABORT Inter on Level 5	26-24 */
#define ILR1_AB_LEVEL6		(6 << 24)  /* ABORT Inter on Level 6	26-24 */
#define ILR1_AB_LEVEL7		(7 << 24)  /* ABORT Inter on Level 7	26-24 */

#define	ILR1_SYSF_LEVEL1	(1 << 20)  /* SYSFAIL Inter on Lvl 1	22-20 */
#define	ILR1_SYSF_LEVEL2	(2 << 20)  /* SYSFAIL Inter on Lvl 2	22-20 */
#define	ILR1_SYSF_LEVEL3	(3 << 20)  /* SYSFAIL Inter on Lvl 3	22-20 */
#define	ILR1_SYSF_LEVEL4	(4 << 20)  /* SYSFAIL Inter on Lvl 4	22-20 */
#define	ILR1_SYSF_LEVEL5	(5 << 20)  /* SYSFAIL Inter on Lvl 5	22-20 */
#define	ILR1_SYSF_LEVEL6	(6 << 20)  /* SYSFAIL Inter on Lvl 6	22-20 */
#define	ILR1_SYSF_LEVEL7	(7 << 20)  /* SYSFAIL Inter on Lvl 7	22-20 */

#define	ILR1_WPE_LEVEL1		(1 << 16)  /* Master Write Post Lvl 1	18-16 */
#define	ILR1_WPE_LEVEL2		(2 << 16)  /* Master Write Post Lvl 2	18-16 */
#define	ILR1_WPE_LEVEL3		(3 << 16)  /* Master Write Post Lvl 3	18-16 */
#define	ILR1_WPE_LEVEL4		(4 << 16)  /* Master Write Post Lvl 4	18-16 */
#define	ILR1_WPE_LEVEL5		(5 << 16)  /* Master Write Post Lvl 5	18-16 */
#define	ILR1_WPE_LEVEL6		(6 << 16)  /* Master Write Post Lvl 6	18-16 */
#define	ILR1_WPE_LEVEL7		(7 << 16)  /* Master Write Post Lvl 7	18-16 */

#define	ILR1_PE_LEVEL1		(1 << 12)  /* Parity Error on Level 1	14-12 */
#define	ILR1_PE_LEVEL2		(2 << 12)  /* Parity Error on Level 2	14-12 */
#define	ILR1_PE_LEVEL3		(3 << 12)  /* Parity Error on Level 3	14-12 */
#define	ILR1_PE_LEVEL4		(4 << 12)  /* Parity Error on Level 4	14-12 */
#define	ILR1_PE_LEVEL5		(5 << 12)  /* Parity Error on Level 5	14-12 */
#define	ILR1_PE_LEVEL6		(6 << 12)  /* Parity Error on Level 6	14-12 */
#define	ILR1_PE_LEVEL7		(7 << 12)  /* Parity Error on Level 7	14-12 */

#define	ILR1_IRQ1E_LEVEL1	(1 << 8)   /* VMEbus IRQ1 edge on Lvl 1	10-8 */
#define	ILR1_IRQ1E_LEVEL2	(2 << 8)   /* VMEbus IRQ1 edge on Lvl 2	10-8 */
#define	ILR1_IRQ1E_LEVEL3	(3 << 8)   /* VMEbus IRQ1 edge on Lvl 3	10-8 */
#define	ILR1_IRQ1E_LEVEL4	(4 << 8)   /* VMEbus IRQ1 edge on Lvl 4	10-8 */
#define	ILR1_IRQ1E_LEVEL5	(5 << 8)   /* VMEbus IRQ1 edge on Lvl 5	10-8 */
#define	ILR1_IRQ1E_LEVEL6	(6 << 8)   /* VMEbus IRQ1 edge on Lvl 6	10-8 */
#define	ILR1_IRQ1E_LEVEL7	(7 << 8)   /* VMEbus IRQ1 edge on Lvl 7	10-8 */

#define	ILR1_TICK2_LEVEL1	(1 << 4)   /* Tick Timer 2 Inter Lvl 1	 6-4 */
#define	ILR1_TICK2_LEVEL2	(2 << 4)   /* Tick Timer 2 Inter Lvl 2	 6-4 */
#define	ILR1_TICK2_LEVEL3	(3 << 4)   /* Tick Timer 2 Inter Lvl 3	 6-4 */
#define	ILR1_TICK2_LEVEL4	(4 << 4)   /* Tick Timer 2 Inter Lvl 4	 6-4 */
#define	ILR1_TICK2_LEVEL5	(5 << 4)   /* Tick Timer 2 Inter Lvl 5	 6-4 */
#define	ILR1_TICK2_LEVEL6	(6 << 4)   /* Tick Timer 2 Inter Lvl 6	 6-4 */
#define	ILR1_TICK2_LEVEL7	(7 << 4)   /* Tick Timer 2 Inter Lvl 7	 6-4 */

#define	ILR1_TICK1_LEVEL1	1	   /* Tick Timer 1 Inter Lvl 1	 6-4 */
#define	ILR1_TICK1_LEVEL2	2	   /* Tick Timer 1 Inter Lvl 2	 6-4 */
#define	ILR1_TICK1_LEVEL3	3	   /* Tick Timer 1 Inter Lvl 3	 6-4 */
#define	ILR1_TICK1_LEVEL4	4	   /* Tick Timer 1 Inter Lvl 4	 6-4 */
#define	ILR1_TICK1_LEVEL5	5	   /* Tick Timer 1 Inter Lvl 5	 6-4 */
#define	ILR1_TICK1_LEVEL6	6	   /* Tick Timer 1 Inter Lvl 6	 6-4 */
#define	ILR1_TICK1_LEVEL7	7	   /* Tick Timer 1 Inter Lvl 7	 6-4 */

/* Interrupt Level Register 2				0x7c	31-00	*/

#define	ILR2_VIA_LEVEL1		(1 << 28)  /* VMEbus Intrptr Ack Lvl 1	30-28 */
#define	ILR2_VIA_LEVEL2		(2 << 28)  /* VMEbus Intrptr Ack Lvl 2	30-28 */
#define	ILR2_VIA_LEVEL3		(3 << 28)  /* VMEbus Intrptr Ack Lvl 3	30-28 */
#define	ILR2_VIA_LEVEL4		(4 << 28)  /* VMEbus Intrptr Ack Lvl 4	30-28 */
#define	ILR2_VIA_LEVEL5		(5 << 28)  /* VMEbus Intrptr Ack Lvl 5	30-28 */
#define	ILR2_VIA_LEVEL6		(6 << 28)  /* VMEbus Intrptr Ack Lvl 6	30-28 */
#define	ILR2_VIA_LEVEL7		(7 << 28)  /* VMEbus Intrptr Ack Lvl 7	30-28 */

#define	ILR2_DMA_LEVEL1		(1 << 24)  /* DMA Controller Int Lvl 1	26-24 */
#define	ILR2_DMA_LEVEL2		(2 << 24)  /* DMA Controller Int Lvl 2	26-24 */
#define	ILR2_DMA_LEVEL3		(3 << 24)  /* DMA Controller Int Lvl 3	26-24 */
#define	ILR2_DMA_LEVEL4		(4 << 24)  /* DMA Controller Int Lvl 4	26-24 */
#define	ILR2_DMA_LEVEL5		(5 << 24)  /* DMA Controller Int Lvl 5	26-24 */
#define	ILR2_DMA_LEVEL6		(6 << 24)  /* DMA Controller Int Lvl 6	26-24 */