vmechip2.h

IXP425的BSP代码

#define	VC2GCSR_GPR4H		VC2GCSR_ADRS(0x1a)  /* General Purpose Reg 4 */
#define	VC2GCSR_GPR4L		VC2GCSR_ADRS(0x1b)  /* General Purpose Reg 4 */
#define	VC2GCSR_GPR5H		VC2GCSR_ADRS(0x1e)  /* General Purpose Reg 5 */
#define	VC2GCSR_GPR5L		VC2GCSR_ADRS(0x1f)  /* General Purpose Reg 5 */

#define	VC2BUS_REVISION		VC2BUS_ADRS(0x00)  /* Revision Reg */
#define	VC2BUS_ID		VC2BUS_ADRS(0x01)  /* ID Reg */
#define	VC2BUS_LM_SIG		VC2BUS_ADRS(0x02)  /* LM/SIG Reg */
#define	VC2BUS_BSCR		VC2BUS_ADRS(0x03)  /* Board Stat/Cont Reg */
#define VC2BUS_GPR0H		VC2BUS_ADRS(0x04)  /* General Purpose Reg 0 */
#define	VC2BUS_GPR0L		VC2BUS_ADRS(0x05)  /* General Purpose Reg 0 */
#define	VC2BUS_GPR1H		VC2BUS_ADRS(0x06)  /* General Purpose Reg 1 */
#define	VC2BUS_GPR1L		VC2BUS_ADRS(0x07)  /* General Purpose Reg 1 */
#define	VC2BUS_GPR2H		VC2BUS_ADRS(0x08)  /* General Purpose Reg 2 */
#define	VC2BUS_GPR2L		VC2BUS_ADRS(0x09)  /* General Purpose Reg 2 */
#define	VC2BUS_GPR3H		VC2BUS_ADRS(0x0a)  /* General Purpose Reg 3 */
#define	VC2BUS_GPR3L		VC2BUS_ADRS(0x0b)  /* General Purpose Reg 3 */
#define	VC2BUS_GPR4H		VC2BUS_ADRS(0x0c)  /* General Purpose Reg 4 */
#define	VC2BUS_GPR4L		VC2BUS_ADRS(0x0d)  /* General Purpose Reg 4 */
#define	VC2BUS_GPR5H		VC2BUS_ADRS(0x0e)  /* General Purpose Reg 5 */
#define	VC2BUS_GPR5L		VC2BUS_ADRS(0x0f)  /* General Purpose Reg 5 */

/* NOW LET'S DEFINE THE BITS FOR THESE REGISTERS */

/*
 * VMEbus Slave Write Post and Snoop Control Reg 2	0x10	31-24
 * VMEbus Slave Address Modifier Select Reg 2		0x10	23-16
 * VMEbus Slave Write Post and Snoop Control Reg 1	0x10	15-08
 * VMEbus Slave Address Modifier Select Reg 1		0x10	07-00
 */
#define	VSAMSR2_SNP_INHIBIT	0x00	   /* Snoop Inhibited		26-25 */
#define	VSAMSR2_SNP_WSD		(1 << 25)  /* Write-Sink Data		26-25 */
#define	VSAMSR2_SNP_WI		(2 << 25)  /* Write-Invalidate		26-25 */
#define	VSAMSR2_WP		(1 << 24)  /* Write Posting Enabled	24 */
#define	VSAMSR2_SUP		(1 << 23)  /* 2nd map to supervi	23 */
#define	VSAMSR2_USR		(1 << 22)  /* 2nd map to user 		22 */
#define	VSAMSR2_A32		(1 << 21)  /* 2nd map to extend access	21 */
#define	VSAMSR2_A24		(1 << 20)  /* 2nd map to stanard access	20 */
#define	VSAMSR2_D64		(1 << 19)  /* 2nd map to D64 block acc  19 */
#define	VSAMSR2_BLK		(1 << 18)  /* 2nd map to block access	18 */
#define	VSAMSR2_PGM		(1 << 17)  /* 2nd map to program access	17 */
#define	VSAMSR2_DAT		(1 << 16)  /* 2nd map to data access	16 */
#define	VSAMSR1_SNP_INHIBIT	0x00	   /* Snoop Inhibited		10-9 */
#define	VSAMSR1_SNP_WSD		(1 << 9)   /* Write-Sink Data		10-9 */
#define	VSAMSR1_SNP_WI		(2 << 9)   /* Write-Invalidate		10-9 */
#define	VSAMSR1_WP		(1 << 8)   /* Write Posting Enabled	 8 */
#define	VSAMSR1_SUP		(1 << 7)   /* 1st map to supervi	 7 */
#define	VSAMSR1_USR		(1 << 6)   /* 1st map to user	 	 6 */
#define	VSAMSR1_A32		(1 << 5)   /* 1st map to extended access 5 */
#define	VSAMSR1_A24		(1 << 4)   /* 1st map to standard access 4 */
#define	VSAMSR1_D64		(1 << 3)   /* 1st map to D64 block acces 3 */
#define	VSAMSR1_BLK		(1 << 2)   /* 1st map to block access	 2 */
#define	VSAMSR1_PGM		(1 << 1)   /* 1st map to program access	 1 */
#define	VSAMSR1_DAT		0x01	   /* 1st map to data access	 0 */

/*
 * Local Bus Slave Attribute Register 4			0x28	31-24
 * Local Bus Slave Attribute Register 3			0x28	23-16
 * Local Bus Slave Attribute Register 2			0x28	15-08
 * Local Bus Slave Attribute Register 1			0x28	07-00
 */
#define	LBSAR4_D16		(1 << 31)  /* D16 data transfers	31 */
#define	LBSAR4_D32		0x00	   /* D32 data transfers	31 */
#define	LBSAR4_WP_ENABLE	(1 << 30)  /* Write posting enabled	30 */
#define	LBSAR4_WP_DISABLE	0x00 	   /* Write posting disabled	30 */
/*	The following are for the Address Modifier equates		29-24 */
#define	LBSAR4_AM_STD_SUP_ASCENDING	VME_AM_STD_SUP_ASCENDING << 24
#define	LBSAR4_AM_STD_SUP_PGM		VME_AM_STD_SUP_PGM << 24
#define	LBSAR4_AM_STD_SUP_DATA		VME_AM_STD_SUP_DATA << 24
#define	LBSAR4_AM_STD_USR_ASCENDING	VME_AM_STD_USR_ASCENDING << 24
#define LBSAR4_AM_STD_USR_PGM		VME_AM_STD_USR_PGM << 24
#define	LBSAR4_AM_STD_USR_DATA		VME_AM_STD_USR_DATA << 24
#define	LBSAR4_AM_SUP_SHORT_IO		VME_AM_SUP_SHORT_IO << 24
#define	LBSAR4_AM_USR_SHORT_IO		VME_AM_USR_SHORT_IO << 24
#define	LBSAR4_AM_EXT_SUP_ASCENDING	VME_AM_EXT_SUP_ASCENDING << 24
#define	LBSAR4_AM_EXT_SUP_PGM		VME_AM_EXT_SUP_PGM << 24
#define	LBSAR4_AM_EXT_SUP_DATA		VME_AM_EXT_SUP_DATA << 24
#define	LBSAR4_AM_EXT_USR_ASCENDING	VME_AM_EXT_USR_ASCENDING << 24
#define	LBSAR4_AM_EXT_USR_PGM		VME_AM_EXT_USR_PGM << 24
#define	LBSAR4_AM_EXT_USR_DATA		VME_AM_EXT_USR_DATA << 24

#define	LBSAR3_D16		(1 << 23)  /* D16 data transfers	23 */
#define	LBSAR3_D32		0x00	   /* D32 data transfers	23 */
#define	LBSAR3_WP_ENABLE	(1 << 22)  /* Write posting enabled	22 */
#define	LBSAR3_WP_DISABLE	0x00	   /* Write posting disabled	22 */
/*	The following are for the Address Modifier equates		21-16 */
#define	LBSAR3_AM_STD_SUP_ASCENDING	VME_AM_STD_SUP_ASCENDING << 16
#define	LBSAR3_AM_STD_SUP_PGM		VME_AM_STD_SUP_PGM << 16
#define	LBSAR3_AM_STD_SUP_DATA		VME_AM_STD_SUP_DATA << 16
#define	LBSAR3_AM_STD_USR_ASCENDING	VME_AM_STD_USR_ASCENDING << 16
#define	LBSAR3_AM_STD_USR_PGM		VME_AM_STD_USR_PGM << 16
#define	LBSAR3_AM_STD_USR_DATA		VME_AM_STD_USR_DATA << 16
#define	LBSAR3_AM_SUP_SHORT_IO		VME_AM_SUP_SHORT_IO << 16
#define	LBSAR3_AM_USR_SHORT_IO		VME_AM_USR_SHORT_IO << 16
#define LBSAR3_AM_EXT_SUP_ASCENDING	VME_AM_EXT_SUP_ASCENDING << 16
#define	LBSAR3_AM_EXT_SUP_PGM		VME_AM_EXT_SUP_PGM << 16
#define	LBSAR3_AM_EXT_SUP_DATA		VME_AM_EXT_SUP_DATA << 16
#define	LBSAR3_AM_EXT_USR_ASCENDING	VME_AM_EXT_USR_ASCENDING << 16
#define	LBSAR3_AM_EXT_USR_PGM		VME_AM_EXT_USR_PGM << 16
#define LBSAR3_AM_EXT_USR_DATA		VME_AM_EXT_USR_DATA << 16

#define	LBSAR2_D16		(1 << 15)  /* D16 data transfers	15 */
#define	LBSAR2_D32		0x00	   /* D32 data transfers	15 */
#define	LBSAR2_WP_ENABLE	(1 << 14)  /* Write posting enabled	14 */
#define	LBSAR2_WP_DISABLE	0x00	   /* Write posting disabled	14 */
/*	The following are for the Address Modifier equates		13-8 */
#define	LBSAR2_AM_STD_SUP_ASCENDING	VME_AM_STD_SUP_ASCENDING << 8
#define	LBSAR2_AM_STD_SUP_PGM		VME_AM_STD_SUP_PGM << 8
#define	LBSAR2_AM_STD_SUP_DATA		VME_AM_STD_SUP_DATA << 8
#define	LBSAR2_AM_STD_USR_ASCENDING	VME_AM_STD_USR_ASCENDING << 8
#define	LBSAR2_AM_STD_USR_PGM		VME_AM_STD_USR_PGM << 8
#define	LBSAR2_AM_STD_USR_DATA		VME_AM_STD_USR_DATA << 8
#define	LBSAR2_AM_SUP_SHORT_IO		VME_AM_SUP_SHORT_IO << 8
#define	LBSAR2_AM_USR_SHORT_IO		VME_AM_USR_SHORT_IO << 8
#define	LBSAR2_AM_EXT_SUP_ASCENDING	VME_AM_EXT_SUP_ASCENDING << 8
#define	LBSAR2_AM_EXT_SUP_PGM		VME_AM_EXT_SUP_PGM << 8
#define	LBSAR2_AM_EXT_SUP_DATA		VME_AM_EXT_SUP_DATA << 8
#define	LBSAR2_AM_EXT_USR_ASCENDING	VME_AM_EXT_USR_ASCENDING << 8
#define	LBSAR2_AM_EXT_USR_PGM		VME_AM_EXT_USR_PGM << 8
#define	LBSAR2_AM_EXT_USR_DATA		VME_AM_EXT_USR_DATA << 8

#define	LBSAR1_D16		(1 << 7)  /* D16 data transfers		 7 */
#define	LBSAR1_D32		0x00	  /* D32 data transfers		 7 */
#define	LBSAR1_WP_ENABLE	(1 << 6)  /* Write posting enabled	 6 */
#define	LBSAR1_WP_DISABLE	0x00	  /* Write posting disabled	 6 */
/*	The following are for the Address Modifier equates		 5-0 */
#define	LBSAR1_AM_STD_SUP_ASCENDING	VME_AM_STD_SUP_ASCENDING
#define	LBSAR1_AM_STD_SUP_PGM		VME_AM_STD_SUP_PGM
#define	LBSAR1_AM_STD_SUP_DATA		VME_AM_STD_SUP_DATA
#define	LBSAR1_AM_STD_USR_ASCENDING	VME_AM_STD_USR_ASCENDING
#define	LBSAR1_AM_STD_USR_PGM		VME_AM_STD_USR_PGM
#define	LBSAR1_AM_STD_USR_DATA		VME_AM_STD_USR_DATA
#define	LBSAR1_AM_SUP_SHORT_IO		VME_AM_SUP_SHORT_IO
#define	LBSAR1_AM_USR_SHORT_IO		VME_AM_USR_SHORT_IO
#define	LBSAR1_AM_EXT_SUP_ASCENDING	VME_AM_EXT_SUP_ASCENDING
#define	LBSAR1_AM_EXT_SUP_PGM		VME_AM_EXT_SUP_PGM
#define	LBSAR1_AM_EXT_SUP_DATA		VME_AM_EXT_SUP_DATA
#define	LBSAR1_AM_EXT_USR_ASCENDING	VME_AM_EXT_USR_ASCENDING
#define	LBSAR1_AM_EXT_USR_PGM		VME_AM_EXT_USR_PGM
#define	LBSAR1_AM_EXT_USR_DATA		VME_AM_EXT_USR_DATA

/*
 * VMEbus Slave GCSR Group Address Reg			0x2c	31-24
 * VMEbus Slave GCSR Board Address Reg			0x2c	23-20
 * Local Bus To VMEbus Enable Control Reg		0x2c	19-16
 * Local Bus to VMEbus I/O Control Reg			0x2c	15-08
 * ROM Control Reg					0x2c	07-00
 */

#define	LBTVCR_EN4		(1 << 19)  /* 4th VMEbus decoder enable	19 */
#define	LBTVCR_EN3		(1 << 18)  /* 3rd VMEbus decoder enable	18 */
#define	LBTVCR_EN2		(1 << 17)  /* 2nd VMEbus decoder enable	17 */
#define	LBTVCR_EN1		(1 << 16)  /* 1st VMEbus decoder enable	16 */
#define	LBTVCR_I2EN		(1 << 15)  /* Enable F page decoder	15 */
#define	LBTVCR_I2WP		(1 << 14)  /* Page F Write Post Enable	14 */
#define	LBTVCR_I2SUP		(1 << 13)  /* Supervisor AM for Page F	13 */
#define	LBTVCR_I2USR		0x00	   /* User AM for Page F	13 */
#define	LBTVCR_I2PROG		(1 << 12)  /* Program AM for Page F	12 */
#define	LBTVCR_I2DATA		0x00	   /* Data AM for Page F	12 */
#define	LBTVCR_I1EN		(1 << 11)  /* Short I/O Enabled		11 */
#define	LBTVCR_I1D16		(1 << 10)  /* D16 data for Short I/O	10 */
#define	LBTVCR_I1D32		0x00	   /* D32 data for Short I/O	10 */
#define	LBTVCR_I1WP		(1 << 9)   /* Write Post for Short I/O	 9 */
#define	LBTVCR_I1SUP		(1 << 8)   /* Supvisor AM for Short I/O	 8 */
#define	LBTVCR_I1USR		0x00	   /* User AM for Short I/O	 8 */
#define	LBTVCR_8MBIT		0x00	   /* 8 MBit Chips		 7-6 */
#define	LBTVCR_4MBIT		(1 << 6)   /* 4 MBit Chips		 7-6 */
#define	LBTVCR_2MBIT		(2 << 6)   /* 2 MBit Chips		 7-6 */
#define	LBTVCR_1MBIT		(3 << 6)   /* 1 MBit Chips		 7-6 */

/* B ROMs SPEED DEFINED FOR 25MHz BUS CLOCK */
#define	LBTVCR_B365NS		0x00	   /* 365 ns B EPROM Access	 5-3 */
#define	LBTVCR_B325NS		(1 << 3)   /* 325 ns B EPROM Access 	 5-3 */
#define	LBTVCR_B285NS		(2 << 3)   /* 285 ns B EPROM Access 	 5-3 */
#define	LBTVCR_B245NS		(3 << 3)   /* 245 ns B EPROM Access 	 5-3 */
#define	LBTVCR_B205NS		(4 << 3)   /* 205 ns B EPROM Access 	 5-3 */
#define	LBTVCR_B165NS		(5 << 3)   /* 165 ns B EPROM Access 	 5-3 */
#define	LBTVCR_B125NS		(6 << 3)   /* 125 ns B EPROM Access 	 5-3 */
#define	LBTVCR_B85NS		(7 << 3)   /* 85 ns B EPROM Access 	 5-3 */

/* A ROMs SPEED DEFINED FOR 25MHz BUS CLOCK */
#define	LBTVCR_A365NS		0x00	   /* 365 ns A EPROM Access 	 2-0 */
#define	LBTVCR_A325NS		0x01	   /* 325 ns A EPROM Access 	 2-0 */
#define	LBTVCR_A285NS		0x02	   /* 285 ns A EPROM Access 	 2-0 */
#define	LBTVCR_A245NS		0x03	   /* 245 ns A EPROM Access 	 2-0 */
#define	LBTVCR_A205NS		0x04	   /* 205 ns A EPROM Access 	 2-0 */
#define	LBTVCR_A165NS		0x05	   /* 165 ns A EPROM Access 	 2-0 */
#define	LBTVCR_A125NS		0x06	   /* 125 ns A EPROM Access 	 2-0 */
#define	LBTVCR_A85NS		0x07	   /* 85 ns A EPROM Access 	 2-0 */

/*
 * EPROM Decoder, SRAM and DMA Control Register		0x30	23-16
 * Local Bus To VMEbus Requester Control Reg		0x30	15-08
 * DMAC Control Register 1				0x30	07-00
 */

#define	DMACR1_ROM0_ON		(1 << 20)  /* Map EPROM to $00000000	20 */
#define	DMACR1_ROM0_OFF		0x00	   /* No Map EPROM to $00000000	20 */
#define	DMACR1_SNOOP_INHIBIT	0x00	   /* Snoop Inhibited		19-18 */
#define	DMACR1_SINK_DATA	(1 << 18)  /* Sink Data			19-18 */
#define	DMACR1_INVALIDATE	(2 << 18)  /* Invalidate		19-18 */
#define	DMACR1_165NS		0x00	   /* 165 ns SRAM Access Time	17-16 */
#define	DMACR1_125NS		(1 << 16)  /* 125 ns SRAM Access Time	17-16 */
#define	DMACR1_85NS		(2 << 16)  /* 85 ns SRAM Access Time	17-16 */
#define	DMACR1_45NS		(3 << 16)  /* 45 ns SRAM Access Time	17-16 */
#define	DMACR1_ROBIN		(1 << 15)  /* Arbiter in Round Robin	15 */
#define	DMACR1_PRIORITY		0x00	   /* Arbiter in Priority	15 */
#define	DMACR1_DHB		(1 << 14)  /* VMEbus acquired from DWB	14 */
#define	DMACR1_DWB		(1 << 13)  /* VMEbus held		13 */
#define	DMACR1_LVFAIR		(1 << 11)  /* Requester in fair mode	11 */
#define	DMACR1_LVRWD		(1 << 10)  /* Release When Done		10 */
#define	DMACR1_LVROR		0x00	   /* Relase On Request		10 */
#define	DMACR1_LVREQ_L0		0x00	   /* Request Level 0		 9-8 */
#define	DMACR1_LVREQ_L1		(1 << 8)   /* Request Level 1		 9-8 */
#define	DMACR1_LVREQ_L2		(2 << 8)   /* Request Level 2		 9-8 */
#define	DMACR1_LVREQ_L3		(3 << 8)   /* Request Level 3		 9-8 */
#define	DMACR1_DHALT		(1 << 7)   /* Halt at end of Command	 7 */
#define	DMACR1_DEN		(1 << 6)   /* DMAC enabled		 6 */
#define	DMACR1_DTBL		(1 << 5)   /* Command chaining mode	 5 */
#define	DMACR1_DFAIR		(1 << 4)   /* Operates in fair mode	 4 */
#define	DMACR1_TIMER_BRX	0x00	   /* Release with Timer & BRx	 3-2 */
#define	DMACR1_TIMER		(1 << 2)   /* Release with Timer	 3-2 */
#define	DMACR1_BRX		(2 << 2)   /* Release with BRx		 3-2 */
#define DMACR1_TIMER_OR_BRX	(3 << 2)   /* Release with Timer or BRx	 3-2 */
#define	DMACR1_DREQ_L0		0x00	   /* VMEbus request Level 0	 1-0 */
#define	DMACR1_DREQ_L1		0x01	   /* VMEbus request Level 1	 1-0 */
#define	DMACR1_DREQ_L2		0x02	   /* VMEbus request Level 2	 1-0 */
#define	DMACR1_DREQ_L3		0x03	   /* VMEbus request Level 3	 1-0 */

/*
 * DMAC Control Register 2				0x34	15-08
 * DMAC Control Register 2				0x34	07-00
 */

#define	DMACR2_INTE		(1 << 15)  /* Interrupt Enabel		15 */
#define	DMACR2_SNOOP_INHIBIT	0x00	   /* Snoop Inhibited		14-13 */
#define	DMACR2_SINK_DATA	(1 << 13)  /* Sink Data			14-13 */
#define	DMACR2_INVALIDATE	(2 << 13)  /* Invalidate		14-13 */
#define	DMACR2_VINC		(1 << 11)  /* Increment Address on DMA	11 */
#define	DMACR2_LINC		(1 << 10)  /* Increment Local Addr DMA	10 */
#define	DMACR2_TO_VME		(1 << 9)   /* Transfer to VMEbus	 9 */
#define DMACR2_TO_LOCAL		0x00	   /* Transfer to Local bus	 9 */
#define	DMACR2_D16		(1 << 8)   /* D16 on the VMEbus		 8 */
#define	DMACR2_D32		0x00	   /* D32 on the VMEbus		 8 */
#define	DMACR2_NO_BLOCK		0x00	   /* Block Transfers Disabled	 7-6 */
#define	DMACR2_D32_BLOCK	(1 << 6)   /* D32 Block Transfer VMEbus	 7-6 */
#define	DMACR2_D64_BLOCK	(3 << 6)   /* D64 Block Transfer VMEbus	 7-6 */
#define	DMACR2_AM_STD_SUP_ASCENDING	VME_AM_STD_SUP_ASCENDING
#define	DMACR2_AM_STD_SUP_PGM		VME_AM_STD_SUP_PGM
#define	DMACR2_AM_STD_SUP_DATA		VME_AM_STD_SUP_DATA
#define	DMACR2_AM_STD_USR_ASCENDING	VME_AM_STD_USR_ASCENDING
#define	DMACR2_AM_STD_USR_PGM		VME_AM_STD_USR_PGM
#define	DMACR2_AM_STD_USR_DATA		VME_AM_STD_USR_DATA
#define	DMACR2_AM_SUP_SHORT_IO		VME_AM_SUP_SHORT_IO
#define	DMACR2_AM_USR_SHORT_IO		VME_AM_USR_SHORT_IO
#define	DMACR2_AM_EXT_SUP_ASCENDING	VME_AM_EXT_SUP_ASCENDING
#define	DMACR2_AM_EXT_SUP_PGM		VME_AM_EXT_SUP_PGM
#define	DMACR2_AM_EXT_SUP_DATA		VME_AM_EXT_SUP_DATA
#define	DMACR2_AM_EXT_USR_ASCENDING	VME_AM_EXT_USR_ASCENDING
#define	DMACR2_AM_EXT_USR_PGM		VME_AM_EXT_USR_PGM
#define	DMACR2_AM_EXT_USR_DATA		VME_AM_EXT_USR_DATA

/*
 * VMEbus Interrupter Control Register			0x48	31-24
 * VMEbus Interrupter Vector Register			0x48	23-16
 * MPU Status and DMA Interrupt Count Register		0x48	15-08
 * DMAC Status Register					0x48	07-00
 */

#define	ICR_IRQ1_INTERRUPTER	0x00	   /* Intrptr connected to IRQ1	30-29 */
#define	ICR_IRQ1_TIMER1		(1 << 29)  /* Timer 1 connected to IRQ1	30-29 */
#define	ICR_IRQ1_TIMER2		(3 << 29)  /* Timer 2 connected to IRQ2	30-29 */
#define	ICR_IRQ_CLEAR		(1 << 28)  /* Clear VMEbus IRQ		28 */
#define	ICR_IRQ_STATUS		(1 << 27)  /* IRQ not acknowledged	27 */
#define	ICR_IRQ_L1		(1 << 24)  /* Generate VME IRQ level 1	26-24 */
#define	ICR_IRQ_L2		(2 << 24)  /*		       level 2	26-24 */
#define	ICR_IRQ_L3		(3 << 24)  /*		       level 3	26-24 */
#define	ICR_IRQ_L4		(4 << 24)  /*		       level 4	26-24 */
#define	ICR_IRQ_L5		(5 << 24)  /*		       level 5	26-24 */
#define	ICR_IRQ_L6		(6 << 24)  /*		       level 6	26-24 */
#define	ICR_IRQ_L7		(7 << 24)  /*		       level 7	26-24 */
#define	ICR_MCLR		(1 << 11)  /* Clear MPU status bits	11 */
#define	ICR_MLBE		(1 << 10)  /* MPU received a TEA	10 */
#define	ICR_MLPE		(1 << 9)   /* MPU -TEA + Parity error	 9 */
#define	ICR_MLOB		(1 << 8)   /* MPU -TEA + Off board	 8 */
#define	ICR_MLTO		(1 << 7)   /* MPU -TEA + Local Time Out	 7 */