vmechip2.h

IXP425的BSP代码

/* vmechip2.h - VMEbus Interface Controller */

/* Copyright 1991-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01i,26apr02,dat  Adding cplusplus protection, SPR 75017
01h,02nov98,fle  removed all the full star-comment-lines in order for refgen
                 to parse this file
01g,03jan97,mas  casting for VC2GCSR_* set to CASTUC from CASTINT (SPR 3389).
01f,19nov96,mas  fixed comment lines per SPR 5428.
01e,12jan93,ccc  added Miscellaneous Control Register for new chips.
01d,17jun92,ccc  fixed typo, SPR 1353.
01c,26may92,rrr  the tree shuffle
01b,04oct91,rrr  passed through the ansification filter
		  -fixed #else and #endif
		  -changed ASMLANGUAGE to _ASMLANGUAGE
		  -changed copyright notice
01a,17jun91,ccc	 written.
*/

#ifdef	DOC
#define __INCvmechip2h
#endif	/* DOC */

#ifndef	__INCvmechip2h
#define	__INCvmechip2h

#ifdef __cplusplus
extern "C" {
#endif

/*
 * This file contains constants for the mv167 VMEbus Interface controller.
 * The macros VMECHIP2_BASE_ADRS and VC2BUS_BASE_ADRS must be defined
 * when including this header.

 * The registers are listed in ascending (numerical) order; the definitions
 * for each register are started with a header eg.
 */

#ifdef	_ASMLANGUAGE
#define CASTUC
#define CASTINT
#else
#define CASTUC  (UCHAR *)
#define CASTINT (int *)
#endif	/* _ASMLANGUAGE */

/*
 * on-board access, register definitions
 * these registers MUST BE WRITTEN 4-BYTE WRITES ONLY
 * they can be read as byte, two-bytes or 4-bytes.
 */

#define	VMECHIP2_REG_INTERVAL	1

#ifndef VMECHIP2_ADRS	/* to permit alternative board addressing */
#define VMECHIP2_ADRS(reg)   (CASTINT (VMECHIP2_BASE_ADRS + \
				       (reg * VMECHIP2_REG_INTERVAL)))
#define VC2GCSR_ADRS(reg)    (CASTUC (VMECHIP2_BASE_ADRS + 0x100 + \
				      (reg * VMECHIP2_REG_INTERVAL)))
#endif	/* VMECHIP2_ADRS */

#ifndef	VC2BUS_ADRS	/* to permit alternative board addressing */
#define	VC2BUS_ADRS(reg)	(CASTINT (VC2BUS_BASE_ADRS + (reg)))
#endif	/* VC2BUS_ADRS */

/* WRITES MUST BE 4-BYTE WRITES ONLY */
/*
 *		VMEbus Slave Ending Address Register 1		0x00	31-16
 *		VMEbus Slave Starting Address Register 1	0x00	15-00
 */
#define VMECHIP2_VSAR1		VMECHIP2_ADRS(0x00)
/*
 *		VMEbus Slave Ending Address Register 2		0x04	31-16
 *		VMEbus Slave Starting Address Register 2	0x04	15-00
 */
#define	VMECHIP2_VSAR2		VMECHIP2_ADRS(0x04)
/*
 *		VMEbus Slave Address Translation Address Reg 1	0x08	31-16
 *		VMEbus Slave Adrs Translation Select Reg 1	0x08	15-00
 */
#define	VMECHIP2_VSATR1		VMECHIP2_ADRS(0x08)
/*
 *		VMEbus Slave Adrs Translation Address Reg 2	0x0c	31-16
 *		VMEbus Slave Adrs Translation Select Reg 2	0x0c	15-00
 */
#define	VMECHIP2_VSATR2		VMECHIP2_ADRS(0x0c)
/*
 *		VMEbus Slave Write Post and Snoop Control Reg 2	0x10	31-24
 *		VMEbus Slave Address Modifier Select Reg 2	0x10	23-16
 *		VMEbus Slave Write Post and Snoop Control Reg 1	0x10	15-08
 *		VMEbus Slave Address Modifier Select Reg 1	0x10	07-00
 */
#define	VMECHIP2_VSAMSR		VMECHIP2_ADRS(0x10)
/*
 *		Local Bus Slave Ending Address Reg 1		0x14	31-16
 *		Local Bus Slave Starting Address Reg 1		0x14	16-00
 */
#define	VMECHIP2_LBSAR1		VMECHIP2_ADRS(0x14)
/*
 *		Local Bus Slave Ending Address Reg 2		0x18	31-16
 *		Local Bus Slave Starting Address Reg 2		0x18	15-00
 */
#define	VMECHIP2_LBSAR2		VMECHIP2_ADRS(0x18)
/*
 *		Local Bus Slave Ending Address Reg 3		0x1c	31-16
 *		Local Bus Slave Starting Address Reg 3		0x1c	15-00
 */
#define	VMECHIP2_LBSAR3		VMECHIP2_ADRS(0x1c)
/*
 *		Local Bus Slave Ending Address Reg 4		0x20	31-16
 *		Local Bus Slave Starting Address Reg 4		0x20	15-00
 */
#define	VMECHIP2_LBSAR4		VMECHIP2_ADRS(0x20)
/*
 *		Local Bus Slave Address Translation Adrs Reg 1	0x24	31-16
 *		Local Bus Slave Address Translation Sel Reg 1	0x24	15-00
 */
#define	VMECHIP2_LBSATR1	VMECHIP2_ADRS(0x24)
/*
 *		Local Bus Slave Attribute Reg 4			0x28	31-24
 *		Local Bus Slave Attribute Reg 3			0x28	23-16
 *		Local Bus Slave Attribute Reg 2			0x28	15-08
 *		Local Bus Slave Attribute Reg 1			0x28	07-00
 */
#define	VMECHIP2_LBSAR		VMECHIP2_ADRS(0x28)
/*
 *		VMEbus Slave GCSR Group Address Reg		0x2c	31-24
 *		VMEbus Slave GCSR Board Address Reg		0x2c	23-20
 *		Local Bus To VMEbus Enable Control Reg		0x2c	19-16
 *		Local Bus To VMEbus I/O Control Reg		0x2c	15-08
 *		ROM Control Reg					0x2c	07-00
 */
#define	VMECHIP2_LBTVCR		VMECHIP2_ADRS(0x2c)
/*
 *		EPROM Decoder, SRAM and DMA Control Register	0x30	23-16
 *		Local Bus To VMEbus Requester Control Reg	0x30	15-08
 *		DMAC Control Register 1				0x30	07-00
 */
#define	VMECHIP2_DMACR1		VMECHIP2_ADRS(0x30)
/*
 *		DMAC Control Register 2				0x34	15-08
 *		DMAC Control Register 2				0x34	07-00
 */
#define	VMECHIP2_DMACR2		VMECHIP2_ADRS(0x34)
/*
 *		DMAC Local Bus Address Counter			0x38	31-00
 */
#define	VMECHIP2_DMACLBAC	VMECHIP2_ADRS(0x38)
/*
 *		DMAC VMEbus Address Counter			0x3c	31-00
 */
#define	VMECHIP2_DMACVAC	VMECHIP2_ADRS(0x3c)
/*
 *		DMAC Byte Counter				0x40	31-00
 */
#define	VMECHIP2_DMACBC		VMECHIP2_ADRS(0x40)
/*
 *		Table Address Counter				0x44	31-00
 */
#define	VMECHIP2_TAC		VMECHIP2_ADRS(0x44)
/*
 *		VMEbus Interrupter Control Register		0x48	31-24
 *		VMEbus Interrupter Vector Register		0x48	23-16
 *		MPU Status and DMA Interrupt Count Register	0x48	15-08
 *		DMAC Status Register				0x48	07-00
 */
#define	VMECHIP2_ICR		VMECHIP2_ADRS(0x48)
/*
 *		VMEbus Arbiter Timeout Control Register		0x4c	31-24
 *		DMAC Ton/Toff Timers and VMEbus Global Timeout	0x4c	23-16
 *		VME Access, Local Bus and Watchdog Timeout	0x4c	15-08
 *		Prescaler Control Register			0x4c	07-00
 */
#define	VMECHIP2_TIMEOUTCR	VMECHIP2_ADRS(0x4c)
/*
 *		Tick Timer 1 Compair Register			0x50	31-00
 */
#define	VMECHIP2_TTCOMP1	VMECHIP2_ADRS(0x50)
/*
 *		Tick Timer 1 Counter				0x54	31-00
 */
#define	VMECHIP2_TTCOUNT1	VMECHIP2_ADRS(0x54)
/*
 *		Tick Timer 2 Compair Register			0x58	31-00
 */
#define	VMECHIP2_TTCOMP2	VMECHIP2_ADRS(0x58)
/*
 *		Tick Timer 2 Counter				0x5c	31-00
 */
#define	VMECHIP2_TTCOUNT2	VMECHIP2_ADRS(0x5c)
/*
 *		Board Control Register				0x60	31-24
 *		Watchdog Timer Control Register			0x60	23-16
 *		Tick Timer 2 Control Register			0x60	15-08
 *		Tick Timer 1 Control Register			0x60	07-00
 */
#define	VMECHIP2_TIMERCR	VMECHIP2_ADRS(0x60)
/*
 *		Prescaler Counter				0x64	31-00
 */
#define	VMECHIP2_PRESCALE_CNT	VMECHIP2_ADRS(0x64)
/*
 *		Local Bus Interrupter Status Reg (24-31)	0x68	31-24
 *		Local Bus Interrupter Status Reg (16-23)	0x68	23-16
 *		Local Bus Interrupter Status Reg (8-15)		0x68	15-08
 *		Local Bus Interrupter Status Reg (0-7)		0x68	07-00
 */
#define	VMECHIP2_LBISR		VMECHIP2_ADRS(0x68)
/*
 *		Local Bus Interrupter Enable Reg (24-31)	0x6c	31-24
 *		Local Bus Interrupter Enable Reg (16-23)	0x6c	24-16
 *		Local Bus Interrupter Enable Reg (8-15)		0x6c	15-08
 *		Local Bus Interrupter Enable Reg (0-7)		0x6c	07-00
 */
#define	VMECHIP2_LBIER		VMECHIP2_ADRS(0x6c)
/*
 *		Software Interrupt Set Register (8-15)		0x70	15-08
 */
#define	VMECHIP2_SISR		VMECHIP2_ADRS(0x70)
/*
 *		Interrupt Clear Register (24-31)		0x74	31-24
 *		Interrupt Clear Register (16-23)		0x74	23-16
 *		Interrupt Clear Register (08-15)		0x74	15-08
 */
#define	VMECHIP2_ICLR		VMECHIP2_ADRS(0x74)
/*
 *		Interrupt Level Register 1 (24-31)		0x78	31-24
 *		Interrupt Level Register 1 (16-23)		0x78	23-16
 *		Interrupt Level Register 1 (8-15)		0x78	15-08
 *		Interrupt Level Register 1 (0-7)		0x78	07-00
 */
#define	VMECHIP2_ILR1		VMECHIP2_ADRS(0x78)
/*
 *		Interrupt Level Register 2 (24-31)		0x7c	31-24
 *		Interrupt Level Register 2 (16-23)		0x7c	23-16
 *		Interrupt Level Register 2 (8-15)		0x7c	15-08
 *		Interrupt Level Register 2 (0-7)		0x7c	07-00
 */
#define	VMECHIP2_ILR2		VMECHIP2_ADRS(0x7c)
/*
 *		Interrupt Level Register 3 (24-31)		0x80	31-24
 *		Interrupt Level Register 3 (16-23)		0x80	23-16
 *		Interrupt Level Register 3 (8-15)		0x80	15-08
 *		Interrupt Level Register 3 (0-7)		0x80	07-00
 */
#define	VMECHIP2_ILR3		VMECHIP2_ADRS(0x80)
/*
 *		Interrupt Level Register 4 (24-31)		0x84	31-24
 *		Interrupt Level Register 4 (16-23)		0x84	23-16
 *		Interrupt Level Register 4 (8-15)		0x84	15-08
 *		Interrupt Level Register 4 (0-7)		0x84	07-00
 */
#define	VMECHIP2_ILR4		VMECHIP2_ADRS(0x84)
/*
 *		Vector Base Register				0x88	31-24
 *		I/O Control Register 1				0x88	23-16
 *		I/O Control Register 2				0x88	15-08
 *		I/O Control Register 3				0x88	07-00
 */
#define	VMECHIP2_IOCR		VMECHIP2_ADRS(0x88)
/*
 *		Miscellaneous Control Register			0x8c    07-00
 */
#define	VMECHIP2_MISCCR		VMECHIP2_ADRS(0x8c)

/* These Global Status and Control Register are 16-bit registers
 * accessible from both the VMEbus and the local bus.
 * They are byte accessible registers.
 */

#define	VC2GCSR_REVISION	VC2GCSR_ADRS(0x02)  /* VMEchip2 Rev Reg */
#define	VC2GCSR_ID		VC2GCSR_ADRS(0x03)  /* VMEchip2 ID Reg */
#define	VC2GCSR_LM_SIG		VC2GCSR_ADRS(0x06)  /* VMEchip2 LM/SIG Reg */
#define	VC2GCSR_BSCR		VC2GCSR_ADRS(0x07)  /* Board Stat/Cont Reg */
#define	VC2GCSR_GPR0H		VC2GCSR_ADRS(0x0a)  /* General Purpose Reg 0 */
#define	VC2GCSR_GPR0L		VC2GCSR_ADRS(0x0b)  /* General Purpose Reg 0 */
#define	VC2GCSR_GPR1H		VC2GCSR_ADRS(0x0e)  /* General Purpose Reg 1 */
#define	VC2GCSR_GPR1L		VC2GCSR_ADRS(0x0f)  /* General Purpose Reg 1 */
#define	VC2GCSR_GPR2H		VC2GCSR_ADRS(0x12)  /* General Purpose Reg 2 */
#define	VC2GCSR_GPR2L		VC2GCSR_ADRS(0x13)  /* General Purpose Reg 2 */
#define	VC2GCSR_GPR3H		VC2GCSR_ADRS(0x16)  /* General Purpose Reg 3 */
#define	VC2GCSR_GPR3L		VC2GCSR_ADRS(0x17)  /* General Purpose Reg 3 */