vic068.h

IXP425的BSP代码

#define	LBTR_PASH_2		0x20	/* PAS high 2 * 64 MHz clocks	75 */
#define	LBTR_PASH_3		0x40	/* PAS high 3 * 64 MHz clocks	75 */
#define	LBTR_PASH_4		0x60	/* PAS high 4 * 64 MHz clocks	75 */
#define	LBTR_PASH_5		0x80	/* PAS high 5 * 64 MHz clocks	75 */
#define	LBTR_PASH_6		0xa0	/* PAS high 6 * 64 MHz clocks	75 */
#define	LBTR_PASH_7		0xc0	/* PAS high 7 * 64 MHz clocks	75 */
#define	LBTR_PASH_8		0xe0	/* PAS high 8 * 64 MHz clocks	75 */

/***************************************************************
* BTDR         0x2a    0xab     Block Transfer Definition Reg  *
****************************************************************/

#define	BTDR_DPADEN		0x01	/* enable dual path DPADEN	0 */
#define	BTDR_AMSR		0x02	/* use AMSR for BT add modifier 1 */
#define	BTDR_LBTDMA_ENA		0x04	/* enable local BT 256 byte DMA 2 */
#define	BTDR_VBTDMA_ENA		0x08    /* enable  VME BT 256 byte DMA	3 */

/***************************************************************
* ICR          0x2b    0xaf     Interface Configuration Reg    *
****************************************************************/

#define	ICR_SCON		0x01	/* system controller pin           0 */
#define	ICR_TURBO		0x02	/* speed up transfers              1 */
#define	ICR_MORE_SETTLE_TIME	0x04	/* add 1 64 MHz intvl to async pins2 */
#define	ICR_DLK_RMC_NO_RETRY	0x08	/* enable deadlock signalling      3 */
#define	ICR_DLK_RETRY		0x10	/* signal deadlock with HALT*      4 */
#define	ICR_REQ_RMC		0x20	/* request bus if RMC* is asserted 5 */
#define	ICR_AS_STRETCH		0x40	/* strech AS*                      6 */
#define	ICR_AS_SIZE		0x80	/* use size information for AS*    7 */

/***************************************************************
* ARCR         0x2c    0xb3     Arbiter/Requester Config. Reg  *
****************************************************************/

#define	ARCR_NOT_FAIR		0x00	/* disable fairness               30 */
#define	ARCR_NO_TOUT		0x0f	/* disable timeout                30 */
#define	ARCR_DRAM_REFRESH	0x10	/* enable DRAM refresh             4 */

#define	ARCR_VBRL_BR0		0x00	/* VME bus request level BR0      65 */
#define	ARCR_VBRL_BR1		0x20	/* VME bus request level BR1      65 */
#define	ARCR_VBRL_BR2		0x40	/* VME bus request level BR2      65 */
#define	ARCR_VBRL_BR3		0x60	/* VME bus request level BR3      65 */

#define	ARCR_RND_ROBIN		0x00	/* select round robin arbitration  7 */
#define	ARCR_PRIORITY		0x80	/* select priority arbitration     7 */

/***************************************************************
* AMSR         0x2d    0xb7     AM Source Reg                  *
****************************************************************/

	/* Extended (A32) address modifier codes   */

#define AMSR_EXT_USR_DATA	0x09	/* user data		       50 */
#define AMSR_EXT_USR_PROG	0x0a	/* user program	access	       50 */
#define AMSR_EXT_USR_BLOCK	0x0b	/* user block transfer access  50 */
#define AMSR_EXT_SPR_DATA	0x0d	/* supervisory data access     50 */
#define AMSR_EXT_SPR_PROG	0x0e	/* supervisory program access  50 */
#define AMSR_EXT_SPR_BLOCK	0x0f	/* super block transfer access 50 */

	/* AMSR_Short (A16) address modifier codes      */

#define AMSR_SHT_USR_ACCESS	0x29	/* user access                 50 */
#define AMSR_SHT_SPR_ACCESS	0x2d	/* supervisory access          50 */

	/* AMSR_Standard (A24) address modifier codes   */

#define AMSR_STD_USR_DATA	0x39    /* user data                   50 */
#define AMSR_STD_USR_PROG	0x3a    /* user program access         50 */
#define AMSR_STD_USR_BLOCK	0x3b    /* user block transfer access  50 */
#define AMSR_STD_SPR_DATA	0x3d    /* supervisory data access     50 */
#define AMSR_STD_SPR_PROG	0x3e    /* supervisory program access  50 */
#define AMSR_STD_SPR_BLOCK	0x3f    /* super block transfer access 50 */

	/* AMSR_during slave access/cycles   */

#define AMSR_SLV_CMP_ALL	0x00	/* all 6 add modifier bits comp	   6 */
#define AMSR_SLV_CMP_3MSB	0x40	/* only 3 most significant add	   6 */
					/* modifier bits compared	     */

	/* Master access/cycles	     */

#define AMSR_MSTR_CMP_ALL	0x00	/* all 6 add modifier bits used	   7 */
#define AMSR_MSTR_CMP_3MSB	0x80	/* only 3 most significant add	   7 */
					/* modifier bits used		     */

/***************************************************************
* BESR         0x2e    0xbb     Bus Error Status Reg           *
****************************************************************/

#define BESR_LBTOA	0x01	/* local  bus time out during		0 */
				/* attempted acquisition		  */
#define BESR_SA_SLSEL1	0x02	/* self-access by SLSEL1		1 */
#define BESR_SA_SLSEL0	0x04	/* self-access by SLSEL0		2 */
#define BESR_LBTO	0x08	/* local  bus time out			3 */
#define BESR_VBTO	0x10	/* VMEbus time out (bus master)		4 */
#define BESR_VBERR	0x20	/* VMEbus bus error BERR*		5 */
#define BESR_LBERR	0x40	/* local  bus error LBERR*		6 */
#define BESR_MASTER	0x80	/* the VIC is VMEbus master		7 */

/***************************************************************
* DSR          0x2f    0xbf     DMA Status Reg                 *
****************************************************************/

#define DSR_INTER_DMA	0x01	/* interleaved DMA in progress		0 */
#define DSR_LBERR_DMA	0x02	/* local  bus error LBERR* during DMA	1 */
#define DSR_VBERR_DMA	0x04	/* VMEbus bus error BERR*  during DMA	2 */
#define DSR_LBERR	0x08	/* local  bus error LBERR* asserted    	3 */
#define DSR_VBERR	0x10	/* VMEbus bus error BERR*  asserted	4 */
#define DSR_BTDMA	0x60	/* VME/local 256 byte address error    65 */
#define	DSR_MASTER_WP	0x80	/* master write post info is stored	7 */

/****************************************************************/
/* SS0CR0       0x30    0xc3     Slave Select 0/Control Reg #0  */
/* and								*/
/* SS1CR0       0x32    0xcb     Slave Select 1/Control Reg #0  */
/****************************************************************/

/* SS0CR0 and SS1CR0 */

#define	SSCR0_BLT_NONE		0x00	/* no block transfer allowed	   10 */
#define	SSCR0_BLT_LOCAL		0x01	/* emulate blck trans on local bus 10 */
#define	SSCR0_BLT_ACC		0x02	/* accelerated block transfer      10 */

#define	SSCR0_ASIZ_A32		0x00	/* A32   address size		   32 */
#define	SSCR0_ASIZ_A24		0x04	/* A24   address size		   32 */
#define	SSCR0_ASIZ_A16		0x08	/* A16   address size		   32 */
#define	SSCR0_ASIZ_AMREG	0x0c	/* use Addr Modifier source reg    32 */

#define	SSCR0_SLSEL_D32		0x10	/* D32 SLSEL[01]* data size	    4 */
#define	SSCR0_SLSEL_D16		0x00	/* D32 SLSEL[01]* data size	    4 */

#define	SSCR0_SLSEL_SPR		0x20 /* supervisory SLSEL[01]* access only  5 */
#define	SSCR0_SLSEL_ALL		0x00 /* all modes   SLSEL[01]* access	    5 */

/* SS1CR0 */

#define SSCR0_MASTER_WP     	0x40    /* enable master write posting	    6 */
#define SSCR0_MASTER_NWP     	0x00    /* no     master write posting	    6 */

#define SSCR0_SLAVE_WP      	0x80    /* enable slave  write posting	    7 */
#define SSCR0_SLAVE_NWP      	0x00    /* no     slave  write posting	    7 */

/* SS0CR0 */

#define	SSCR0_TIMER_MASK	0x3f	/* timer field mask                   */
#define	SSCR0_TIMER_DIS		0x00	/* timer disabled		   76 */
#define	SSCR0_TIMER_50		0x40	/* 50  Hz timer (output on LIRQ2*) 76 */
#define	SSCR0_TIMER_1000	0x80	/* 1000 Hz timer (outpt on LIRQ2*) 76 */
#define	SSCR0_TIMER_100		0xc0	/* 100 Hz timer (output on LIRQ2*) 76 */

/***************************************************************
* SS0CR1       0x31    0xc7     Slave Select 0/Control Reg #1  *
* and							       *
* SS1CR1       0x33    0xcf     Slave Select 1/Control Reg #1  *
****************************************************************/

#define	SSCR1_DTACK_0		0x00	/* 0   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_2		0x01	/* 2   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_25		0x02	/* 2.5 x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_3		0x03	/* 3   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_35		0x04	/* 3.5 x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_4		0x05	/* 4   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_45		0x06	/* 4.5 x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_5		0x07	/* 5   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_55		0x08	/* 5.5 x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_6		0x09	/* 6   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_65		0x0a	/* 6.5 x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_7		0x0b	/* 7   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_75		0x0c	/* 7.5 x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_8		0x0d	/* 8   x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_85		0x0e	/* 8.5 x 64 Mhz DTACK* delay	30 */
#define	SSCR1_DTACK_9		0x0f	/* 9   x 64 Mhz DTACK* delay	30 */

#define	SSCR1_DSACK_0		0x00	/* 0   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_2		0x10	/* 2   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_25		0x20	/* 2.5 x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_3		0x30	/* 3   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_35		0x40	/* 3.5 x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_4		0x50	/* 4   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_45		0x60	/* 4.5 x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_5		0x70	/* 5   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_55		0x80	/* 5.5 x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_6		0x90	/* 6   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_65		0xa0	/* 6.5 x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_7		0xb0	/* 7   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_75		0xc0	/* 7.5 x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_8		0xd0	/* 8   x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_85		0xe0	/* 8.5 x 64 Mhz DTACK* delay	74 */
#define	SSCR1_DSACK_9		0xf0	/* 9   x 64 Mhz DTACK* delay	74 */

/***************************************************************
* RCR          0x34    0xd3     Release Control Reg            *
****************************************************************/

#define	RCR_ROR			0x00	/* release on request		76 */
#define	RCR_RWD			0x40	/* release when done		76 */
#define	RCR_ROC			0x80	/* release on BCLR*		76 */
#define	RCR_BCAP		0xc0	/* bus capture and hold		76 */

/***************************************************************
* BTCR         0x35    0xd7     Block Transfer Control Reg     *
****************************************************************/

#define	BTCR_LCIP_MASK		0x0f	/* local cycle interl've period mk 30 */

#define	BTCR_DMA_WRITE		0x10	/* write DMA enable		    4 */

	/* Note: bits 7, 6 and 5 are mutually exclusive        */

#define	BTCR_MBT		0x20	/* enable   MOVEM type block trsfer 5 */
#define	BTCR_VDMA_GO		0x40	/* initiate VME   DMA block trsfer  6 */
#define	BTCR_LDMA_GO		0x80	/* initiate local DMA block trsfer  7 */

/***************************************************************
* BTLR0        0x36    0xdb     Block Transfer Length Reg #0   *
* and							       *
* BTLR1        0x37    0xdf     Block Transfer Length Reg #1   *
****************************************************************/

/* none */

/***************************************************************
* SRR          0x38    0xe3     System Reset Reg               *
****************************************************************/

#define	SRR_SYSRESET	0xf0	/* assert SYSRESET on the VMEbus and	*/
				/* reset all reset-able VIC registers	*/

#ifdef __cplusplus
}
#endif

#endif /* __INCvic068h */