vic068.h

IXP425的BSP代码

* to                                                           *
* LICR7        0x0f    0x3f     Local Interrupt Control Reg #7 *
****************************************************************/

#define	LICR_IRQ_LVL_MASK	0x07	/* local interrupt level mask	  */
#define	LICR_IRQ_STATE		0x08	/* LIRQ(i) state		3 */
#define	LICR_IRQ_VEC_DEV	0x00	/* device supplies vector	4 */
#define	LICR_IRQ_VEC_VIC	0x10	/* VIC supplies vector		4 */
#define	LICR_IRQ_LEVEL		0x00	/* level sensitive		5 */
#define	LICR_IRQ_EDGE		0x20	/* edge sensitive		5 */
#define	LICR_IRQ_ACTIVEL	0x00	/* active low			6 */
#define	LICR_IRQ_ACTIVEH	0x40	/* active high			6 */
#define	LICR_IRQ_ENABLE		0x00	/* enable  IRQ			7 */
#define	LICR_IRQ_DISABLE	0x80	/* disable IRQ			7 */

/***************************************************************
* ICGICR       0x10    0x43     ICGS Interrupt Control Reg     *
****************************************************************/

#define	ICGICR_IRQ_LVL_MASK	0x07	/* local interrupt level mask	  */
#define	ICGICR_IRQ_ICGS0_ENA	0x00	/* enable  ICGS0 local interrpt 4 */
#define	ICGICR_IRQ_ICGS0_DIS	0x10	/* disable ICGS0 local interrpt 4 */
#define	ICGICR_IRQ_ICGS1_ENA	0x00	/* enable  ICGS1 local interrpt 5 */
#define	ICGICR_IRQ_ICGS1_DIS    0x20	/* disable ICGS1 local interrpt 5 */
#define	ICGICR_IRQ_ICGS2_ENA	0x00	/* enable  ICGS2 local interrpt 6 */
#define	ICGICR_IRQ_ICGS2_DIS	0x40	/* disable ICGS2 local interrpt 6 */
#define	ICGICR_IRQ_ICGS3_ENA	0x00	/* enable  ICGS3 local interrpt 7 */
#define	ICGICR_IRQ_ICGS3_DIS	0x80	/* disable ICGS3 local interrpt 7 */

/***************************************************************
* ICMICR       0x11    0x47     ICMS Interrupt Control Reg     *
****************************************************************/

#define	ICMICR_IRQ_LVL_MASK	0x07	/* local interrupt level mask	  */
#define	ICMICR_IRQ_ICMS0_DIS	0x10	/* disable ICMS0 local interrpt 4 */
#define	ICMICR_IRQ_ICMS1_DIS	0x20	/* disable ICMS1 local interrpt 5 */
#define	ICMICR_IRQ_ICMS2_DIS	0x40	/* disable ICMS2 local interrpt 6 */
#define	ICMICR_IRQ_ICMS3_DIS	0x80	/* disable ICMS3 local interrpt 7 */

/***************************************************************
* EGICR        0x12    0x4b     Error Group Int Control Reg    *
****************************************************************/

#define	EGICR_IRQ_LVL_MASK	0x07	/* local interrupt level mask	  */
#define	EGICR_IRQ_SYSFAIL_ENA	0x00	/* enable  SYSFAIL* local int	4 */
#define	EGICR_IRQ_SYSFAIL_DIS	0x10	/* disable SYSFAIL* local int	4 */
#define	EGICR_IRQ_ABTTO_ENA	0x00	/* enable  arbitration time out	5 */
#define	EGICR_IRQ_ABTTO_DIS	0x20	/* disable arbitration time out	5 */
#define	EGICR_IRQ_WPFAIL_ENA	0x00	/* enable  write post fail	6 */
#define	EGICR_IRQ_WPFAIL_DIS	0x40	/* disable write post fail	6 */
#define	EGICR_IRQ_ACFAIL_ENA	0x00	/* enable  ACFAIL* local int	7 */
#define	EGICR_IRQ_ACFAIL_DIS	0x80	/* disable ACFAIL* local int	7 */

/***************************************************************
* ICGIVBR      0x13    0x4f     ICGS Interrupt Vector Base Reg *
****************************************************************/

/* Identity of interrupting ICGS (read only)	*/

#define	ICGIVBR_ICGS0		0x00	/* ICGS0		10 */
#define	ICGIVBR_ICGS1		0x01	/* ICGS1		10 */
#define	ICGIVBR_ICGS2		0x02	/* ICGS2		10 */
#define	ICGIVBR_ICGS3		0x03	/* ICGS3		10 */
#define	ICGIVBR_VEC_MASK	0xfc	/* ICGS vector base mask   */

/***************************************************************
* ICMIVBR      0x14    0x53     ICMS Interrupt Vector Base Reg *
****************************************************************/

/* Identity of interrupting ICMS (read only)	*/

#define	ICMIVBR_ICMS0		0x00	/* ICMS0		10 */
#define	ICMIVBR_ICMS1		0x01	/* ICMS1		10 */
#define	ICMIVBR_ICMS2		0x02	/* ICMS2		10 */
#define	ICMIVBR_ICMS3		0x03	/* ICMS3		10 */
#define	ICMIVBR_VEC_MASK	0xfc	/* ICMI vector base mask   */

/***************************************************************
* LIVBR        0x15    0x57     Local Int Vector Base Reg      *
****************************************************************/

/* Identity of local interrupt (read only)	*/

#define	LIVBR_LIRQ1		0x01	/* LIRQ1		20 */
#define	LIVBR_LIRQ2		0x02	/* LIRQ2		20 */
#define	LIVBR_LIRQ3		0x03	/* LIRQ3		20 */
#define	LIVBR_LIRQ4		0x04	/* LIRQ4		20 */
#define	LIVBR_LIRQ5		0x05	/* LIRQ5		20 */
#define	LIVBR_LIRQ6		0x06	/* LIRQ6		20 */
#define	LIVBR_LIRQ7		0x07	/* LIRQ7		20 */
#define	LIVBR_VEC_MASK		0xf8	/* LIRQ vector base mask   */

/***************************************************************
* EGIVBR       0x16    0x5b     Error Group Int Vec Base Reg   *
****************************************************************/

/* Error Conditions (read only)	*/

#define	EGIVBR_ACFAIL		0x00	/* ACFAIL* error condition	20 */
#define	EGIVBR_WPFAIL		0x01	/* write post fail error cond	20 */
#define	EGIVBR_ABTTO		0x02	/* arbitration time out err con	20 */
#define	EGIVBR_SYSFAIL		0x03	/* SYSFAIL* error condition	20 */
#define	EGIVBR_VIIA		0x04	/* VMEbus Interrupter Interrupt	20 */
					/* Acknowledge error condition	20 */
#define	EGIVBR_DMAI		0x05	/* DMA Interrupt		20 */
#define	EGIVBR_VEC_MASK		0xf8	/* EGIRQ vector base mask   */

/***************************************************************
* ICSR         0x17    0x5f     Interprocessor Comm Switch Reg *
****************************************************************/

#define ICSR_ICMS0		0x01	/* set   ICMS0			 0 */
#define ICSR_ICMS1		0x02	/* set   ICMS1			 1 */
#define ICSR_ICMS2		0x04	/* set   ICMS2			 2 */
#define ICSR_ICMS3		0x08	/* set   ICMS3			 3 */

/* ICGS (read only) */

#define ICSR_ICGS0		0x10	/* set   ICGS0			 4 */
#define ICSR_ICGS1		0x20	/* set   ICGS1			 5 */
#define ICSR_ICGS2		0x40	/* set   ICGS2			 6 */
#define ICSR_ICGS3		0x80	/* set   ICGS3			 7 */

/***************************************************************
* ICR0         0x18    0x63     Interprocessor Comm. Reg #0    *
* to                                                           *
* ICR4         0x1c    0x73     Interprocessor Comm. Reg #4    *
****************************************************************/

/* none */

/***************************************************************
* ICR5         0x1d    0x77     Interprocessor Comm. Reg #5    *
*                               (VIC ID Register)	       *
****************************************************************/

/* none - revisions are referred to by the hex code */

/***************************************************************
* ICR6         0x1e    0x7b     Interprocessor Comm. Reg #6    *
****************************************************************/

/* XXX should the following fields be 6 or 7 bits wide ? */

#define ICR6_HALT		0x3d	/* VIC detected VME HALT	  50 */
#define ICR6_IRESET		0x3e	/* VIC performing reset function  50 */
#define ICR6_SYSRESET		0x3f	/* VMEbus SYSRESET		  50 */
#define ICR6_HALT_IRESET	0x40	/* VMEbus HALT or IRESET asserted  6 */
#define ICR6_SYSFAIL		0x40	/* assert SYSFAIL		   6 */
#define ICR6_ACFAIL		0x80	/* ACFAIL state			   7 */

/***************************************************************
* ICR7         0x1f    0x7f     Interprocessor Comm. Reg #7    *
****************************************************************/

#define ICR7_ICR0		0x01	/* ICR0 semaphore		0 */
#define ICR7_ICR1		0x02	/* ICR1 semaphore		1 */
#define ICR7_ICR2		0x04	/* ICR2 semaphore		2 */
#define ICR7_ICR3		0x08	/* ICR3 semaphore		3 */
#define ICR7_ICR4		0x10	/* ICR4 semaphore		4 */
#define ICR7_MASTER    		0x20    /* the VIC is VMEbus master     5 */
#define ICR7_RESET		0x40	/* assert  RESET* and HALT* 	6 */
#define ICR7_SYSFAIL_INH	0x80	/* inhibit SYSFAIL* assertion	7 */

/*****************************************************************
* VIRSR        0x20    0x83     VME Interrupt Request/Status Reg *
******************************************************************/

#define VIRSR_IRQ_ENA		0x01     /* VMEbus interrupt enable 	0 */
#define VIRSR_IRQ1		0x02     /* assert on VMEbus, VME IRQ 1 1 */
#define VIRSR_IRQ2		0x04     /* assert on VMEbus, VME IRQ 2 2 */
#define VIRSR_IRQ3		0x08     /* assert on VMEbus, VME IRQ 3 3 */
#define VIRSR_IRQ4		0x10     /* assert on VMEbus, VME IRQ 4 4 */
#define VIRSR_IRQ5		0x20     /* assert on VMEbus, VME IRQ 5 5 */
#define VIRSR_IRQ6		0x40     /* assert on VMEbus, VME IRQ 6 6 */
#define VIRSR_IRQ7		0x80     /* assert on VMEbus, VME IRQ 7 7 */

/***************************************************************
* VIVR1        0x21    0x87     VME Interrupt Vector Reg #1    *
* to                                                           *
* VIVR7        0x27    0xaf     VME Interrupt Vector Reg #7    *
****************************************************************/

/* none */

/***************************************************************
* TTR          0x28    0xa3     Transfer Time-out Reg          *
****************************************************************/

#define	TTR_VTO_ACQ_EXC		0x00	/* exclude aquisition time	 0 */
#define	TTR_VTO_ACQ_INC		0x01	/* include aquisition time	 0 */
#define	TTR_ARBTO		0x02	/* arbitration timeout occured	 1 */
#define	TTR_LTO_4		0x00	/* local 4 us time out		42 */
#define	TTR_LTO_16		0x04	/* local 16 us time out 	42 */
#define	TTR_LTO_32		0x08	/* local 32 us time out 	42 */
#define	TTR_LTO_64		0x0c	/* local 64 us time out		42 */
#define	TTR_LTO_128		0x10	/* local 128 us time out	42 */
#define	TTR_LTO_256		0x14	/* local 256 us time out	42 */
#define	TTR_LTO_512		0x18	/* local 512 us time out	42 */
#define	TTR_LTO_INF		0x1c	/* local infinite time out	42 */
#define	TTR_VTO_4		0x00	/* VMEbus 4 us time out		75 */
#define	TTR_VTO_16		0x20	/* VMEbus 16 us time out	75 */
#define	TTR_VTO_32		0x40	/* VMEbus 32 us time out	75 */
#define	TTR_VTO_64		0x60	/* VMEbus 64 us time out	75 */
#define	TTR_VTO_128		0x80	/* VMEbus 128 us time out	75 */
#define	TTR_VTO_256		0xa0	/* VMEbus 256 us time out	75 */
#define	TTR_VTO_512		0xc0	/* VMEbus 512 us time out	75 */
#define	TTR_VTO_INF		0xe0	/* VMEbus infinite time out	75 */

/***************************************************************
* LBTR         0x29    0xa7     Local Bus Timing Reg           *
****************************************************************/

#define	LBTR_PASL_2		0x00	/* PAS low 2 * 64 MHz clocks	30 */
#define	LBTR_PASL_3		0x01	/* PAS low 3 * 64 MHz clocks	30 */
#define	LBTR_PASL_4		0x02	/* PAS low 4 * 64 MHz clocks	30 */
#define	LBTR_PASL_5		0x03	/* PAS low 5 * 64 MHz clocks	30 */
#define	LBTR_PASL_6		0x04	/* PAS low 6 * 64 MHz clocks	30 */
#define	LBTR_PASL_7		0x05	/* PAS low 7 * 64 MHz clocks	30 */
#define	LBTR_PASL_8		0x06	/* PAS low 8 * 64 MHz clocks	30 */
#define	LBTR_PASL_9		0x07	/* PAS low 9 * 64 MHz clocks	30 */
#define	LBTR_PASL_10		0x08	/* PAS low 10 * 64 MHz clocks	30 */
#define	LBTR_PASL_11		0x09	/* PAS low 11 * 64 MHz clocks	30 */
#define	LBTR_PASL_12		0x0a	/* PAS low 12 * 64 MHz clocks	30 */
#define	LBTR_PASL_13		0x0b	/* PAS low 13 * 64 MHz clocks	30 */
#define	LBTR_PASL_14		0x0c	/* PAS low 14 * 64 MHz clocks	30 */
#define	LBTR_PASL_15		0x0d	/* PAS low 15 * 64 MHz clocks	30 */
#define	LBTR_PASL_16		0x0e	/* PAS low 16 * 64 MHz clocks	30 */
#define	LBTR_PASL_17		0x0f	/* PAS low 17 * 64 MHz clocks	30 */

#define	LBTR_DS_1		0x00	/* DS 1 * 64 MHz clocks 	 4 */
#define	LBTR_DS_2		0x10	/* DS 2 * 64 MHz clocks 	 4 */

#define	LBTR_PASH_1		0x00	/* PAS high 1 * 64 MHz clocks	75 */