vic068.h

IXP425的BSP代码

/* vic068.h - VMEbus Interface Controller */

/* Copyright 1984-1992 Wind River Systems, Inc. */
/*
modification history
--------------------
01k,22sep92,rrr  added support for c++
01j,26may92,rrr  the tree shuffle
01i,04oct91,rrr  passed through the ansification filter
		  -fixed #else and #endif
		  -changed ASMLANGUAGE to _ASMLANGUAGE
		  -changed copyright notice
01h,06may91,nfs  moved ifdef's to ensure clean mangening
01g,30apr91,nfs  added ifdef for documentation
01f,25apr91,nfs  corrected VME_ICGS and VME_ICMS defines (rs33 document error)
		 corrected VME_SET_ADRS and VME_CLR_ADRS (VIC document error)
                 ICR5 defines removed, revisions are referred to by their hex
		 code (f1,f2,f3,f4,f5 and f8 are currently valid)
01e,25mar91,del  re-definition of VIC_ADRS and VME_ICF_ADRS permitted
01d,25mar91,nfs  re-written
            jcf
01c,25nov90,gae  WRS cleanup.
01b,22mar90,eve	 general cleanup
01a,12mar89,fwa	 written.
*/

#ifdef DOC
#define INCvic068h
#endif	/* DOC */

#ifndef __INCvic068h
#define __INCvic068h

#ifdef __cplusplus
extern "C" {
#endif

/*
This file contains constants for the VTC VMEbus Interface controller.
The macro VIC_BASE_ADRS must be defined when including this header.

The following standards have been adopted in the creation of this file.

Register definitions which provide access to the VIC chip locally
(on-board) have the prefix "VIC".  Register definitions which provide
access to the VIC chip via the VMEbus (off-board) have the prefix
"VME".

The registers are listed in ascending (numerical) order; the definitions
for each register are started with a header eg.

 Register    Register Register          Register
 Mnemonic     Number  Address             Name
    |           |        |                 |
    v           v        v                 v
*****************************************************************
* VIICR        0x01    0x03     VME Interrupter Irq Control Reg *
*****************************************************************

in some cases where a number of registers have the same definitions the
header looks like this eg.

****************************************************************
* VICR1        0x02    0x07     VME Interrupt Control Reg #1   *
* to                                                           *
* VICR7        0x08    0x1f     VME Interrupt Control Reg #7   *
****************************************************************

The format of the definitions is as follows; the define name always
starts with the register mnemonic it is associated with. The [7-0]
number at the end of the comment indicates the bit position the define
applies to; the definition ICGICR_IRQ_EN_ICGS3, in the following
example, the 7 applies to bit 7
	   |								|
	   v								v
 define	ICGICR_IRQ_EN_ICGS3	0x00	 * enable  ICGS3 local int	7 *

If the define applies to more than one bit, then the applicable bit
range is specified by two digits; in the following example ICGICR_IRQ_EN_ICGS,
applies to the four bit field, bits 7-4.
									|
									v
 define	ICGICR_IRQ_EN_ICGS	0x00	 * enable  all ICGS local int's 74 *

If no bit field is given, then the define applies to the whole register.
*/

#ifdef	_ASMLANGUAGE
#define CAST
#else
/* #define CAST	(UCHAR *) */
#define CAST (char *)
#endif	/* _ASMLANGUAGE */

/* on-board access, register definitions */

#define	VIC_REG_INTERVAL	4

#ifndef VIC_ADRS	/* to permit alternative board addressing */
#define VIC_ADRS(reg)   (CAST (VIC_BASE_ADRS + (reg * VIC_REG_INTERVAL) + 3))
#endif	/* VIC_ADRS */

#define VIC_VIICR	VIC_ADRS(0x00)	/* VME Interrupter Irq Control Reg */
#define VIC_VICR1	VIC_ADRS(0x01)	/* VME Interrupt Control Reg #1    */
#define VIC_VICR2	VIC_ADRS(0x02)	/* VME Interrupt Control Reg #2    */
#define VIC_VICR3	VIC_ADRS(0x03)	/* VME Interrupt Control Reg #3    */
#define VIC_VICR4	VIC_ADRS(0x04)	/* VME Interrupt Control Reg #4    */
#define VIC_VICR5	VIC_ADRS(0x05)	/* VME Interrupt Control Reg #5    */
#define VIC_VICR6	VIC_ADRS(0x06)	/* VME Interrupt Control Reg #6    */
#define VIC_VICR7	VIC_ADRS(0x07)	/* VME Interrupt Control Reg #7    */
#define VIC_DSICR	VIC_ADRS(0x08)	/* DMA Status Int Control Reg      */
#define VIC_LICR1	VIC_ADRS(0x09)	/* Local Interrupt Control Reg #1  */
#define VIC_LICR2	VIC_ADRS(0x0a)	/* Local Interrupt Control Reg #2  */
#define VIC_LICR3	VIC_ADRS(0x0b)	/* Local Interrupt Control Reg #3  */
#define VIC_LICR4	VIC_ADRS(0x0c)	/* Local Interrupt Control Reg #4  */
#define VIC_LICR5	VIC_ADRS(0x0d)	/* Local Interrupt Control Reg #5  */
#define VIC_LICR6	VIC_ADRS(0x0e)	/* Local Interrupt Control Reg #6  */
#define VIC_LICR7	VIC_ADRS(0x0f)	/* Local Interrupt Control Reg #7  */
#define VIC_ICGICR	VIC_ADRS(0x10)	/* ICGS Interrupt Control Reg      */
#define VIC_ICMICR	VIC_ADRS(0x11)	/* ICMS Interrupt Control Reg      */
#define VIC_EGICR	VIC_ADRS(0x12)	/* Error Group Int Control Reg     */
#define VIC_ICGIVBR	VIC_ADRS(0x13)	/* ICGS Interrupt Vector Base Reg  */
#define VIC_ICMIVBR	VIC_ADRS(0x14)	/* ICMS Interrupt Vector Base Reg  */
#define VIC_LIVBR	VIC_ADRS(0x15)	/* Local Int Vector Base Reg       */
#define VIC_EGIVBR	VIC_ADRS(0x16)	/* Error Group Int Vec Base Reg    */
#define VIC_ICSR	VIC_ADRS(0x17)	/* Interprocessor Comm Switch Reg  */
#define VIC_ICR0	VIC_ADRS(0x18)	/* Interprocessor Comm. Reg #0     */
#define VIC_ICR1	VIC_ADRS(0x19)	/* Interprocessor Comm. Reg #1     */
#define VIC_ICR2	VIC_ADRS(0x1a)	/* Interprocessor Comm. Reg #2     */
#define VIC_ICR3	VIC_ADRS(0x1b)	/* Interprocessor Comm. Reg #3     */
#define VIC_ICR4	VIC_ADRS(0x1c)	/* Interprocessor Comm. Reg #4     */
#define VIC_ICR5	VIC_ADRS(0x1d)	/* Interprocessor Comm. Reg #5     */
#define VIC_ICR6	VIC_ADRS(0x1e)	/* Interprocessor Comm. Reg #6     */
#define VIC_ICR7	VIC_ADRS(0x1f)	/* Interprocessor Comm. Reg #7     */
#define VIC_VIRSR	VIC_ADRS(0x20)	/* VME Interrupt Request/Stat. Reg */
#define VIC_VIVR1	VIC_ADRS(0x21)	/* VME Interrupt Vector Reg #1     */
#define VIC_VIVR2	VIC_ADRS(0x22)	/* VME Interrupt Vector Reg #2     */
#define VIC_VIVR3	VIC_ADRS(0x23)	/* VME Interrupt Vector Reg #3     */
#define VIC_VIVR4	VIC_ADRS(0x24)	/* VME Interrupt Vector Reg #4     */
#define VIC_VIVR5	VIC_ADRS(0x25)	/* VME Interrupt Vector Reg #5     */
#define VIC_VIVR6	VIC_ADRS(0x26)	/* VME Interrupt Vector Reg #6     */
#define VIC_VIVR7	VIC_ADRS(0x27)	/* VME Interrupt Vector Reg #7     */
#define VIC_TTR		VIC_ADRS(0x28)	/* Transfer Time-out Reg           */
#define VIC_LBTR	VIC_ADRS(0x29)	/* Local Bus Timing Reg            */
#define VIC_BTDR	VIC_ADRS(0x2a)	/* Block Transfer Definition Reg   */
#define VIC_ICR		VIC_ADRS(0x2b)	/* Interface Configuration Reg     */
#define VIC_ARCR	VIC_ADRS(0x2c)	/* Arbiter/Requester Config. Reg   */
#define VIC_AMSR	VIC_ADRS(0x2d)	/* AM Source Reg                   */
#define VIC_BESR	VIC_ADRS(0x2e)	/* Bus Error Status Reg            */
#define VIC_DSR		VIC_ADRS(0x2f)	/* DMA Status Reg                  */
#define VIC_SS0CR0	VIC_ADRS(0x30)	/* Slave Select 0/Control Reg #0   */
#define VIC_SS0CR1	VIC_ADRS(0x31)	/* Slave Select 0/Control Reg #1   */
#define VIC_SS1CR0	VIC_ADRS(0x32)	/* Slave Select 1/Control Reg #0   */
#define VIC_SS1CR1	VIC_ADRS(0x33)	/* Slave Select 1/Control Reg #1   */
#define VIC_RCR		VIC_ADRS(0x34)	/* Release Control Reg             */
#define VIC_BTCR	VIC_ADRS(0x35)	/* Block Transfer Control Reg      */
#define VIC_BTLR0	VIC_ADRS(0x36)	/* Block Transfer Length Reg #0    */
#define VIC_BTLR1	VIC_ADRS(0x37)	/* Block Transfer Length Reg #1    */
#define VIC_SRR		VIC_ADRS(0x38)	/* System Reset Reg                */

/* off-board access, register definitions */

#define	VME_ICF_REG_INTERVAL	2

#ifndef VME_ICF_ADRS	/* to permit alternative off-board addressing */
#define VME_ICF_ADRS(adrs, icf, type, reg) \
		(CAST (adrs + icf + (reg * VME_ICF_REG_INTERVAL) + type ))
#endif	/* VME_ICF_ADRS */

/* Interprocessor Communication Facility - icf */

#define VME_ICR		0x00	/* IC Registers       ICR0-7  */
#define VME_ICGS	0x10	/* IC Global Switches ICGS0-3 */
#define VME_ICMS	0x20	/* IC Module Switches ICMS0-3 */

/* Type of register access - type */

#define VME_ODD_ADRS	0x01	/* ICR always accessed at odd byte addresses */

#define VME_SET_ADRS	0x01	/* ICGS and ICMS set    switch access */
#define VME_CLR_ADRS	0x00	/* ICGS and ICMS clear  switch access */

#define	VME_ICR0(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,0)
#define	VME_ICR1(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,1)
#define	VME_ICR2(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,2)
#define	VME_ICR3(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,3)
#define	VME_ICR4(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,4)
#define	VME_ICR5(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,5)
#define	VME_ICR6(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,6)
#define	VME_ICR7(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,7)

#define	VME_ICGS0_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,0)
#define	VME_ICGS0_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,0)
#define	VME_ICGS1_SET(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,1)
#define	VME_ICGS1_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,1)
#define	VME_ICGS2_SET(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,2)
#define	VME_ICGS2_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,2)
#define	VME_ICGS3_SET(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,3)
#define	VME_ICGS3_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,3)

#define	VME_ICMS0_SET(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,0)
#define	VME_ICMS0_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,0)
#define	VME_ICMS1_SET(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,1)
#define	VME_ICMS1_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,1)
#define	VME_ICMS2_SET(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,2)
#define	VME_ICMS2_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,2)
#define	VME_ICMS3_SET(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,3)
#define	VME_ICMS3_CLR(baseAdrs)	VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,3)

/****************************************************************
* VIICR        0x00    0x03     VME Interrupter Irq Control Reg *
*****************************************************************/

#define	VIICR_IRQ_LVL_MASK	0x07	/* local interrupt level mask	7 */
#define	VIICR_IRQ_DISABLE	0x80	/* disable interrupter IRQ      7 */

/***************************************************************
* VICR1        0x01    0x07     VME Interrupt Control Reg #1   *
* to                                                           *
* VICR7        0x07    0x1f     VME Interrupt Control Reg #7   *
****************************************************************/

#define	VICR_IRQ_LVL_MASK	0x07	/* local interrupt level mask	7 */
#define	VICR_IRQ_DISABLE	0x80	/* disable interrupt IRQ	7 */

/***************************************************************
* DSICR        0x08    0x23     DMA Status Int Control Reg     *
****************************************************************/

#define	DSICR_IRQ_LVL_MASK	0x07	/* local interrupt level mask	7 */
#define	DSICR_IRQ_DISABLE	0x80	/* disable DMA termination IRQ	7 */

/***************************************************************
* LICR1        0x09    0x27     Local Interrupt Control Reg #1 *