m68681sio.h

IXP425的BSP代码

/* m68681Sio.h - Motorola M68681 serial chip header file */

/* Copyright 1984-1996 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,03jun96,dat	 added opcrCopy and oprCopy fields, new rtns
01a,08feb96,dds	 created.
*/

/*
This file contains constants for the Motorola M68681 serial chip.
The constants DUART_REG_OFFSET and SIO must defined when
including this header file.
*/

#ifndef __INCm68681Sioh
#define __INCm68681Sioh

#ifdef __cplusplus
extern "C" {
#endif

#ifndef	_ASMLANGUAGE

#include "sioLib.h"

/* device and channel structures */

/* 
 * The M68681_CHAN structure defines a serial I/O channel which
 * describes the baudrate, interrupt mode, control 
 * registers mode registers and the I/O port registers for a given channel. 
 * Also the various SIO driver functions ( ioctl, txStarup, callbackInstall,
 * pollInput, polloutput ) that this channel could utilize are declared 
 * here.
*/

typedef volatile UCHAR VCHAR;	/* shorthand for volatile UCHAR */

typedef struct m68681_chan	/* M68681_CHAN */
    {
    /* always goes first */
    SIO_CHAN	sio;		/* driver functions */
    
    struct m68681_duart *pDuart;/* pointer to the mc68681 DUART */

    /* callbacks */

    STATUS	(*getTxChar)();	/* pointer to a xmitr function */
    STATUS	(*putRcvChar)();/* pointer to a recvr function */
    void *	getTxArg;
    void *	putRcvArg;

    /* control and data register addresses for each channel */

    VCHAR *	mr;		/* mode register address */
    VCHAR *	sr;		/* status register address */
    VCHAR *	csr;		/* clock select  register address */
    VCHAR *	cr;		/* command register address */
    VCHAR *	rb;		/* receiver buffer address */
    VCHAR *	tb;		/* transmit buffer address */

    UCHAR	xmitEnb;	/* bit for transmit enable */
    UCHAR	rcvrEnb;	/* bit for transmit enable */
    UCHAR	rxBreak;	/* bit for enabling break interrupt */

    /* misc values */

    UINT	baudRate;	/* current baud rate */
    UINT	options;	/* current options, SIO_HW_OPTS_SET */

    /* interrupt/polled mode configuration info */

    UINT	mode;		/* SIO_MODE_[INT | POLL] */
    UCHAR       intVec;		/* interrupt vector address */
    UCHAR       intType;	/* type of vector to supply from M68681 */
    UINT	channel;	/* channel number (0 or 1) */
    } M68681_CHAN;

/* This structure defines that the m68681 has two channels */

typedef struct m68681_duart	/* M68681_DUART */
    {
    M68681_CHAN  portA;		/* port A device descriptor */
    M68681_CHAN  portB;		/* port B device descriptor */

    /* The registers defined below are common to both channels */

    VCHAR *	ipcr;		/* input port change register address */
    VCHAR *	acr;		/* auxilliary control register address */
    VCHAR *	isr;		/* interupt status register address */
    VCHAR *	imr;		/* interupt mask register address */
    VCHAR *	ip;		/* input port register address */
    VCHAR *	opcr;		/* output port config register address */
    VCHAR *	sopbc;		/* set output port register address */
    VCHAR *	ropbc;		/* reset output port register address */
    VCHAR *	ctroff;		/* Counter off */
    VCHAR *	ctron;		/* counter on  */
    VCHAR *	ctlr;		/* counter timer lower register  */
    VCHAR *	ctur;		/* counter timer upper register  */
    VCHAR *	ivr;		/* interupt vector register address */

    UCHAR 	imrCopy;	/* stores interrupt mask register value  */
    UINT	baudFreq;	/* baud clock frequency */
    UCHAR	acrCopy;	/* copy of acr */
    UCHAR	opcrCopy;	/* copy of opcr */
    UCHAR	oprCopy;	/* copy of opr */

    VOIDFUNCPTR	tickRtn;	/* Timer interrupt service routine */
    void *	tickArg;	/* pointer to the system clock */
    BOOL	intEnable;	/* allow interrupt mode flag */

    } M68681_DUART;

typedef struct m68681_clock	/* M68681_CLK */
    {
    M68681_DUART * pDuart;	/* pointer to the DUART */
    VOIDFUNCPTR	routine;	/* user routine */
    void *	arg;		/* arg for user routine */
    BOOL	running;	/* current status */
    UINT	rate;		/* interrupt rate, ticks per second */
    UINT	hertz;		/* oscillator input rate, hertz */
    UINT	min;		/* min rate */
    UINT	max;		/* max rate */
    UINT	preload;	/* counter/timer preload value */
    } M68681_CLK;


#if defined(__STDC__) || defined(__cplusplus)

/* serial procedures */
IMPORT	void	m68681DevInit	(M68681_DUART *);
IMPORT	void	m68681DevInit2	(M68681_DUART *);
IMPORT	void	m68681Int	(M68681_DUART *);
IMPORT	void	m68681ImrSetClr	(M68681_DUART *, UCHAR, UCHAR);
IMPORT	void	m68681AcrSetClr	(M68681_DUART *, UCHAR, UCHAR);
IMPORT	void	m68681OprSetClr	(M68681_DUART *, UCHAR, UCHAR);
IMPORT	void	m68681OpcrSetClr(M68681_DUART *, UCHAR, UCHAR);
IMPORT	UCHAR	m68681Imr	(M68681_DUART *);
IMPORT	UCHAR	m68681Acr	(M68681_DUART *);
IMPORT	UCHAR	m68681Opcr	(M68681_DUART *);
IMPORT	UCHAR	m68681Opr	(M68681_DUART *);

/* clock procedures */
IMPORT	STATUS	m68681ClkInit	(M68681_CLK *, M68681_DUART *);
IMPORT	void	m68681ClkInt	(M68681_CLK *);
IMPORT	STATUS	m68681ClkConnect(M68681_CLK *, VOIDFUNCPTR, void *);
IMPORT	void	m68681ClkEnable (M68681_CLK *);
IMPORT	void	m68681ClkDisable(M68681_CLK *); 
IMPORT	int	m68681ClkRateGet(M68681_CLK *);
IMPORT	STATUS	m68681ClkRateSet(M68681_CLK *, int);
IMPORT	int	m68681ClkReadOnFly(M68681_CLK *);

#else   /* __STDC__ */

IMPORT	void	m68681DevInit	();
IMPORT	void	m68681DevInit2	();
IMPORT	void	m68681Int	();
IMPORT	void	m68681ImrSetClr	();
IMPORT	void	m68681AcrSetClr	();

IMPORT	STATUS	m68681ClkInit	();
IMPORT	void	m68681ClkInt	();
IMPORT	STATUS	m68681ClkConnect();
IMPORT	void	m68681ClkEnable ();
IMPORT	void	m68681ClkDisable(); 
IMPORT	int	m68681ClkRateGet();
IMPORT	STATUS	m68681ClkRateSet();
IMPORT	int	m68681ClkReadOnFly();

#endif  /* __STDC__ */

#endif	/* _ASMLANGUAGE */

/* channels */

#define M68681_CHANNEL_A   0
#define M68681_CHANNEL_B   1


#define M68681_N_CHANS    2	/* number of serial channels on chip */

#ifdef	_ASMLANGUAGE
#   define M681_ADRS(reg)	(M68681_BASE + (reg * M68681_REG_OFFSET))
#else
#   define M681_ADRS(reg)	((VCHAR *)M68681_BASE+(reg*M68681_REG_OFFSET))
#endif	/* _ASMLANGUAGE */

/* SIO -- m68681 serial channel chip -- register definitions */

#define M68681_MRA	M681_ADRS(0x00)	/* R/W: mode reg. A */
#define M68681_SRA	M681_ADRS(0x01)	/* R: status reg. A */
#define M68681_CSRA	M681_ADRS(0x01)	/* W: clock select reg. A */
#define M68681_CRA	M681_ADRS(0x02)	/* W: command reg. A */
#define M68681_RHRA	M681_ADRS(0x03)	/* R: receive buffer A */
#define M68681_THRA	M681_ADRS(0x03)	/* W: transmit buffer A */