cd2400sio.h

IXP425的BSP代码

/* cd2400.h - Cirrus Logic CD2400 serial chip header */

/* Copyright 1991-1997 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,29sep98,fle  doc : made it refgen parsable
01c,04mar97,dat  SPR 7767, added #ifdef _ASMLANGUAGE
01b,15jun95,ms	 updated for new driver.
01a,06mar95,myz  written (from cd2400Serial.h).
*/

/*
*/

#ifndef __INCcd2400Sioh
#define __INCcd2400Sioh

#ifdef __cplusplus
extern "C" {
#endif

#define N_CHANNELS    4			/* number of serial channels on chip */

#ifndef	_ASMLANGUAGE

/* channel descriptors */

typedef struct
    {
    /* always goes first */

    SIO_DRV_FUNCS *     pDrvFuncs;      /* driver functions */

    /* callbacks */

    STATUS      (*getTxChar) ();
    STATUS      (*putRcvChar) ();
    void *      getTxArg;
    void *      putRcvArg;

    BOOL        created;
    UINT16      int_vec;        /* channel interrupt vector base */
    UINT16      chan_num;       /* the channel number of this device */
    UINT16      channelMode;
    void        (*intEnDisable)(int mode);
    struct CD2400_QUSART * pQusart;
    } CD2400_CHAN;

/* cd2400 chip descriptor */

typedef struct CD2400_QUSART
    {
    CD2400_CHAN  channel[N_CHANNELS];
    UINT16      numChannels;
    char *	baseAdrs;		/* the base address of the device */
    UINT16      regSpacing;
    INT16       devMode;		/* only one channel in polling mode */
    int		baudClkFreq;
    BOOL	(*rxReady) (struct CD2400_QUSART *);
    BOOL	(*txReady) (struct CD2400_QUSART *);
    } CD2400_QUSART;

/* on-board access, register definitions */

#undef  MPCC_ADRS
#define MPCC_ADRS(reg) (pQusart->baseAdrs + (reg * pQusart->regSpacing))

/* MPCC -- cd2400 serial channel chip -- register definitions
 * Defined in this order which is the order of defined in
 * the CIRRUS LOGIC document
 */

/* GLOBAL REGISTERS */
#define	MPCC_GFRCR	MPCC_ADRS(0x81)	/* Global Firmware Rev Code Register */
#define	MPCC_TFTC	MPCC_ADRS(0x80)	/* Transmit FIFO Transfer Count */
#define	MPCC_MEOIR	MPCC_ADRS(0x86)	/* Modem End of Interrupt Register */
#define	MPCC_TEOIR	MPCC_ADRS(0x85)	/* Transmit End of Interrupt Register */
#define	MPCC_REOIR	MPCC_ADRS(0x84)	/* Receive End of Interrupt Register */
#define	MPCC_MISR	MPCC_ADRS(0x8b)	/* Modem (/Timer) Interrupt Status Re */
#define	MPCC_TISR	MPCC_ADRS(0x8a)	/* Transmit Interrupt Status Register */
#define	MPCC_RISR	MPCC_ADRS(0x88)	/* Receive Interrupt Stat Reg (WORD) */
#define	MPCC_RISRL	MPCC_ADRS(0x89)	/* Receive Interrupt Stat Reg Low */
#define	MPCC_RISRH	MPCC_ADRS(0x88)	/* Receive Interrupt Stat Reg High */
#define	MPCC_MIR	MPCC_ADRS(0xef)	/* Modem Interrupt Register */
#define	MPCC_TIR	MPCC_ADRS(0xec)	/* Transmit Interrupt Register */
#define	MPCC_RIR	MPCC_ADRS(0xed)	/* Receive Interrupt Register */
#define	MPCC_STK	MPCC_ADRS(0xe2)	/* Stack Register */
#define	MPCC_TPR	MPCC_ADRS(0xda)	/* Timer Period Register */
#define	MPCC_PILR1	MPCC_ADRS(0xe3)	/* Priority Interrupt Level Reg 1 */
#define	MPCC_PILR2	MPCC_ADRS(0xe0)	/* Priority Interrupt Level Reg 2 */
#define	MPCC_PILR3	MPCC_ADRS(0xe1)	/* Priority Interrupt Level Reg 3 */
#define	MPCC_CAR	MPCC_ADRS(0xee)	/* Channel Access Register */
#define	MPCC_RDR	MPCC_ADRS(0xf8)	/* Receive Data Register */
#define	MPCC_TDR	MPCC_ADRS(0xf8)	/* Transmit Data Register */
#define	MPCC_DMR	MPCC_ADRS(0xf6)	/* DMA Mode Register */

/* Per-Channel Registers */

#define	MPCC_LICR	MPCC_ADRS(0x26)	/* Local Interrupting Channel Reg */
#define	MPCC_LIVR	MPCC_ADRS(0x09)	/* Local Interrupt Vector Register */
#define	MPCC_CCR	MPCC_ADRS(0x13)	/* Channel Command Register */
#define MPCC_STCR	MPCC_ADRS(0x12)	/* Special Transmit Command Register */
#define	MPCC_IER	MPCC_ADRS(0x11)	/* Interrupt Enable Register */
#define	MPCC_COR1	MPCC_ADRS(0x10)	/* Channel Option Register 1 */
#define	MPCC_COR2	MPCC_ADRS(0x17)	/* Channel Option Register 2 */
#define	MPCC_COR3	MPCC_ADRS(0x16)	/* Channel Option Register 3 */
#define	MPCC_COR4	MPCC_ADRS(0x15)	/* Channel Option Register 4 */
#define	MPCC_COR5	MPCC_ADRS(0x14)	/* Channel Option Register 5 */
#define	MPCC_COR6	MPCC_ADRS(0x18)	/* Channel Option Register 6 */
#define	MPCC_COR7	MPCC_ADRS(0x07)	/* Channel Option Register 7 */
#define	MPCC_CMR	MPCC_ADRS(0x1b)	/* Channel Mode Register */
#define	MPCC_CSR	MPCC_ADRS(0x1a)	/* Channel Status Reg (Sync Modes) */
#define	MPCC_DMABSTS	MPCC_ADRS(0x19)	/* DMA Buffer Status */
#define	MPCC_LNXT	MPCC_ADRS(0x2e)	/* LNext Character */
#define	MPCC_SCHR1	MPCC_ADRS(0x1f)	/* Special Character Register 1 */
#define	MPCC_RFAR1	MPCC_ADRS(0x1f)	/* Receive Frame Address Register 1 */
#define	MPCC_SCHR2	MPCC_ADRS(0x1e)	/* Special Character Register 2 */
#define	MPCC_RFAR2	MPCC_ADRS(0x1e)	/* Receive Frame Address Register 2 */
#define	MPCC_SCHR3	MPCC_ADRS(0x1d)	/* Special Character Register 3 */
#define MPCC_RFAR3	MPCC_ADRS(0x1d)	/* Receive Frame Address Register 3 */
#define	MPCC_SCHR4	MPCC_ADRS(0x1c)	/* Special Character Register 4 */
#define	MPCC_RFAR4	MPCC_ADRS(0x1c)	/* Receive Frame Address Register 4 */
#define	MPCC_SCRL	MPCC_ADRS(0x23) /* Special Character Range Low */
#define	MPCC_SCRH	MPCC_ADRS(0x22)	/* Special Character Range High */
#define	MPCC_RTPR	MPCC_ADRS(0x24)	/* Receive Timeout Period Register */
#define	MPCC_RTPRL	MPCC_ADRS(0x25)	/* Receive Timeout Period Reg Low */
#define	MPCC_RTPRH	MPCC_ADRS(0x24)	/* Receive Timeout Period Reg High */
#define	MPCC_GT1	MPCC_ADRS(0x2a)	/* General Timer 1 */
#define	MPCC_GT1L	MPCC_ADRS(0x2b)	/* General Timer 1 Low */
#define	MPCC_GT1H	MPCC_ADRS(0x2a)	/* General Timer 1 High */
#define	MPCC_GT2	MPCC_ADRS(0x29)	/* General Timer 2 */
#define	MPCC_TTR	MPCC_ADRS(0x29)	/* Transmit Timer Register */
#define	MPCC_RFOC	MPCC_ADRS(0x30)	/* Receive FIFO Output Count */
#define	MPCC_TCBADRL	MPCC_ADRS(0x3a)	/* Transmit Current Buffer Addr Lower */
#define	MPCC_TCBADRH	MPCC_ADRS(0x38)	/* Transmit Current Buffer Addr Upper */
#define	MPCC_RCBADRL	MPCC_ADRS(0x3e)	/* Receive Current Buffer Addr Lower */
#define	MPCC_RCBADRH	MPCC_ADRS(0x3c)	/* Receive Current Buffer Addr Upper */
#define	MPCC_ARBADRL	MPCC_ADRS(0x42)	/* A Receive Buffer Address Lower */
#define MPCC_ARBADRU	MPCC_ADRS(0x40)	/* A Receive Buffer Address Upper */
#define	MPCC_BRBADRL	MPCC_ADRS(0x46)	/* B Receive Buffer Address Lower */
#define	MPCC_BRBADRU	MPCC_ADRS(0x44)	/* B Receive Buffer Address Upper */
#define	MPCC_ARBCNT	MPCC_ADRS(0x4a)	/* A Receive Buffer Count */
#define	MPCC_BRBCNT	MPCC_ADRS(0x48)	/* B Receive Buffer Count */
#define	MPCC_ARBSTS	MPCC_ADRS(0x4f)	/* A Receive Buffer Status */
#define	MPCC_BRBSTS	MPCC_ADRS(0x4e)	/* B Receive Buffer Status */
#define	MPCC_ATBADRL	MPCC_ADRS(0x52)	/* A Transmit Buffer Address Lower */
#define	MPCC_ATBADRU	MPCC_ADRS(0x50)	/* B Transmit Buffer Address Upper */
#define	MPCC_BTBADRL	MPCC_ADRS(0x56)	/* B Transmit Buffer Address Lower */
#define	MPCC_BTBADRU	MPCC_ADRS(0x54)	/* B Transmit Buffer Address Upper */
#define	MPCC_ATBCNT	MPCC_ADRS(0x5a)	/* A Buffer Transmit Byte Count */
#define	MPCC_BTBCNT	MPCC_ADRS(0x58)	/* B Buffer Transmit Byte Count */
#define	MPCC_ATBSTS	MPCC_ADRS(0x5f)	/* A Transmit Buffer Status */
#define	MPCC_BTBSTS	MPCC_ADRS(0x5e)	/* B Transmit Buffer Status */
#define	MPCC_MSVRRTS	MPCC_ADRS(0xde)	/* Modem Signal Value Register - RTS */
#define MPCC_MSVRDTR	MPCC_ADRS(0xdf)	/* Modem Signal Value Register - DTR */
#define	MPCC_TBPR	MPCC_ADRS(0xc3)	/* Transmit Baud Rate Period Register */
#define	MPCC_TCOR	MPCC_ADRS(0xc0)	/* Transmit Clock Option Register */
#define	MPCC_RBPR	MPCC_ADRS(0xcb)	/* Receive Baud Rate Period Register */
#define	MPCC_RCOR	MPCC_ADRS(0xc8)	/* Receive Clock Option Register */
#define	MPCC_CPSR	MPCC_ADRS(0xd6)	/* CRC Polynomial Select Register */

/* Now let's define some register bit values */

/* MEOIR		0x86		Modem End of Interrupt Register    */
/* TEOIR		0x85		Transmit End of Interrupt Register */
/* REOIR		0x84		Receive End of Interrupt Register  */
#define	EOIR_SET_TIMER_2	0x20	/* load MISR to timer 2 */
#define	EOIR_SET_TIMER_1	0x10	/* load MISR to timer 1 */
#define	EOIR_TERMINATE_BUF	0x80	/* 1=Terminate buffer in DMA Mode */
#define	EOIR_END_OF_FRAME	0x40	/* 0 = no, 1 = yes */
#define	EOIR_NO_TRANSFER	0x08	/* no data transferred */
#define EOIR_DIS_EXCEP_CHAR	0x40	/* 0 = no, 1 = yes */
#define	EOIR_TRANSFER		0x00	/* data was transferred */

/* MISR		0x8b		Modem (/Timer) Interrupt Status Register */
#define	MISR_DSR_CHANGED	0x80	/* 0 = no, 1 = yes */
#define	MISR_CD_CHANGED		0x40	/* 0 = no, 1 = yes */
#define	MISR_CTS_CHANGED	0x20	/* 0 = no, 1 = yes */
#define	MISR_TIMER2_TIMEOUT	0x02	/* 0 = no, 1 = yes */
#define MISR_TIMER1_TIMEOUT	0x01	/* 0 = no, 1 = yes */

/* TISR		0x8a		Transmit Interrupt Status Register          */
#define	TISR_TRANS_BERR		0x80	/* 0 = no, 1 = yes (Bus error) */
#define	TISR_TRANS_EOF		0x40	/* 0 = no, 1 = yes (End Of Frame) */
#define	TISR_TRANS_EOB		0x20	/* 0 = no, 1 = yes (End Of trans Buf) */
#define	TISR_TRANS_UNDERRUN	0x10	/* 0 = no, 1 = yes */
#define	TISR_TRANS_A_OR_B	0x08	/* 0 = Buffer A, 1 = Buffer B */
#define	TISR_TX_EMPTY		0x02	/* 0 = no, 1 = yes (idle condition) */
#define	TISR_TX_DATA		0x01	/* 0 = no, 1 = yes (below threshold) */

/* RISR		0x88		Receive Interrupt Status Register       */
/* RISRL	0x89		Receive Interrupt Status Register Low   */
/* HDLC Mode */
#define	RISR_REC_EOF		0x40	/* 0 = no, 1 = yes */
#define	RISR_REC_ABORT		0x20	/* 0 = no, 1 = yes (term frame) */
#define	RISR_REC_CRC		0x10	/* 0 = no, 1 = yes (CRC error frame) */
#define	RISR_REC_OVERRUN	0x08	/* 0 = no, 1 = yes (Overrun occured) */
#define	RISR_REC_RESIDUAL	0x04	/* 0 = no, 1 = yes (char was partial */
#define	RISR_REC_CLEAR_DCT	0x01	/* 0 = no, 1 = yes (X.21 Clr signal) */
/* Asynchronous Mode */
#define	RISR_REC_TIMEOUT	0x80	/* 0 = no, 1 = yes (No char rec'd) */
#define	RISR_REC_PARITY_ERR	0x04	/* 0 = no, 1 = yes (Parity error) */
#define	RISR_REC_FRAME_ERR	0x02	/* 0 = no, 1 = yes (Frame error) */
#define RISR_REC_BREAK		0x01	/* 0 = no, 1 = yes (Break detected) */

/* RISRH	0x88		Receive Interrupt Status Register High */
#define	RISR_REC_BERR		0x80	/* 0 = no, 1 = yes (Bus error) */
#define	RISR_REC_EOB		0x20	/* 0 = no, 1 = yes (End Of Buffer) */
#define	RISR_REC_A_OR_B		0x08	/* 0 = Buffer A, 1 = Buffer B */

/* MIR		0xef		Modem Interrupt Register 	*/
#define	MIR_MODEM_ENABLE	0x80	/* 0 = no, 1 = yes (Modem inter) */
#define	MIR_MODEM_ACTIVE	0x40	/* 0 = no, 1 = yes (Modem Active) */
#define	MIR_MODEM_EOI		0x20	/* 0 = no, 1 = yes (Modem End Of Int) */

/* TIR		0xec		Transmit Interrupt Register 	*/
#define	TIR_TRANS_ENABLE	0x80	/* 0 = no, 1 = yes (Trans inter) */
#define	TIR_TRANS_ACTIVE	0x40	/* 0 = no, 1 = yes (Trans Active) */
#define	TIR_TRANS_EOI		0x20	/* 0 = no, 1 = yes (Trans End of Int) */

/* RIR		0xed		Receive Interrupt Register 	*/
#define	RIR_REC_ENABLE		0x80	/* 0 = no, 1 = yes (Rec inter) */
#define	RIR_REC_ACTIVE		0x40	/* 0 = no, 1 = yes (Rec Active) */
#define	RIR_REC_EOI		0x20	/* 0 = no, 1 = yes (Rec End of Int) */