mmuarmlib.h

IXP425的BSP代码

 * currently generates unaligned accesses in its code, and switching this
 * on will cause immediate faults. So, do not put it into the enable
 * mask.
 *
 * We used to clear all the Reserved/Should Be Zero bits when the
 * MMU/MPU was enabled, by including one bits for them in the definition
 * of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
 * the definitions of the bits within the MMU Control Register. The MMU
 * Control register is initialised within romInit()/sysInit(), as the BSP
 * is the only place where the particular details of the CPU/MMU are
 * actually known. In general, it will be appropriate for the BSP to
 * initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
 * MMU is enabled, we will only change the bits we are particularly
 * concerned about, by using a Read-Modify-Write strategy.
 */

#if (ARMMMU == ARMMMU_810)
#define MMU_ENABLE_MASK  (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM | \
			  MMUCR_Z_ENABLE)
#else
#define MMU_ENABLE_MASK  (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
#endif /* (ARMMMU == ARMMMU_810) */

#if 0
#if ((ARMMMU == ARMMMU_940T) || (ARMMMU == ARMMMU_920T))
/*
 * When enabling the 940T/920T, we should not alter the clocking mode that
 * has been selected earlier (by the BSP).
 */

#define MMU_ENABLE_MASK  (0x3FFFE000 | \
			MMUCR_M_ENABLE | \
			MMUCR_SYSTEM | MMUCR_ROM | MMUCR_F | MMUCR_Z_ENABLE)
#else
#define MMU_ENABLE_MASK  (0xFFFFE000 | \
			MMUCR_M_ENABLE | \
			MMUCR_SYSTEM | MMUCR_ROM | MMUCR_F | MMUCR_Z_ENABLE)
#endif /* (ARMMMU == ARMMMU_940T/920T) */
#endif /* <<< 0 */

#if ((ARMMMU == ARMMMU_710A) || (ARMMMU == ARMMMU_720T) || \
     (ARMMMU == ARMMMU_920T))
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_ROM)
#endif

#if (ARMMMU == ARMMMU_810)
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_ROM )
#endif

#if ((ARMMMU == ARMMMU_SA110) || (ARMMMU == ARMMMU_SA1100) || \
     (ARMMMU == ARMMMU_SA1500) || (ARMMMU == ARMMMU_XSCALE))
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_ROM)
#endif

#if ((ARMMMU == ARMMMU_940T) || (ARMMMU == ARMMMU_740T) || \
     (ARMMMU == ARMMMU_946E))
#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE)
#endif


/*
 * Values to be used when the MMU Control Register is initialised from
 * within romInit.s or sysALib.s (before the MMU is enabled). Note that
 * on 710A, this is also used to initialise the soft-copy of the MMU CR
 * that we need to keep (in order to emulate Read-Modify-Write
 * operations). So, 710A BSPs *MUST* initialise the MMU CR with the value
 * contained here, or else trouble will ensue. This restriction does
 * not apply to non-710A BSPs, but caution must be exercised in choosing a
 * value different to that defined here.
 */

#if (_BYTE_ORDER == _LITTLE_ENDIAN)

/* little-endian */

#if ((ARMMMU == ARMMMU_710A) || (ARMMMU == ARMMMU_720T))
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_ROM)
#endif

#if (ARMMMU == ARMMMU_810)
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_ROM)
#endif

#if ((ARMMMU == ARMMMU_SA110) || (ARMMMU == ARMMMU_SA1100) || \
     (ARMMMU == ARMMMU_SA1500) || (ARMMMU == ARMMMU_XSCALE))
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_ROM)
#endif

#if ((ARMMMU == ARMMMU_940T) || (ARMMMU == ARMMMU_946E))
/* W bit is Should Be One */

#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_W_ENABLE)
#endif

#if (ARMMMU == ARMMMU_740T)
#define MMU_INIT_VALUE	0
#endif

#if (ARMMMU == ARMMMU_920T)
/* W bit is Should Be One */

#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_ROM | MMUCR_W_ENABLE)
#endif

#else	/* (_BYTE_ORDER == _LITTLE_ENDIAN) */

/* big-endian */

#if ((ARMMMU == ARMMMU_710A) || (ARMMMU == ARMMMU_720T))
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_BIGEND | MMUCR_ROM)
#endif

#if (ARMMMU == ARMMMU_810)
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_BIGEND | MMUCR_ROM)
#endif

#if ((ARMMMU == ARMMMU_SA110) || (ARMMMU == ARMMMU_SA1100) || \
     (ARMMMU == ARMMMU_SA1500) || (ARMMMU == ARMMMU_XSCALE))
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_BIGEND | MMUCR_ROM)
#endif

#if ((ARMMMU == ARMMMU_940T) || (ARMMMU == ARMMMU_946E))
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_BIGEND | MMUCR_W_ENABLE)
#endif

#if (ARMMMU == ARMMMU_740T)
#define MMU_INIT_VALUE	MMUCR_BIGEND	
#endif

#if (ARMMMU == ARMMMU_920T)
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
			MMUCR_W_ENABLE | MMUCR_BIGEND | MMUCR_ROM)
#endif

#endif	/* _BYTE_ORDER == _LITTLE_ENDIAN */


#if (ARMMMU == ARMMMU_810)

/*
 * Definitions for register 15 of the MMU coprocessor (clock and test
 * configuration).
 */

#define MMUCTR_D 	(1<<0)	/* Enable Dynamic Clock switching */
#define MMUCTR_S 	(1<<1)	/* Enable Synchronous clock switching */
#define MMUCTR_F_BUS	(0<<2)	/* Fast clock source: ... bus clock */
#define MMUCTR_F_REF	(1<<2)	/* ... REFCLK */
#define MMUCTR_F_PLL	(3<<2)	/* ... PLL output clock */

#endif /* (ARMMMU == ARMMMU_810) */

#ifndef	_ASMLANGUAGE

#if (!ARM_HAS_MPU)

#if (_BYTE_ORDER == _LITTLE_ENDIAN)

/* little-endian */

typedef struct
    {
    UINT type	: 2;		/* descriptor type, 1 => page */
    UINT pad1	: 2;		/* SBZ */
    UINT pad2	: 1;		/* SBO */
    UINT domain	: 4;		/* domain number */
    UINT pad3	: 1;		/* SBZ */
    UINT addr	: 22;		/* base address of page table */
    } PAGE_DESC_FIELD;


/* Layout of Page Table Entries (PTEs), actually small page descriptors */

typedef struct
    {
#if (CPU==XSCALE)
    UINT type	: 2;		/* page type, 3 => extended small page */
    UINT cb	: 2;		/* cacheable/bufferable bits */
    UINT ap	: 2;		/* access permission */
    UINT tex 	: 4;		/* type extension field */
    UINT sbz	: 2;		/* should be zero */
    UINT addr	: 20;		/* page base address */
#else
    UINT type	: 2;		/* page type, 2 => small page */
    UINT cb	: 2;		/* cacheable/bufferable bits */
    UINT ap0	: 2;		/* access permission, sub-page 0 */
    UINT ap1	: 2;		/* access permission, sub-page 1 */
    UINT ap2	: 2;		/* access permission, sub-page 2 */
    UINT ap3	: 2;		/* access permission, sub-page 3 */
    UINT addr	: 20;		/* page base address */
#endif /* if CPU=XSCALE */
    } PTE_FIELD;

#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */

/* big-endian */

typedef struct
    {
    UINT addr	: 22;		/* descriptor type, 1 => page */
    UINT pad3	: 1;		/* SBZ */
    UINT domain	: 4;		/* domain number */
    UINT pad2	: 1;		/* SBO */
    UINT pad1	: 2;		/* SBZ */
    UINT type	: 2;		/* base address of page table */
    } PAGE_DESC_FIELD;

/* Layout of Page Table Entries (PTEs), actually small page descriptors */

typedef struct
    {
#if (CPU==XSCALE)
    UINT addr	: 20;		/* page base address */
    UINT sbz	: 2;		/* should be zero */
    UINT tex 	: 4;		/* type extension field */
    UINT ap	: 2;		/* access permission */
    UINT cb	: 2;		/* cacheable/bufferable bits */
    UINT type	: 2;		/* page type, 3 => extended small page */
#else
    UINT addr	: 20;		/* page base address */
    UINT ap3	: 2;		/* access permission, sub-page 3 */
    UINT ap2	: 2;		/* access permission, sub-page 2 */
    UINT ap1	: 2;		/* access permission, sub-page 1 */
    UINT ap0	: 2;		/* access permission, sub-page 0 */
    UINT cb	: 2;		/* cacheable/bufferable bits */
    UINT type	: 2;		/* page type, 2 => small page */
#endif /* if CPU=XSCALE */
    } PTE_FIELD;

#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */

typedef union
    {
    PAGE_DESC_FIELD fields;
    UINT32 bits;
    } LEVEL_1_DESC;

typedef union
    {
    PTE_FIELD fields;
    UINT32 bits;
    } PTE;

typedef struct mmuTransTblStruct
    {
    LEVEL_1_DESC *pLevel1Table;
    } MMU_TRANS_TBL;

#else /* (!ARM_HAS_MPU) */

#define MPU_NUM_REGIONS 8

#if (_BYTE_ORDER == _LITTLE_ENDIAN)
typedef struct
    {
    UINT enable : 1;		/* 1 => region enabled */
    UINT size	: 5;		/* size  */
    UINT pad	: 6;		/* padding */
    UINT base	: 20;		/* region base address */
    } MPU_REGION_FIELDS;
#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
/* Big-Endian */

typedef struct
    {
    UINT base	: 20;		/* region base address */
    UINT pad	: 6;		/* padding */
    UINT size	: 5;		/* size  */
    UINT enable : 1;		/* 1 => region enabled */
    } MPU_REGION_FIELDS;
#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */

typedef union
    {
    MPU_REGION_FIELDS fields;
    UINT32 bits;
    } MPU_REGION_REG;

typedef struct mmuTransTblStruct
    {
    MPU_REGION_REG regs[MPU_NUM_REGIONS];
    } MMU_TRANS_TBL;

#endif /* (!ARM_HAS_MPU) */


/* Externally visible mmuLib, mmuMapLib and mmuALib2 routines */

IMPORT UINT32 mmuReadId (void);
IMPORT void * mmuVirtToPhys (void * addr);
IMPORT void * mmuPhysToVirt (void * addr);

IMPORT UINT32	(* mmuCrGet) (void);
IMPORT void	(* mmuModifyCr) (UINT32 value, UINT32 mask);
IMPORT UINT32	mmuHardCrGet (void);
IMPORT UINT32	mmuSoftCrGet (void);
IMPORT void	mmuModifyHardCr (UINT32 value, UINT32 mask);
IMPORT void	mmuModifySoftCr (UINT32 value, UINT32 mask);

#if	(ARMMMU == ARMMMU_710A)
#include "mmuArm710aLib.h"
#elif	(ARMMMU == ARMMMU_720T)
#include "mmuArm720tLib.h"
#elif	(ARMMMU == ARMMMU_740T)
#include "mmuArm740tLib.h"
#elif	(ARMMMU == ARMMMU_810)
#include "mmuArm810Lib.h"
#elif	(ARMMMU == ARMMMU_SA110)
#include "mmuArmSA110Lib.h"
#elif	(ARMMMU == ARMMMU_SA1100)
#include "mmuArmSA1100Lib.h"
#elif	(ARMMMU == ARMMMU_SA1500)
#include "mmuArmSA1500Lib.h"
#elif	(ARMMMU == ARMMMU_920T)
#include "mmuArm920tLib.h"
#elif	(ARMMMU == ARMMMU_940T)
#include "mmuArm940tLib.h"
#elif	(ARMMMU == ARMMMU_946E)
#include "mmuArm946eLib.h"
#elif	(ARMMMU == ARMMMU_XSCALE)
#include "mmuArmXSCALELib.h"
#endif	/* ARMMMU == ARMMMU_710A */


#if (!ARM_HAS_MPU)

/*
 * Pointer to a function that can be filled in by the BSP to point to a
 * function that returns a memory partition id for an area of memory to store
 * the Level 1 and Level 2 page tables. This area must be big enough for all
 * use. No provision is made to use that memory and then continue using
 * system memory once that has been filled.
 * N.B. at the time of writing, this feature has NEVER been tested at all.
 */

IMPORT PART_ID (* _func_armPageSource) (void);

#endif /* (!ARM_HAS_MPU) */

#endif	/* _ASMLANGUAGE */

#endif /* (ARMMMU != ARMMMU_NONE) */

#ifdef __cplusplus
}
#endif

#endif	/* __INCmmuArmLibh */