dsmsimsolarislib.h

IXP425的BSP代码

#define	RS2_o5		0x0000000D	/* source register 2: %o5 */
#define	RS2_o4		0x0000000C	/* source register 2: %o4 */
#define	RS2_o3		0x0000000B	/* source register 2: %o3 */
#define	RS2_o2		0x0000000A	/* source register 2: %o2 */
#define	RS2_o1		0x00000009	/* source register 2: %o1 */
#define	RS2_o0		0x00000008	/* source register 2: %o0 */
#define	RS2_g7		0x00000007	/* source register 2: %g7 */
#define	RS2_g6		0x00000006	/* source register 2: %g6 */
#define	RS2_g5		0x00000005	/* source register 2: %g5 */
#define	RS2_g4		0x00000004	/* source register 2: %g4 */
#define	RS2_g3		0x00000003	/* source register 2: %g3 */
#define	RS2_g2		0x00000002	/* source register 2: %g2 */
#define	RS2_g1		0x00000001	/* source register 2: %g1 */
#define	RS2_g0		0x00000000	/* source register 2: %g0 */

/* instruction fields: floating point unit register equates */

#define	RD_f31		0x3E000000	/* destination register: %f31 */
#define	RD_f30		0x3C000000	/* destination register: %f30 */
#define	RD_f29		0x3A000000	/* destination register: %f29 */
#define	RD_f28		0x38000000	/* destination register: %f28 */
#define	RD_f27		0x36000000	/* destination register: %f27 */
#define	RD_f26		0x34000000	/* destination register: %f26 */
#define	RD_f25		0x32000000	/* destination register: %f25 */
#define	RD_f24		0x30000000	/* destination register: %f24 */
#define	RD_f23		0x2E000000	/* destination register: %f23 */
#define	RD_f22		0x2C000000	/* destination register: %f22 */
#define	RD_f21		0x2A000000	/* destination register: %f21 */
#define	RD_f20		0x28000000	/* destination register: %f20 */
#define	RD_f19		0x26000000	/* destination register: %f19 */
#define	RD_f18		0x24000000	/* destination register: %f18 */
#define	RD_f17		0x22000000	/* destination register: %f17 */
#define	RD_f16		0x20000000	/* destination register: %f16 */
#define	RD_f15		0x1E000000	/* destination register: %f15 */
#define	RD_f14		0x1C000000	/* destination register: %f14 */
#define	RD_f13		0x1A000000	/* destination register: %f13 */
#define	RD_f12		0x18000000	/* destination register: %f12 */
#define	RD_f11		0x16000000	/* destination register: %f11 */
#define	RD_f10		0x14000000	/* destination register: %f10 */
#define	RD_f09		0x12000000	/* destination register: %f09 */
#define	RD_f08		0x10000000	/* destination register: %f08 */
#define	RD_f07		0x0E000000	/* destination register: %f07 */
#define	RD_f06		0x0C000000	/* destination register: %f06 */
#define	RD_f05		0x0A000000	/* destination register: %f05 */
#define	RD_f04		0x08000000	/* destination register: %f04 */
#define	RD_f03		0x06000000	/* destination register: %f03 */
#define	RD_f02		0x04000000	/* destination register: %f02 */
#define	RD_f01		0x02000000	/* destination register: %f01 */
#define	RD_f00		0x00000000	/* destination register: %f00 */
#define	RS1_f31		0x0007C000	/* source register 1: %f31 */
#define	RS1_f30		0x00078000	/* source register 1: %f30 */
#define	RS1_f29		0x00074000	/* source register 1: %f29 */
#define	RS1_f28		0x00060000	/* source register 1: %f28 */
#define	RS1_f27		0x0006C000	/* source register 1: %f27 */
#define	RS1_f26		0x00068000	/* source register 1: %f26 */
#define	RS1_f25		0x00064000	/* source register 1: %f25 */
#define	RS1_f24		0x00060000	/* source register 1: %f24 */
#define	RS1_f23		0x0005C000	/* source register 1: %f23 */
#define	RS1_f22		0x00058000	/* source register 1: %f22 */
#define	RS1_f21		0x00054000	/* source register 1: %f21 */
#define	RS1_f20		0x00050000	/* source register 1: %f20 */
#define	RS1_f19		0x0004C000	/* source register 1: %f19 */
#define	RS1_f18		0x00048000	/* source register 1: %f18 */
#define	RS1_f17		0x00044000	/* source register 1: %f17 */
#define	RS1_f16		0x00040000	/* source register 1: %f16 */
#define	RS1_f15		0x0003C000	/* source register 1: %f15 */
#define	RS1_f14		0x00038000	/* source register 1: %f14 */
#define	RS1_f13		0x00034000	/* source register 1: %f13 */
#define	RS1_f12		0x00030000	/* source register 1: %f12 */
#define	RS1_f11		0x0002C000	/* source register 1: %f11 */
#define	RS1_f10		0x00028000	/* source register 1: %f10 */
#define	RS1_f09		0x00024000	/* source register 1: %f09 */
#define	RS1_f08		0x00020000	/* source register 1: %f08 */
#define	RS1_f07		0x0001C000	/* source register 1: %f07 */
#define	RS1_f06		0x00018000	/* source register 1: %f06 */
#define	RS1_f05		0x00014000	/* source register 1: %f05 */
#define	RS1_f04		0x00010000	/* source register 1: %f04 */
#define	RS1_f03		0x0000C000	/* source register 1: %f03 */
#define	RS1_f02		0x00008000	/* source register 1: %f02 */
#define	RS1_f01		0x00004000	/* source register 1: %f01 */
#define	RS1_f00		0x00000000	/* source register 1: %f00 */
#define	RS2_f31		0x0000001F	/* source register 2: %f31 */
#define	RS2_f30		0x0000001E	/* source register 2: %f30 */
#define	RS2_f29		0x0000001D	/* source register 2: %f29 */
#define	RS2_f28		0x0000001C	/* source register 2: %f28 */
#define	RS2_f27		0x0000001B	/* source register 2: %f27 */
#define	RS2_f26		0x0000001A	/* source register 2: %f26 */
#define	RS2_f25		0x00000019	/* source register 2: %f25 */
#define	RS2_f24		0x00000018	/* source register 2: %f24 */
#define	RS2_f23		0x00000017	/* source register 2: %f23 */
#define	RS2_f22		0x00000016	/* source register 2: %f22 */
#define	RS2_f21		0x00000015	/* source register 2: %f21 */
#define	RS2_f20		0x00000014	/* source register 2: %f20 */
#define	RS2_f19		0x00000013	/* source register 2: %f19 */
#define	RS2_f18		0x00000012	/* source register 2: %f18 */
#define	RS2_f17		0x00000011	/* source register 2: %f17 */
#define	RS2_f16		0x00000010	/* source register 2: %f16 */
#define	RS2_f15		0x0000000F	/* source register 2: %f15 */
#define	RS2_f14		0x0000000E	/* source register 2: %f14 */
#define	RS2_f13		0x0000000D	/* source register 2: %f13 */
#define	RS2_f12		0x0000000C	/* source register 2: %f12 */
#define	RS2_f11		0x0000000B	/* source register 2: %f11 */
#define	RS2_f10		0x0000000A	/* source register 2: %f10 */
#define	RS2_f09		0x00000009	/* source register 2: %f09 */
#define	RS2_f08		0x00000008	/* source register 2: %f08 */
#define	RS2_f07		0x00000007	/* source register 2: %f07 */
#define	RS2_f06		0x00000006	/* source register 2: %f06 */
#define	RS2_f05		0x00000005	/* source register 2: %f05 */
#define	RS2_f04		0x00000004	/* source register 2: %f04 */
#define	RS2_f03		0x00000003	/* source register 2: %f03 */
#define	RS2_f02		0x00000002	/* source register 2: %f02 */
#define	RS2_f01		0x00000001	/* source register 2: %f01 */
#define	RS2_f00		0x00000000	/* source register 2: %f00 */

/* instruction fields: miscellaneous equates */

#define	A_1		0x20000000	/* annul bit on */
#define	A_0		0x00000000	/* annul bit off */
#define	COND_F		0x1E000000	/* test condition F */
#define	COND_E		0x1C000000	/* test condition E */
#define	COND_D		0x1A000000	/* test condition D */
#define	COND_C		0x18000000	/* test condition C */
#define	COND_B		0x16000000	/* test condition B */
#define	COND_A		0x14000000	/* test condition A */
#define	COND_9		0x12000000	/* test condition 9 */
#define	COND_8		0x10000000	/* test condition 8 */
#define	COND_7		0x0E000000	/* test condition 7 */
#define	COND_6		0x0C000000	/* test condition 6 */
#define	COND_5		0x0A000000	/* test condition 5 */
#define	COND_4		0x08000000	/* test condition 4 */
#define	COND_3		0x06000000	/* test condition 3 */
#define	COND_2		0x04000000	/* test condition 2 */
#define	COND_1		0x02000000	/* test condition 1 */
#define	COND_0		0x00000000	/* test condition 0 */
#define	I_1		0x00002000	/* second ALU operand is simm13 */
#define	I_0		0x00000000	/* second ALU operand is rs2 and possibly ASI */
#define	ASI_SUPER_D	0x00000160	/* alternate address space: supervisor data */
#define	ASI_USER_D	0x00000140	/* alternate address space: user data */
#define	ASI_SUPER_I	0x00000120	/* alternate address space: supervisor instruction */
#define	ASI_USER_I	0x00000100	/* alternate address space: user instruction */


/* instruction types */

/*	Listed in order of first occurrence in dsmLib_sparc.c. */
/*	Note the reversal of where you would think formats 1 & 2 should be. */

/* instruction types: instruction format 2 (OP_0: Bicc, FBfcc, CBccc, SETHI) */

#define	itUnimp			0x00		/* unimplemented instruction */
#define	itBranch		0x01		/* branch instructions */
#define	itNop			0x02		/* no operation */
#define	itSethi			0x03		/* SETHI instruction */

/* instruction types: instruction format 1 (OP_1: Call)  */

#define	itCall			0x10		/* CALL disp30 */

/* instruction types: instruction format 3 (OP_2: arithmetic, etc.) */

#define	itArith			0x20		/* arithmetic ops: general case */
#define	itArithRs1SpoofMov	0x21		/* arithmetic ops: special rs1 values */
#define	itArithOrSet		0x22		/* arithmetic ops: special 'or' case */
#define	itArithRs1Spoof		0x23		/* arithmetic ops: special rs1 values */
#define	itArithRs1Rs2Spoof	0x24		/* arithmetic ops: special rs1 and rs2 values */
#define	itArithRs2Spoof		0x25		/* arithmetic ops: special rs2 values */
#define	itArithRdSpoof		0x26		/* arithmetic ops: special rd values */
#define	itArithRs1RdSpoof	0x27		/* arithmetic ops: special rs1 and rd values */
#define	itArithRs2RdSpoof	0x28		/* arithmetic ops: special rs2 and rd values */
#define	itArithRdSpoofCmp	0x29		/* arithmetic ops: special rd values */
#define	itShift			0x30		/* general case shift ops */
#define	itRdY			0x40		/* read from %y */
#define	itRdPsr			0x41		/* read from %psr */
#define	itRdWim			0x42		/* read from %wim */
#define	itRdTbr			0x43		/* read from %tbr */
#define	itWrY			0x44		/* write to %y */
#define	itWrPsr			0x45		/* write to %psr */
#define	itWrWim			0x46		/* write to %wim */
#define	itWrTbr			0x47		/* write to %tbr */
#define	itRdAsr			0x48		/* RDASR */
#define	itWrAsr			0x49		/* WRASR */
#define	itFloat2op		0x50		/* floating point, 2-operand ops */
#define	itFloat3op		0x51		/* floating point, 3-operand ops */
#define	itFloatCompare		0x52		/* floating point, compare ops */
#define	itCpop1			0x60		/* coprocessor operations, class 1 */
#define	itCpop2			0x61		/* coprocessor operations, class 2 */
#define	itRet			0x80		/* return (simple case) */
#define	itJmp			0x81		/* jump */
#define	itJmpl			0x82		/* jump and link */
#define	itRett			0x83		/* return from trap */
#define	itTrap			0x90		/* trap instructions */
#define	itFlush			0xA0		/* flush cache */
#define	itSaveTrivial		0xA1		/* save window */
#define	itSave			0xA2		/* save window */
#define	itRestoreTrivial	0xA3		/* restore window */
#define	itRestore		0xA4		/* restore window */

/* instruction types: instruction format 3 (OP_3: load/store) */

#define	itLd			0xB0		/* general load */
#define	itSt			0xB1		/* general store */
#define	itClr			0xB2		/* store from %g0 */
#define	itSwap			0xB3		/* general swap */
#define	itLdAsi			0xB4		/* load from alternate address space */
#define	itStAsi			0xB5		/* store to alternate address space */
#define	itClrAsi		0xB6		/* store %g0 to alternate address space */
#define	itSwapAsi		0xB7		/* swap with alternate address space */
#define	itLdFreg		0xC0		/* load from floating point register */
#define	itLdFsr			0xC1		/* load from floating point status register */
#define	itStFreg		0xC2		/* store to floating point register */
#define	itStFsr			0xC3		/* store to floating point status register */
#define	itStFq			0xC4		/* store to floating point queue */
#define	itLdCreg		0xC5		/* load from coprocessor register */
#define	itLdCsr			0xC6		/* load from coprocessor status register */
#define	itStCreg		0xC7		/* store to coprocessor register */
#define	itStCsr			0xC8		/* store to coprocessor status register */
#define	itStCq			0xC9		/* store to coprocessor queue */

/* the following structure is not size compatible with the
	one for the Motorola 68k family due to changed word size. */

typedef struct
    {
    char *name;
    unsigned long op;
    unsigned long mask;
    int type;
    } INST;

/* function declarations */

#if defined(__STDC__) || defined(__cplusplus)

IMPORT    int          dsmData (INSTR *binInst, unsigned int address);
IMPORT    int          dsmInst (FAST INSTR *binInst, unsigned int address,
                                VOIDFUNCPTR prtAddress);
IMPORT    int          dsmNbytes (FAST INSTR *binInst);

#else

IMPORT    int          dsmData ();
IMPORT    int          dsmInst ();
IMPORT    int          dsmNbytes ();

#endif  /* __STDC__ */

#ifdef __cplusplus
}
#endif

#endif /* __INCdsmSimsparcLibh */